diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11601,6 +11601,25 @@
 
   SDValue TrueVal = N->getOperand(1);
   SDValue FalseVal = N->getOperand(2);
+  // select(C0, x, select(C1, x, y)) -> select(C0|C1, x, y)
+  if (FalseVal.hasOneUse() && FalseVal.getOpcode() == ISD::SELECT &&
+      FalseVal.getOperand(1) == TrueVal) {
+    EVT VT = N->getValueType(0);
+    SDLoc DL(N);
+    SDValue And =
+        DAG.getNode(ISD::OR, DL, VT, N->getOperand(0), FalseVal.getOperand(0));
+    return DAG.getSelect(DL, VT, And, TrueVal, FalseVal.getOperand(2));
+  }
+  // select(C0, select(C1, x, y), y) -> select(C0&C1, x, y)
+  if (TrueVal.hasOneUse() && TrueVal.getOpcode() == ISD::SELECT &&
+      TrueVal.getOperand(2) == FalseVal) {
+    EVT VT = N->getValueType(0);
+    SDLoc DL(N);
+    SDValue And =
+        DAG.getNode(ISD::AND, DL, VT, N->getOperand(0), FalseVal.getOperand(0));
+    return DAG.getSelect(DL, VT, And, TrueVal.getOperand(1), FalseVal);
+  }
+
   if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false))
     return V;
   return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true);
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
--- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -2092,20 +2092,14 @@
 ; RV32IF-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IF-NEXT:    .cfi_offset ra, -4
 ; RV32IF-NEXT:    call __fixdfdi@plt
-; RV32IF-NEXT:    slti a2, a1, 0
-; RV32IF-NEXT:    beqz a1, .LBB29_2
-; RV32IF-NEXT:  # %bb.1: # %entry
-; RV32IF-NEXT:    addi a3, a2, -1
-; RV32IF-NEXT:    or a0, a3, a0
-; RV32IF-NEXT:  .LBB29_2: # %entry
-; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    slti a2, a1, 1
+; RV32IF-NEXT:    addi a2, a2, -1
+; RV32IF-NEXT:    or a0, a2, a0
+; RV32IF-NEXT:    srai a2, a1, 31
 ; RV32IF-NEXT:    and a1, a2, a1
-; RV32IF-NEXT:    beqz a1, .LBB29_4
-; RV32IF-NEXT:  # %bb.3: # %entry
-; RV32IF-NEXT:    sgtz a1, a1
-; RV32IF-NEXT:    neg a1, a1
+; RV32IF-NEXT:    slti a1, a1, 0
+; RV32IF-NEXT:    addi a1, a1, -1
 ; RV32IF-NEXT:    and a0, a1, a0
-; RV32IF-NEXT:  .LBB29_4: # %entry
 ; RV32IF-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 16
 ; RV32IF-NEXT:    ret
@@ -2386,20 +2380,14 @@
 ; RV32-NEXT:    fmv.x.w a0, fa0
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    call __fixsfdi@plt
-; RV32-NEXT:    slti a2, a1, 0
-; RV32-NEXT:    beqz a1, .LBB35_2
-; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    addi a3, a2, -1
-; RV32-NEXT:    or a0, a3, a0
-; RV32-NEXT:  .LBB35_2: # %entry
-; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    slti a2, a1, 1
+; RV32-NEXT:    addi a2, a2, -1
+; RV32-NEXT:    or a0, a2, a0
+; RV32-NEXT:    srai a2, a1, 31
 ; RV32-NEXT:    and a1, a2, a1
-; RV32-NEXT:    beqz a1, .LBB35_4
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    sgtz a1, a1
-; RV32-NEXT:    neg a1, a1
+; RV32-NEXT:    slti a1, a1, 0
+; RV32-NEXT:    addi a1, a1, -1
 ; RV32-NEXT:    and a0, a1, a0
-; RV32-NEXT:  .LBB35_4: # %entry
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
@@ -2942,87 +2930,71 @@
 ; RV32IF-NEXT:    mv a1, a0
 ; RV32IF-NEXT:    addi a0, sp, 8
 ; RV32IF-NEXT:    call __fixdfti@plt
-; RV32IF-NEXT:    lw a0, 20(sp)
-; RV32IF-NEXT:    lw t0, 8(sp)
-; RV32IF-NEXT:    lw a4, 12(sp)
-; RV32IF-NEXT:    lw a1, 16(sp)
-; RV32IF-NEXT:    lui a3, 524288
-; RV32IF-NEXT:    addi a6, a3, -1
-; RV32IF-NEXT:    mv a2, t0
-; RV32IF-NEXT:    beq a4, a6, .LBB45_2
+; RV32IF-NEXT:    lw a1, 20(sp)
+; RV32IF-NEXT:    lw a4, 16(sp)
+; RV32IF-NEXT:    lw a2, 8(sp)
+; RV32IF-NEXT:    lw a0, 12(sp)
+; RV32IF-NEXT:    or a6, a4, a1
+; RV32IF-NEXT:    slti a3, a1, 0
+; RV32IF-NEXT:    beqz a6, .LBB45_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
-; RV32IF-NEXT:    sltu a2, a4, a6
-; RV32IF-NEXT:    addi a2, a2, -1
-; RV32IF-NEXT:    or a2, a2, t0
-; RV32IF-NEXT:  .LBB45_2: # %entry
-; RV32IF-NEXT:    or a7, a1, a0
-; RV32IF-NEXT:    slti a5, a0, 0
-; RV32IF-NEXT:    bnez a7, .LBB45_16
-; RV32IF-NEXT:  # %bb.3: # %entry
-; RV32IF-NEXT:    mv t0, a4
-; RV32IF-NEXT:    bgez a0, .LBB45_17
-; RV32IF-NEXT:  .LBB45_4: # %entry
-; RV32IF-NEXT:    bgeu a4, a6, .LBB45_18
+; RV32IF-NEXT:    addi a5, a3, -1
+; RV32IF-NEXT:    j .LBB45_3
+; RV32IF-NEXT:  .LBB45_2:
+; RV32IF-NEXT:    srai a5, a0, 31
+; RV32IF-NEXT:  .LBB45_3: # %entry
+; RV32IF-NEXT:    or a2, a5, a2
+; RV32IF-NEXT:    lui a5, 524288
+; RV32IF-NEXT:    addi t0, a5, -1
+; RV32IF-NEXT:    mv a7, a0
+; RV32IF-NEXT:    bgez a1, .LBB45_13
+; RV32IF-NEXT:  # %bb.4: # %entry
+; RV32IF-NEXT:    bgeu a0, t0, .LBB45_14
 ; RV32IF-NEXT:  .LBB45_5: # %entry
-; RV32IF-NEXT:    beqz a7, .LBB45_7
+; RV32IF-NEXT:    beqz a6, .LBB45_7
 ; RV32IF-NEXT:  .LBB45_6: # %entry
-; RV32IF-NEXT:    mv a4, t0
+; RV32IF-NEXT:    mv a0, a7
 ; RV32IF-NEXT:  .LBB45_7: # %entry
-; RV32IF-NEXT:    srai a6, a0, 31
-; RV32IF-NEXT:    and a1, a6, a1
-; RV32IF-NEXT:    seqz a6, a0
-; RV32IF-NEXT:    neg a5, a5
-; RV32IF-NEXT:    and a5, a5, a0
-; RV32IF-NEXT:    addi a6, a6, -1
-; RV32IF-NEXT:    mv a0, a4
-; RV32IF-NEXT:    bgez a5, .LBB45_9
+; RV32IF-NEXT:    srai a6, a1, 31
+; RV32IF-NEXT:    and a6, a6, a4
+; RV32IF-NEXT:    seqz a7, a1
+; RV32IF-NEXT:    neg a4, a3
+; RV32IF-NEXT:    and a4, a4, a1
+; RV32IF-NEXT:    addi a1, a7, -1
+; RV32IF-NEXT:    mv a3, a0
+; RV32IF-NEXT:    bgez a4, .LBB45_9
 ; RV32IF-NEXT:  # %bb.8: # %entry
-; RV32IF-NEXT:    lui a0, 524288
+; RV32IF-NEXT:    lui a3, 524288
 ; RV32IF-NEXT:  .LBB45_9: # %entry
-; RV32IF-NEXT:    and a6, a6, a1
-; RV32IF-NEXT:    mv a1, a4
-; RV32IF-NEXT:    bltu a3, a4, .LBB45_11
+; RV32IF-NEXT:    and a6, a1, a6
+; RV32IF-NEXT:    mv a1, a0
+; RV32IF-NEXT:    bltu a5, a0, .LBB45_11
 ; RV32IF-NEXT:  # %bb.10: # %entry
 ; RV32IF-NEXT:    lui a1, 524288
 ; RV32IF-NEXT:  .LBB45_11: # %entry
-; RV32IF-NEXT:    and a6, a6, a5
-; RV32IF-NEXT:    li a7, -1
-; RV32IF-NEXT:    bne a6, a7, .LBB45_19
+; RV32IF-NEXT:    and a5, a6, a4
+; RV32IF-NEXT:    li a6, -1
+; RV32IF-NEXT:    beq a5, a6, .LBB45_15
 ; RV32IF-NEXT:  # %bb.12: # %entry
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    bne a4, a3, .LBB45_20
+; RV32IF-NEXT:    slti a0, a4, 0
+; RV32IF-NEXT:    addi a0, a0, -1
+; RV32IF-NEXT:    and a0, a0, a2
+; RV32IF-NEXT:    mv a1, a3
+; RV32IF-NEXT:    j .LBB45_16
 ; RV32IF-NEXT:  .LBB45_13: # %entry
-; RV32IF-NEXT:    beq a6, a7, .LBB45_15
+; RV32IF-NEXT:    mv a7, t0
+; RV32IF-NEXT:    bltu a0, t0, .LBB45_5
 ; RV32IF-NEXT:  .LBB45_14: # %entry
-; RV32IF-NEXT:    slti a0, a5, 0
-; RV32IF-NEXT:    addi a0, a0, -1
+; RV32IF-NEXT:    mv a0, t0
+; RV32IF-NEXT:    bnez a6, .LBB45_6
+; RV32IF-NEXT:    j .LBB45_7
+; RV32IF-NEXT:  .LBB45_15:
+; RV32IF-NEXT:    srai a0, a0, 31
 ; RV32IF-NEXT:    and a0, a0, a2
-; RV32IF-NEXT:  .LBB45_15: # %entry
+; RV32IF-NEXT:  .LBB45_16: # %entry
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
-; RV32IF-NEXT:  .LBB45_16: # %entry
-; RV32IF-NEXT:    addi a2, a5, -1
-; RV32IF-NEXT:    or a2, a2, t0
-; RV32IF-NEXT:    mv t0, a4
-; RV32IF-NEXT:    bltz a0, .LBB45_4
-; RV32IF-NEXT:  .LBB45_17: # %entry
-; RV32IF-NEXT:    mv t0, a6
-; RV32IF-NEXT:    bltu a4, a6, .LBB45_5
-; RV32IF-NEXT:  .LBB45_18: # %entry
-; RV32IF-NEXT:    mv a4, a6
-; RV32IF-NEXT:    bnez a7, .LBB45_6
-; RV32IF-NEXT:    j .LBB45_7
-; RV32IF-NEXT:  .LBB45_19: # %entry
-; RV32IF-NEXT:    mv a1, a0
-; RV32IF-NEXT:    mv a0, a2
-; RV32IF-NEXT:    beq a4, a3, .LBB45_13
-; RV32IF-NEXT:  .LBB45_20: # %entry
-; RV32IF-NEXT:    sltu a0, a3, a4
-; RV32IF-NEXT:    neg a0, a0
-; RV32IF-NEXT:    and a0, a0, a2
-; RV32IF-NEXT:    bne a6, a7, .LBB45_14
-; RV32IF-NEXT:    j .LBB45_15
 ;
 ; RV64IF-LABEL: stest_f64i64_mm:
 ; RV64IF:       # %bb.0: # %entry
@@ -3080,87 +3052,71 @@
 ; RV32IFD-NEXT:    .cfi_offset ra, -4
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call __fixdfti@plt
-; RV32IFD-NEXT:    lw a0, 20(sp)
-; RV32IFD-NEXT:    lw t0, 8(sp)
-; RV32IFD-NEXT:    lw a4, 12(sp)
-; RV32IFD-NEXT:    lw a1, 16(sp)
-; RV32IFD-NEXT:    lui a3, 524288
-; RV32IFD-NEXT:    addi a6, a3, -1
-; RV32IFD-NEXT:    mv a2, t0
-; RV32IFD-NEXT:    beq a4, a6, .LBB45_2
+; RV32IFD-NEXT:    lw a1, 20(sp)
+; RV32IFD-NEXT:    lw a4, 16(sp)
+; RV32IFD-NEXT:    lw a2, 8(sp)
+; RV32IFD-NEXT:    lw a0, 12(sp)
+; RV32IFD-NEXT:    or a6, a4, a1
+; RV32IFD-NEXT:    slti a3, a1, 0
+; RV32IFD-NEXT:    beqz a6, .LBB45_2
 ; RV32IFD-NEXT:  # %bb.1: # %entry
-; RV32IFD-NEXT:    sltu a2, a4, a6
-; RV32IFD-NEXT:    addi a2, a2, -1
-; RV32IFD-NEXT:    or a2, a2, t0
-; RV32IFD-NEXT:  .LBB45_2: # %entry
-; RV32IFD-NEXT:    or a7, a1, a0
-; RV32IFD-NEXT:    slti a5, a0, 0
-; RV32IFD-NEXT:    bnez a7, .LBB45_16
-; RV32IFD-NEXT:  # %bb.3: # %entry
-; RV32IFD-NEXT:    mv t0, a4
-; RV32IFD-NEXT:    bgez a0, .LBB45_17
-; RV32IFD-NEXT:  .LBB45_4: # %entry
-; RV32IFD-NEXT:    bgeu a4, a6, .LBB45_18
+; RV32IFD-NEXT:    addi a5, a3, -1
+; RV32IFD-NEXT:    j .LBB45_3
+; RV32IFD-NEXT:  .LBB45_2:
+; RV32IFD-NEXT:    srai a5, a0, 31
+; RV32IFD-NEXT:  .LBB45_3: # %entry
+; RV32IFD-NEXT:    or a2, a5, a2
+; RV32IFD-NEXT:    lui a5, 524288
+; RV32IFD-NEXT:    addi t0, a5, -1
+; RV32IFD-NEXT:    mv a7, a0
+; RV32IFD-NEXT:    bgez a1, .LBB45_13
+; RV32IFD-NEXT:  # %bb.4: # %entry
+; RV32IFD-NEXT:    bgeu a0, t0, .LBB45_14
 ; RV32IFD-NEXT:  .LBB45_5: # %entry
-; RV32IFD-NEXT:    beqz a7, .LBB45_7
+; RV32IFD-NEXT:    beqz a6, .LBB45_7
 ; RV32IFD-NEXT:  .LBB45_6: # %entry
-; RV32IFD-NEXT:    mv a4, t0
+; RV32IFD-NEXT:    mv a0, a7
 ; RV32IFD-NEXT:  .LBB45_7: # %entry
-; RV32IFD-NEXT:    srai a6, a0, 31
-; RV32IFD-NEXT:    and a1, a6, a1
-; RV32IFD-NEXT:    seqz a6, a0
-; RV32IFD-NEXT:    neg a5, a5
-; RV32IFD-NEXT:    and a5, a5, a0
-; RV32IFD-NEXT:    addi a6, a6, -1
-; RV32IFD-NEXT:    mv a0, a4
-; RV32IFD-NEXT:    bgez a5, .LBB45_9
+; RV32IFD-NEXT:    srai a6, a1, 31
+; RV32IFD-NEXT:    and a6, a6, a4
+; RV32IFD-NEXT:    seqz a7, a1
+; RV32IFD-NEXT:    neg a4, a3
+; RV32IFD-NEXT:    and a4, a4, a1
+; RV32IFD-NEXT:    addi a1, a7, -1
+; RV32IFD-NEXT:    mv a3, a0
+; RV32IFD-NEXT:    bgez a4, .LBB45_9
 ; RV32IFD-NEXT:  # %bb.8: # %entry
-; RV32IFD-NEXT:    lui a0, 524288
+; RV32IFD-NEXT:    lui a3, 524288
 ; RV32IFD-NEXT:  .LBB45_9: # %entry
-; RV32IFD-NEXT:    and a6, a6, a1
-; RV32IFD-NEXT:    mv a1, a4
-; RV32IFD-NEXT:    bltu a3, a4, .LBB45_11
+; RV32IFD-NEXT:    and a6, a1, a6
+; RV32IFD-NEXT:    mv a1, a0
+; RV32IFD-NEXT:    bltu a5, a0, .LBB45_11
 ; RV32IFD-NEXT:  # %bb.10: # %entry
 ; RV32IFD-NEXT:    lui a1, 524288
 ; RV32IFD-NEXT:  .LBB45_11: # %entry
-; RV32IFD-NEXT:    and a6, a6, a5
-; RV32IFD-NEXT:    li a7, -1
-; RV32IFD-NEXT:    bne a6, a7, .LBB45_19
+; RV32IFD-NEXT:    and a5, a6, a4
+; RV32IFD-NEXT:    li a6, -1
+; RV32IFD-NEXT:    beq a5, a6, .LBB45_15
 ; RV32IFD-NEXT:  # %bb.12: # %entry
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    bne a4, a3, .LBB45_20
+; RV32IFD-NEXT:    slti a0, a4, 0
+; RV32IFD-NEXT:    addi a0, a0, -1
+; RV32IFD-NEXT:    and a0, a0, a2
+; RV32IFD-NEXT:    mv a1, a3
+; RV32IFD-NEXT:    j .LBB45_16
 ; RV32IFD-NEXT:  .LBB45_13: # %entry
-; RV32IFD-NEXT:    beq a6, a7, .LBB45_15
+; RV32IFD-NEXT:    mv a7, t0
+; RV32IFD-NEXT:    bltu a0, t0, .LBB45_5
 ; RV32IFD-NEXT:  .LBB45_14: # %entry
-; RV32IFD-NEXT:    slti a0, a5, 0
-; RV32IFD-NEXT:    addi a0, a0, -1
+; RV32IFD-NEXT:    mv a0, t0
+; RV32IFD-NEXT:    bnez a6, .LBB45_6
+; RV32IFD-NEXT:    j .LBB45_7
+; RV32IFD-NEXT:  .LBB45_15:
+; RV32IFD-NEXT:    srai a0, a0, 31
 ; RV32IFD-NEXT:    and a0, a0, a2
-; RV32IFD-NEXT:  .LBB45_15: # %entry
+; RV32IFD-NEXT:  .LBB45_16: # %entry
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
-; RV32IFD-NEXT:  .LBB45_16: # %entry
-; RV32IFD-NEXT:    addi a2, a5, -1
-; RV32IFD-NEXT:    or a2, a2, t0
-; RV32IFD-NEXT:    mv t0, a4
-; RV32IFD-NEXT:    bltz a0, .LBB45_4
-; RV32IFD-NEXT:  .LBB45_17: # %entry
-; RV32IFD-NEXT:    mv t0, a6
-; RV32IFD-NEXT:    bltu a4, a6, .LBB45_5
-; RV32IFD-NEXT:  .LBB45_18: # %entry
-; RV32IFD-NEXT:    mv a4, a6
-; RV32IFD-NEXT:    bnez a7, .LBB45_6
-; RV32IFD-NEXT:    j .LBB45_7
-; RV32IFD-NEXT:  .LBB45_19: # %entry
-; RV32IFD-NEXT:    mv a1, a0
-; RV32IFD-NEXT:    mv a0, a2
-; RV32IFD-NEXT:    beq a4, a3, .LBB45_13
-; RV32IFD-NEXT:  .LBB45_20: # %entry
-; RV32IFD-NEXT:    sltu a0, a3, a4
-; RV32IFD-NEXT:    neg a0, a0
-; RV32IFD-NEXT:    and a0, a0, a2
-; RV32IFD-NEXT:    bne a6, a7, .LBB45_14
-; RV32IFD-NEXT:    j .LBB45_15
 ;
 ; RV64IFD-LABEL: stest_f64i64_mm:
 ; RV64IFD:       # %bb.0: # %entry
@@ -3270,63 +3226,56 @@
 ; RV32IF-NEXT:    mv a1, a0
 ; RV32IF-NEXT:    addi a0, sp, 8
 ; RV32IF-NEXT:    call __fixdfti@plt
-; RV32IF-NEXT:    lw a1, 16(sp)
-; RV32IF-NEXT:    lw a0, 20(sp)
-; RV32IF-NEXT:    li a3, 1
-; RV32IF-NEXT:    mv a6, a1
-; RV32IF-NEXT:    bltz a0, .LBB47_2
+; RV32IF-NEXT:    lw a1, 20(sp)
+; RV32IF-NEXT:    lw a0, 16(sp)
+; RV32IF-NEXT:    slti a2, a1, 0
+; RV32IF-NEXT:    beqz a1, .LBB47_2
 ; RV32IF-NEXT:  # %bb.1: # %entry
+; RV32IF-NEXT:    mv a4, a2
+; RV32IF-NEXT:    j .LBB47_3
+; RV32IF-NEXT:  .LBB47_2:
+; RV32IF-NEXT:    seqz a4, a0
+; RV32IF-NEXT:  .LBB47_3: # %entry
+; RV32IF-NEXT:    xori a3, a0, 1
+; RV32IF-NEXT:    or a7, a3, a1
 ; RV32IF-NEXT:    li a6, 1
-; RV32IF-NEXT:  .LBB47_2: # %entry
-; RV32IF-NEXT:    mv a2, a1
-; RV32IF-NEXT:    bltu a1, a3, .LBB47_4
-; RV32IF-NEXT:  # %bb.3: # %entry
-; RV32IF-NEXT:    li a2, 1
-; RV32IF-NEXT:  .LBB47_4: # %entry
-; RV32IF-NEXT:    lw a4, 12(sp)
-; RV32IF-NEXT:    lw a3, 8(sp)
-; RV32IF-NEXT:    slti a5, a0, 0
-; RV32IF-NEXT:    beqz a0, .LBB47_6
-; RV32IF-NEXT:  # %bb.5: # %entry
-; RV32IF-NEXT:    mv a2, a6
-; RV32IF-NEXT:    mv a6, a5
-; RV32IF-NEXT:    j .LBB47_7
-; RV32IF-NEXT:  .LBB47_6:
-; RV32IF-NEXT:    seqz a6, a1
+; RV32IF-NEXT:    mv a3, a0
+; RV32IF-NEXT:    bltz a1, .LBB47_5
+; RV32IF-NEXT:  # %bb.4: # %entry
+; RV32IF-NEXT:    li a3, 1
+; RV32IF-NEXT:  .LBB47_5: # %entry
+; RV32IF-NEXT:    lw a5, 8(sp)
+; RV32IF-NEXT:    lw t1, 12(sp)
+; RV32IF-NEXT:    neg t0, a4
+; RV32IF-NEXT:    seqz a4, a7
+; RV32IF-NEXT:    bltu a0, a6, .LBB47_7
+; RV32IF-NEXT:  # %bb.6: # %entry
+; RV32IF-NEXT:    li a0, 1
 ; RV32IF-NEXT:  .LBB47_7: # %entry
-; RV32IF-NEXT:    neg a6, a6
-; RV32IF-NEXT:    and a3, a6, a3
-; RV32IF-NEXT:    xori a1, a1, 1
-; RV32IF-NEXT:    or a1, a1, a0
-; RV32IF-NEXT:    seqz a1, a1
-; RV32IF-NEXT:    addi a1, a1, -1
-; RV32IF-NEXT:    and a3, a1, a3
-; RV32IF-NEXT:    and a4, a6, a4
-; RV32IF-NEXT:    and a1, a1, a4
-; RV32IF-NEXT:    neg a4, a5
-; RV32IF-NEXT:    and a4, a4, a0
-; RV32IF-NEXT:    mv a0, a3
+; RV32IF-NEXT:    and a6, t0, t1
+; RV32IF-NEXT:    addi a4, a4, -1
+; RV32IF-NEXT:    and a5, t0, a5
 ; RV32IF-NEXT:    beqz a1, .LBB47_9
 ; RV32IF-NEXT:  # %bb.8: # %entry
-; RV32IF-NEXT:    seqz a0, a1
-; RV32IF-NEXT:    addi a0, a0, -1
-; RV32IF-NEXT:    and a0, a0, a3
+; RV32IF-NEXT:    mv a0, a3
 ; RV32IF-NEXT:  .LBB47_9: # %entry
-; RV32IF-NEXT:    beqz a4, .LBB47_11
+; RV32IF-NEXT:    and a3, a4, a6
+; RV32IF-NEXT:    neg a2, a2
+; RV32IF-NEXT:    and a2, a2, a1
+; RV32IF-NEXT:    and a1, a4, a5
+; RV32IF-NEXT:    beqz a2, .LBB47_11
 ; RV32IF-NEXT:  # %bb.10: # %entry
-; RV32IF-NEXT:    sgtz a5, a4
-; RV32IF-NEXT:    or a2, a2, a4
-; RV32IF-NEXT:    bnez a2, .LBB47_12
-; RV32IF-NEXT:    j .LBB47_13
+; RV32IF-NEXT:    sgtz a4, a2
+; RV32IF-NEXT:    j .LBB47_12
 ; RV32IF-NEXT:  .LBB47_11:
-; RV32IF-NEXT:    snez a5, a2
-; RV32IF-NEXT:    or a2, a2, a4
-; RV32IF-NEXT:    beqz a2, .LBB47_13
+; RV32IF-NEXT:    snez a4, a0
 ; RV32IF-NEXT:  .LBB47_12: # %entry
-; RV32IF-NEXT:    neg a2, a5
-; RV32IF-NEXT:    and a0, a2, a3
-; RV32IF-NEXT:    and a1, a2, a1
-; RV32IF-NEXT:  .LBB47_13: # %entry
+; RV32IF-NEXT:    or a0, a0, a2
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    or a0, a0, a4
+; RV32IF-NEXT:    neg a2, a0
+; RV32IF-NEXT:    and a0, a2, a1
+; RV32IF-NEXT:    and a1, a2, a3
 ; RV32IF-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IF-NEXT:    addi sp, sp, 32
 ; RV32IF-NEXT:    ret
@@ -3350,12 +3299,9 @@
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:    beqz a2, .LBB47_4
-; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a2
-; RV64-NEXT:    neg a1, a1
+; RV64-NEXT:    slti a1, a2, 0
+; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:  .LBB47_4: # %entry
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
@@ -3368,63 +3314,56 @@
 ; RV32IFD-NEXT:    .cfi_offset ra, -4
 ; RV32IFD-NEXT:    addi a0, sp, 8
 ; RV32IFD-NEXT:    call __fixdfti@plt
-; RV32IFD-NEXT:    lw a1, 16(sp)
-; RV32IFD-NEXT:    lw a0, 20(sp)
-; RV32IFD-NEXT:    li a3, 1
-; RV32IFD-NEXT:    mv a6, a1
-; RV32IFD-NEXT:    bltz a0, .LBB47_2
+; RV32IFD-NEXT:    lw a1, 20(sp)
+; RV32IFD-NEXT:    lw a0, 16(sp)
+; RV32IFD-NEXT:    slti a2, a1, 0
+; RV32IFD-NEXT:    beqz a1, .LBB47_2
 ; RV32IFD-NEXT:  # %bb.1: # %entry
+; RV32IFD-NEXT:    mv a4, a2
+; RV32IFD-NEXT:    j .LBB47_3
+; RV32IFD-NEXT:  .LBB47_2:
+; RV32IFD-NEXT:    seqz a4, a0
+; RV32IFD-NEXT:  .LBB47_3: # %entry
+; RV32IFD-NEXT:    xori a3, a0, 1
+; RV32IFD-NEXT:    or a7, a3, a1
 ; RV32IFD-NEXT:    li a6, 1
-; RV32IFD-NEXT:  .LBB47_2: # %entry
-; RV32IFD-NEXT:    mv a2, a1
-; RV32IFD-NEXT:    bltu a1, a3, .LBB47_4
-; RV32IFD-NEXT:  # %bb.3: # %entry
-; RV32IFD-NEXT:    li a2, 1
-; RV32IFD-NEXT:  .LBB47_4: # %entry
-; RV32IFD-NEXT:    lw a4, 12(sp)
-; RV32IFD-NEXT:    lw a3, 8(sp)
-; RV32IFD-NEXT:    slti a5, a0, 0
-; RV32IFD-NEXT:    beqz a0, .LBB47_6
-; RV32IFD-NEXT:  # %bb.5: # %entry
-; RV32IFD-NEXT:    mv a2, a6
-; RV32IFD-NEXT:    mv a6, a5
-; RV32IFD-NEXT:    j .LBB47_7
-; RV32IFD-NEXT:  .LBB47_6:
-; RV32IFD-NEXT:    seqz a6, a1
+; RV32IFD-NEXT:    mv a3, a0
+; RV32IFD-NEXT:    bltz a1, .LBB47_5
+; RV32IFD-NEXT:  # %bb.4: # %entry
+; RV32IFD-NEXT:    li a3, 1
+; RV32IFD-NEXT:  .LBB47_5: # %entry
+; RV32IFD-NEXT:    lw a5, 8(sp)
+; RV32IFD-NEXT:    lw t1, 12(sp)
+; RV32IFD-NEXT:    neg t0, a4
+; RV32IFD-NEXT:    seqz a4, a7
+; RV32IFD-NEXT:    bltu a0, a6, .LBB47_7
+; RV32IFD-NEXT:  # %bb.6: # %entry
+; RV32IFD-NEXT:    li a0, 1
 ; RV32IFD-NEXT:  .LBB47_7: # %entry
-; RV32IFD-NEXT:    neg a6, a6
-; RV32IFD-NEXT:    and a3, a6, a3
-; RV32IFD-NEXT:    xori a1, a1, 1
-; RV32IFD-NEXT:    or a1, a1, a0
-; RV32IFD-NEXT:    seqz a1, a1
-; RV32IFD-NEXT:    addi a1, a1, -1
-; RV32IFD-NEXT:    and a3, a1, a3
-; RV32IFD-NEXT:    and a4, a6, a4
-; RV32IFD-NEXT:    and a1, a1, a4
-; RV32IFD-NEXT:    neg a4, a5
-; RV32IFD-NEXT:    and a4, a4, a0
-; RV32IFD-NEXT:    mv a0, a3
+; RV32IFD-NEXT:    and a6, t0, t1
+; RV32IFD-NEXT:    addi a4, a4, -1
+; RV32IFD-NEXT:    and a5, t0, a5
 ; RV32IFD-NEXT:    beqz a1, .LBB47_9
 ; RV32IFD-NEXT:  # %bb.8: # %entry
-; RV32IFD-NEXT:    seqz a0, a1
-; RV32IFD-NEXT:    addi a0, a0, -1
-; RV32IFD-NEXT:    and a0, a0, a3
+; RV32IFD-NEXT:    mv a0, a3
 ; RV32IFD-NEXT:  .LBB47_9: # %entry
-; RV32IFD-NEXT:    beqz a4, .LBB47_11
+; RV32IFD-NEXT:    and a3, a4, a6
+; RV32IFD-NEXT:    neg a2, a2
+; RV32IFD-NEXT:    and a2, a2, a1
+; RV32IFD-NEXT:    and a1, a4, a5
+; RV32IFD-NEXT:    beqz a2, .LBB47_11
 ; RV32IFD-NEXT:  # %bb.10: # %entry
-; RV32IFD-NEXT:    sgtz a5, a4
-; RV32IFD-NEXT:    or a2, a2, a4
-; RV32IFD-NEXT:    bnez a2, .LBB47_12
-; RV32IFD-NEXT:    j .LBB47_13
+; RV32IFD-NEXT:    sgtz a4, a2
+; RV32IFD-NEXT:    j .LBB47_12
 ; RV32IFD-NEXT:  .LBB47_11:
-; RV32IFD-NEXT:    snez a5, a2
-; RV32IFD-NEXT:    or a2, a2, a4
-; RV32IFD-NEXT:    beqz a2, .LBB47_13
+; RV32IFD-NEXT:    snez a4, a0
 ; RV32IFD-NEXT:  .LBB47_12: # %entry
-; RV32IFD-NEXT:    neg a2, a5
-; RV32IFD-NEXT:    and a0, a2, a3
-; RV32IFD-NEXT:    and a1, a2, a1
-; RV32IFD-NEXT:  .LBB47_13: # %entry
+; RV32IFD-NEXT:    or a0, a0, a2
+; RV32IFD-NEXT:    seqz a0, a0
+; RV32IFD-NEXT:    or a0, a0, a4
+; RV32IFD-NEXT:    neg a2, a0
+; RV32IFD-NEXT:    and a0, a2, a1
+; RV32IFD-NEXT:    and a1, a2, a3
 ; RV32IFD-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32IFD-NEXT:    addi sp, sp, 32
 ; RV32IFD-NEXT:    ret
@@ -3445,87 +3384,71 @@
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixsfti@plt
-; RV32-NEXT:    lw a0, 20(sp)
-; RV32-NEXT:    lw t0, 8(sp)
-; RV32-NEXT:    lw a4, 12(sp)
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    lui a3, 524288
-; RV32-NEXT:    addi a6, a3, -1
-; RV32-NEXT:    mv a2, t0
-; RV32-NEXT:    beq a4, a6, .LBB48_2
+; RV32-NEXT:    lw a1, 20(sp)
+; RV32-NEXT:    lw a4, 16(sp)
+; RV32-NEXT:    lw a2, 8(sp)
+; RV32-NEXT:    lw a0, 12(sp)
+; RV32-NEXT:    or a6, a4, a1
+; RV32-NEXT:    slti a3, a1, 0
+; RV32-NEXT:    beqz a6, .LBB48_2
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    sltu a2, a4, a6
-; RV32-NEXT:    addi a2, a2, -1
-; RV32-NEXT:    or a2, a2, t0
-; RV32-NEXT:  .LBB48_2: # %entry
-; RV32-NEXT:    or a7, a1, a0
-; RV32-NEXT:    slti a5, a0, 0
-; RV32-NEXT:    bnez a7, .LBB48_16
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    mv t0, a4
-; RV32-NEXT:    bgez a0, .LBB48_17
-; RV32-NEXT:  .LBB48_4: # %entry
-; RV32-NEXT:    bgeu a4, a6, .LBB48_18
+; RV32-NEXT:    addi a5, a3, -1
+; RV32-NEXT:    j .LBB48_3
+; RV32-NEXT:  .LBB48_2:
+; RV32-NEXT:    srai a5, a0, 31
+; RV32-NEXT:  .LBB48_3: # %entry
+; RV32-NEXT:    or a2, a5, a2
+; RV32-NEXT:    lui a5, 524288
+; RV32-NEXT:    addi t0, a5, -1
+; RV32-NEXT:    mv a7, a0
+; RV32-NEXT:    bgez a1, .LBB48_13
+; RV32-NEXT:  # %bb.4: # %entry
+; RV32-NEXT:    bgeu a0, t0, .LBB48_14
 ; RV32-NEXT:  .LBB48_5: # %entry
-; RV32-NEXT:    beqz a7, .LBB48_7
+; RV32-NEXT:    beqz a6, .LBB48_7
 ; RV32-NEXT:  .LBB48_6: # %entry
-; RV32-NEXT:    mv a4, t0
+; RV32-NEXT:    mv a0, a7
 ; RV32-NEXT:  .LBB48_7: # %entry
-; RV32-NEXT:    srai a6, a0, 31
-; RV32-NEXT:    and a1, a6, a1
-; RV32-NEXT:    seqz a6, a0
-; RV32-NEXT:    neg a5, a5
-; RV32-NEXT:    and a5, a5, a0
-; RV32-NEXT:    addi a6, a6, -1
-; RV32-NEXT:    mv a0, a4
-; RV32-NEXT:    bgez a5, .LBB48_9
+; RV32-NEXT:    srai a6, a1, 31
+; RV32-NEXT:    and a6, a6, a4
+; RV32-NEXT:    seqz a7, a1
+; RV32-NEXT:    neg a4, a3
+; RV32-NEXT:    and a4, a4, a1
+; RV32-NEXT:    addi a1, a7, -1
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    bgez a4, .LBB48_9
 ; RV32-NEXT:  # %bb.8: # %entry
-; RV32-NEXT:    lui a0, 524288
+; RV32-NEXT:    lui a3, 524288
 ; RV32-NEXT:  .LBB48_9: # %entry
-; RV32-NEXT:    and a6, a6, a1
-; RV32-NEXT:    mv a1, a4
-; RV32-NEXT:    bltu a3, a4, .LBB48_11
+; RV32-NEXT:    and a6, a1, a6
+; RV32-NEXT:    mv a1, a0
+; RV32-NEXT:    bltu a5, a0, .LBB48_11
 ; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB48_11: # %entry
-; RV32-NEXT:    and a6, a6, a5
-; RV32-NEXT:    li a7, -1
-; RV32-NEXT:    bne a6, a7, .LBB48_19
+; RV32-NEXT:    and a5, a6, a4
+; RV32-NEXT:    li a6, -1
+; RV32-NEXT:    beq a5, a6, .LBB48_15
 ; RV32-NEXT:  # %bb.12: # %entry
-; RV32-NEXT:    mv a0, a2
-; RV32-NEXT:    bne a4, a3, .LBB48_20
+; RV32-NEXT:    slti a0, a4, 0
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    mv a1, a3
+; RV32-NEXT:    j .LBB48_16
 ; RV32-NEXT:  .LBB48_13: # %entry
-; RV32-NEXT:    beq a6, a7, .LBB48_15
+; RV32-NEXT:    mv a7, t0
+; RV32-NEXT:    bltu a0, t0, .LBB48_5
 ; RV32-NEXT:  .LBB48_14: # %entry
-; RV32-NEXT:    slti a0, a5, 0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    mv a0, t0
+; RV32-NEXT:    bnez a6, .LBB48_6
+; RV32-NEXT:    j .LBB48_7
+; RV32-NEXT:  .LBB48_15:
+; RV32-NEXT:    srai a0, a0, 31
 ; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:  .LBB48_15: # %entry
+; RV32-NEXT:  .LBB48_16: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB48_16: # %entry
-; RV32-NEXT:    addi a2, a5, -1
-; RV32-NEXT:    or a2, a2, t0
-; RV32-NEXT:    mv t0, a4
-; RV32-NEXT:    bltz a0, .LBB48_4
-; RV32-NEXT:  .LBB48_17: # %entry
-; RV32-NEXT:    mv t0, a6
-; RV32-NEXT:    bltu a4, a6, .LBB48_5
-; RV32-NEXT:  .LBB48_18: # %entry
-; RV32-NEXT:    mv a4, a6
-; RV32-NEXT:    bnez a7, .LBB48_6
-; RV32-NEXT:    j .LBB48_7
-; RV32-NEXT:  .LBB48_19: # %entry
-; RV32-NEXT:    mv a1, a0
-; RV32-NEXT:    mv a0, a2
-; RV32-NEXT:    beq a4, a3, .LBB48_13
-; RV32-NEXT:  .LBB48_20: # %entry
-; RV32-NEXT:    sltu a0, a3, a4
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    bne a6, a7, .LBB48_14
-; RV32-NEXT:    j .LBB48_15
 ;
 ; RV64-LABEL: stest_f32i64_mm:
 ; RV64:       # %bb.0: # %entry
@@ -3604,63 +3527,56 @@
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixsfti@plt
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    lw a0, 20(sp)
-; RV32-NEXT:    li a3, 1
-; RV32-NEXT:    mv a6, a1
-; RV32-NEXT:    bltz a0, .LBB50_2
+; RV32-NEXT:    lw a1, 20(sp)
+; RV32-NEXT:    lw a0, 16(sp)
+; RV32-NEXT:    slti a2, a1, 0
+; RV32-NEXT:    beqz a1, .LBB50_2
 ; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    mv a4, a2
+; RV32-NEXT:    j .LBB50_3
+; RV32-NEXT:  .LBB50_2:
+; RV32-NEXT:    seqz a4, a0
+; RV32-NEXT:  .LBB50_3: # %entry
+; RV32-NEXT:    xori a3, a0, 1
+; RV32-NEXT:    or a7, a3, a1
 ; RV32-NEXT:    li a6, 1
-; RV32-NEXT:  .LBB50_2: # %entry
-; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a3, .LBB50_4
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    li a2, 1
-; RV32-NEXT:  .LBB50_4: # %entry
-; RV32-NEXT:    lw a4, 12(sp)
-; RV32-NEXT:    lw a3, 8(sp)
-; RV32-NEXT:    slti a5, a0, 0
-; RV32-NEXT:    beqz a0, .LBB50_6
-; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    mv a2, a6
-; RV32-NEXT:    mv a6, a5
-; RV32-NEXT:    j .LBB50_7
-; RV32-NEXT:  .LBB50_6:
-; RV32-NEXT:    seqz a6, a1
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    bltz a1, .LBB50_5
+; RV32-NEXT:  # %bb.4: # %entry
+; RV32-NEXT:    li a3, 1
+; RV32-NEXT:  .LBB50_5: # %entry
+; RV32-NEXT:    lw a5, 8(sp)
+; RV32-NEXT:    lw t1, 12(sp)
+; RV32-NEXT:    neg t0, a4
+; RV32-NEXT:    seqz a4, a7
+; RV32-NEXT:    bltu a0, a6, .LBB50_7
+; RV32-NEXT:  # %bb.6: # %entry
+; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB50_7: # %entry
-; RV32-NEXT:    neg a6, a6
-; RV32-NEXT:    and a3, a6, a3
-; RV32-NEXT:    xori a1, a1, 1
-; RV32-NEXT:    or a1, a1, a0
-; RV32-NEXT:    seqz a1, a1
-; RV32-NEXT:    addi a1, a1, -1
-; RV32-NEXT:    and a3, a1, a3
-; RV32-NEXT:    and a4, a6, a4
-; RV32-NEXT:    and a1, a1, a4
-; RV32-NEXT:    neg a4, a5
-; RV32-NEXT:    and a4, a4, a0
-; RV32-NEXT:    mv a0, a3
+; RV32-NEXT:    and a6, t0, t1
+; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    and a5, t0, a5
 ; RV32-NEXT:    beqz a1, .LBB50_9
 ; RV32-NEXT:  # %bb.8: # %entry
-; RV32-NEXT:    seqz a0, a1
-; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:  .LBB50_9: # %entry
-; RV32-NEXT:    beqz a4, .LBB50_11
+; RV32-NEXT:    and a3, a4, a6
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a2, a2, a1
+; RV32-NEXT:    and a1, a4, a5
+; RV32-NEXT:    beqz a2, .LBB50_11
 ; RV32-NEXT:  # %bb.10: # %entry
-; RV32-NEXT:    sgtz a5, a4
-; RV32-NEXT:    or a2, a2, a4
-; RV32-NEXT:    bnez a2, .LBB50_12
-; RV32-NEXT:    j .LBB50_13
+; RV32-NEXT:    sgtz a4, a2
+; RV32-NEXT:    j .LBB50_12
 ; RV32-NEXT:  .LBB50_11:
-; RV32-NEXT:    snez a5, a2
-; RV32-NEXT:    or a2, a2, a4
-; RV32-NEXT:    beqz a2, .LBB50_13
+; RV32-NEXT:    snez a4, a0
 ; RV32-NEXT:  .LBB50_12: # %entry
-; RV32-NEXT:    neg a2, a5
-; RV32-NEXT:    and a0, a2, a3
-; RV32-NEXT:    and a1, a2, a1
-; RV32-NEXT:  .LBB50_13: # %entry
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    or a0, a0, a4
+; RV32-NEXT:    neg a2, a0
+; RV32-NEXT:    and a0, a2, a1
+; RV32-NEXT:    and a1, a2, a3
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
@@ -3684,12 +3600,9 @@
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:    beqz a2, .LBB50_4
-; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a2
-; RV64-NEXT:    neg a1, a1
+; RV64-NEXT:    slti a1, a2, 0
+; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:  .LBB50_4: # %entry
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
@@ -3712,87 +3625,71 @@
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixsfti@plt
-; RV32-NEXT:    lw a0, 20(sp)
-; RV32-NEXT:    lw t0, 8(sp)
-; RV32-NEXT:    lw a4, 12(sp)
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    lui a3, 524288
-; RV32-NEXT:    addi a6, a3, -1
-; RV32-NEXT:    mv a2, t0
-; RV32-NEXT:    beq a4, a6, .LBB51_2
+; RV32-NEXT:    lw a1, 20(sp)
+; RV32-NEXT:    lw a4, 16(sp)
+; RV32-NEXT:    lw a2, 8(sp)
+; RV32-NEXT:    lw a0, 12(sp)
+; RV32-NEXT:    or a6, a4, a1
+; RV32-NEXT:    slti a3, a1, 0
+; RV32-NEXT:    beqz a6, .LBB51_2
 ; RV32-NEXT:  # %bb.1: # %entry
-; RV32-NEXT:    sltu a2, a4, a6
-; RV32-NEXT:    addi a2, a2, -1
-; RV32-NEXT:    or a2, a2, t0
-; RV32-NEXT:  .LBB51_2: # %entry
-; RV32-NEXT:    or a7, a1, a0
-; RV32-NEXT:    slti a5, a0, 0
-; RV32-NEXT:    bnez a7, .LBB51_16
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    mv t0, a4
-; RV32-NEXT:    bgez a0, .LBB51_17
-; RV32-NEXT:  .LBB51_4: # %entry
-; RV32-NEXT:    bgeu a4, a6, .LBB51_18
+; RV32-NEXT:    addi a5, a3, -1
+; RV32-NEXT:    j .LBB51_3
+; RV32-NEXT:  .LBB51_2:
+; RV32-NEXT:    srai a5, a0, 31
+; RV32-NEXT:  .LBB51_3: # %entry
+; RV32-NEXT:    or a2, a5, a2
+; RV32-NEXT:    lui a5, 524288
+; RV32-NEXT:    addi t0, a5, -1
+; RV32-NEXT:    mv a7, a0
+; RV32-NEXT:    bgez a1, .LBB51_13
+; RV32-NEXT:  # %bb.4: # %entry
+; RV32-NEXT:    bgeu a0, t0, .LBB51_14
 ; RV32-NEXT:  .LBB51_5: # %entry
-; RV32-NEXT:    beqz a7, .LBB51_7
+; RV32-NEXT:    beqz a6, .LBB51_7
 ; RV32-NEXT:  .LBB51_6: # %entry
-; RV32-NEXT:    mv a4, t0
+; RV32-NEXT:    mv a0, a7
 ; RV32-NEXT:  .LBB51_7: # %entry
-; RV32-NEXT:    srai a6, a0, 31
-; RV32-NEXT:    and a1, a6, a1
-; RV32-NEXT:    seqz a6, a0
-; RV32-NEXT:    neg a5, a5
-; RV32-NEXT:    and a5, a5, a0
-; RV32-NEXT:    addi a6, a6, -1
-; RV32-NEXT:    mv a0, a4
-; RV32-NEXT:    bgez a5, .LBB51_9
+; RV32-NEXT:    srai a6, a1, 31
+; RV32-NEXT:    and a6, a6, a4
+; RV32-NEXT:    seqz a7, a1
+; RV32-NEXT:    neg a4, a3
+; RV32-NEXT:    and a4, a4, a1
+; RV32-NEXT:    addi a1, a7, -1
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    bgez a4, .LBB51_9
 ; RV32-NEXT:  # %bb.8: # %entry
-; RV32-NEXT:    lui a0, 524288
+; RV32-NEXT:    lui a3, 524288
 ; RV32-NEXT:  .LBB51_9: # %entry
-; RV32-NEXT:    and a6, a6, a1
-; RV32-NEXT:    mv a1, a4
-; RV32-NEXT:    bltu a3, a4, .LBB51_11
+; RV32-NEXT:    and a6, a1, a6
+; RV32-NEXT:    mv a1, a0
+; RV32-NEXT:    bltu a5, a0, .LBB51_11
 ; RV32-NEXT:  # %bb.10: # %entry
 ; RV32-NEXT:    lui a1, 524288
 ; RV32-NEXT:  .LBB51_11: # %entry
-; RV32-NEXT:    and a6, a6, a5
-; RV32-NEXT:    li a7, -1
-; RV32-NEXT:    bne a6, a7, .LBB51_19
+; RV32-NEXT:    and a5, a6, a4
+; RV32-NEXT:    li a6, -1
+; RV32-NEXT:    beq a5, a6, .LBB51_15
 ; RV32-NEXT:  # %bb.12: # %entry
-; RV32-NEXT:    mv a0, a2
-; RV32-NEXT:    bne a4, a3, .LBB51_20
+; RV32-NEXT:    slti a0, a4, 0
+; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    and a0, a0, a2
+; RV32-NEXT:    mv a1, a3
+; RV32-NEXT:    j .LBB51_16
 ; RV32-NEXT:  .LBB51_13: # %entry
-; RV32-NEXT:    beq a6, a7, .LBB51_15
+; RV32-NEXT:    mv a7, t0
+; RV32-NEXT:    bltu a0, t0, .LBB51_5
 ; RV32-NEXT:  .LBB51_14: # %entry
-; RV32-NEXT:    slti a0, a5, 0
-; RV32-NEXT:    addi a0, a0, -1
+; RV32-NEXT:    mv a0, t0
+; RV32-NEXT:    bnez a6, .LBB51_6
+; RV32-NEXT:    j .LBB51_7
+; RV32-NEXT:  .LBB51_15:
+; RV32-NEXT:    srai a0, a0, 31
 ; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:  .LBB51_15: # %entry
+; RV32-NEXT:  .LBB51_16: # %entry
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
-; RV32-NEXT:  .LBB51_16: # %entry
-; RV32-NEXT:    addi a2, a5, -1
-; RV32-NEXT:    or a2, a2, t0
-; RV32-NEXT:    mv t0, a4
-; RV32-NEXT:    bltz a0, .LBB51_4
-; RV32-NEXT:  .LBB51_17: # %entry
-; RV32-NEXT:    mv t0, a6
-; RV32-NEXT:    bltu a4, a6, .LBB51_5
-; RV32-NEXT:  .LBB51_18: # %entry
-; RV32-NEXT:    mv a4, a6
-; RV32-NEXT:    bnez a7, .LBB51_6
-; RV32-NEXT:    j .LBB51_7
-; RV32-NEXT:  .LBB51_19: # %entry
-; RV32-NEXT:    mv a1, a0
-; RV32-NEXT:    mv a0, a2
-; RV32-NEXT:    beq a4, a3, .LBB51_13
-; RV32-NEXT:  .LBB51_20: # %entry
-; RV32-NEXT:    sltu a0, a3, a4
-; RV32-NEXT:    neg a0, a0
-; RV32-NEXT:    and a0, a0, a2
-; RV32-NEXT:    bne a6, a7, .LBB51_14
-; RV32-NEXT:    j .LBB51_15
 ;
 ; RV64-LABEL: stest_f16i64_mm:
 ; RV64:       # %bb.0: # %entry
@@ -3918,63 +3815,56 @@
 ; RV32-NEXT:    call __extendhfsf2@plt
 ; RV32-NEXT:    addi a0, sp, 8
 ; RV32-NEXT:    call __fixsfti@plt
-; RV32-NEXT:    lw a1, 16(sp)
-; RV32-NEXT:    lw a0, 20(sp)
-; RV32-NEXT:    li a3, 1
-; RV32-NEXT:    mv a6, a1
-; RV32-NEXT:    bltz a0, .LBB53_2
+; RV32-NEXT:    lw a1, 20(sp)
+; RV32-NEXT:    lw a0, 16(sp)
+; RV32-NEXT:    slti a2, a1, 0
+; RV32-NEXT:    beqz a1, .LBB53_2
 ; RV32-NEXT:  # %bb.1: # %entry
+; RV32-NEXT:    mv a4, a2
+; RV32-NEXT:    j .LBB53_3
+; RV32-NEXT:  .LBB53_2:
+; RV32-NEXT:    seqz a4, a0
+; RV32-NEXT:  .LBB53_3: # %entry
+; RV32-NEXT:    xori a3, a0, 1
+; RV32-NEXT:    or a7, a3, a1
 ; RV32-NEXT:    li a6, 1
-; RV32-NEXT:  .LBB53_2: # %entry
-; RV32-NEXT:    mv a2, a1
-; RV32-NEXT:    bltu a1, a3, .LBB53_4
-; RV32-NEXT:  # %bb.3: # %entry
-; RV32-NEXT:    li a2, 1
-; RV32-NEXT:  .LBB53_4: # %entry
-; RV32-NEXT:    lw a4, 12(sp)
-; RV32-NEXT:    lw a3, 8(sp)
-; RV32-NEXT:    slti a5, a0, 0
-; RV32-NEXT:    beqz a0, .LBB53_6
-; RV32-NEXT:  # %bb.5: # %entry
-; RV32-NEXT:    mv a2, a6
-; RV32-NEXT:    mv a6, a5
-; RV32-NEXT:    j .LBB53_7
-; RV32-NEXT:  .LBB53_6:
-; RV32-NEXT:    seqz a6, a1
+; RV32-NEXT:    mv a3, a0
+; RV32-NEXT:    bltz a1, .LBB53_5
+; RV32-NEXT:  # %bb.4: # %entry
+; RV32-NEXT:    li a3, 1
+; RV32-NEXT:  .LBB53_5: # %entry
+; RV32-NEXT:    lw a5, 8(sp)
+; RV32-NEXT:    lw t1, 12(sp)
+; RV32-NEXT:    neg t0, a4
+; RV32-NEXT:    seqz a4, a7
+; RV32-NEXT:    bltu a0, a6, .LBB53_7
+; RV32-NEXT:  # %bb.6: # %entry
+; RV32-NEXT:    li a0, 1
 ; RV32-NEXT:  .LBB53_7: # %entry
-; RV32-NEXT:    neg a6, a6
-; RV32-NEXT:    and a3, a6, a3
-; RV32-NEXT:    xori a1, a1, 1
-; RV32-NEXT:    or a1, a1, a0
-; RV32-NEXT:    seqz a1, a1
-; RV32-NEXT:    addi a1, a1, -1
-; RV32-NEXT:    and a3, a1, a3
-; RV32-NEXT:    and a4, a6, a4
-; RV32-NEXT:    and a1, a1, a4
-; RV32-NEXT:    neg a4, a5
-; RV32-NEXT:    and a4, a4, a0
-; RV32-NEXT:    mv a0, a3
+; RV32-NEXT:    and a6, t0, t1
+; RV32-NEXT:    addi a4, a4, -1
+; RV32-NEXT:    and a5, t0, a5
 ; RV32-NEXT:    beqz a1, .LBB53_9
 ; RV32-NEXT:  # %bb.8: # %entry
-; RV32-NEXT:    seqz a0, a1
-; RV32-NEXT:    addi a0, a0, -1
-; RV32-NEXT:    and a0, a0, a3
+; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:  .LBB53_9: # %entry
-; RV32-NEXT:    beqz a4, .LBB53_11
+; RV32-NEXT:    and a3, a4, a6
+; RV32-NEXT:    neg a2, a2
+; RV32-NEXT:    and a2, a2, a1
+; RV32-NEXT:    and a1, a4, a5
+; RV32-NEXT:    beqz a2, .LBB53_11
 ; RV32-NEXT:  # %bb.10: # %entry
-; RV32-NEXT:    sgtz a5, a4
-; RV32-NEXT:    or a2, a2, a4
-; RV32-NEXT:    bnez a2, .LBB53_12
-; RV32-NEXT:    j .LBB53_13
+; RV32-NEXT:    sgtz a4, a2
+; RV32-NEXT:    j .LBB53_12
 ; RV32-NEXT:  .LBB53_11:
-; RV32-NEXT:    snez a5, a2
-; RV32-NEXT:    or a2, a2, a4
-; RV32-NEXT:    beqz a2, .LBB53_13
+; RV32-NEXT:    snez a4, a0
 ; RV32-NEXT:  .LBB53_12: # %entry
-; RV32-NEXT:    neg a2, a5
-; RV32-NEXT:    and a0, a2, a3
-; RV32-NEXT:    and a1, a2, a1
-; RV32-NEXT:  .LBB53_13: # %entry
+; RV32-NEXT:    or a0, a0, a2
+; RV32-NEXT:    seqz a0, a0
+; RV32-NEXT:    or a0, a0, a4
+; RV32-NEXT:    neg a2, a0
+; RV32-NEXT:    and a0, a2, a1
+; RV32-NEXT:    and a1, a2, a3
 ; RV32-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
 ; RV32-NEXT:    addi sp, sp, 32
 ; RV32-NEXT:    ret
@@ -4000,12 +3890,9 @@
 ; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:    beqz a2, .LBB53_4
-; RV64-NEXT:  # %bb.3: # %entry
-; RV64-NEXT:    sgtz a1, a2
-; RV64-NEXT:    neg a1, a1
+; RV64-NEXT:    slti a1, a2, 0
+; RV64-NEXT:    addi a1, a1, -1
 ; RV64-NEXT:    and a0, a1, a0
-; RV64-NEXT:  .LBB53_4: # %entry
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 16
 ; RV64-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/min-max.ll b/llvm/test/CodeGen/RISCV/min-max.ll
--- a/llvm/test/CodeGen/RISCV/min-max.ll
+++ b/llvm/test/CodeGen/RISCV/min-max.ll
@@ -682,13 +682,11 @@
 define i64 @smin_i64_negone(i64 %a) {
 ; RV32I-LABEL: smin_i64_negone:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    slti a2, a1, -1
-; RV32I-NEXT:    li a3, -1
+; RV32I-NEXT:    slti a2, a1, 0
 ; RV32I-NEXT:    addi a2, a2, -1
-; RV32I-NEXT:    beq a1, a3, .LBB27_2
-; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    or a0, a2, a0
-; RV32I-NEXT:  .LBB27_2:
+; RV32I-NEXT:    slti a2, a1, -1
+; RV32I-NEXT:    addi a2, a2, -1
 ; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
@@ -702,13 +700,11 @@
 ; RV32ZBB-LABEL: smin_i64_negone:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    li a2, -1
-; RV32ZBB-NEXT:    beq a1, a2, .LBB27_2
-; RV32ZBB-NEXT:  # %bb.1:
-; RV32ZBB-NEXT:    slti a3, a1, -1
-; RV32ZBB-NEXT:    addi a3, a3, -1
-; RV32ZBB-NEXT:    or a0, a3, a0
-; RV32ZBB-NEXT:  .LBB27_2:
-; RV32ZBB-NEXT:    min a1, a1, a2
+; RV32ZBB-NEXT:    min a2, a1, a2
+; RV32ZBB-NEXT:    slti a1, a1, 0
+; RV32ZBB-NEXT:    addi a1, a1, -1
+; RV32ZBB-NEXT:    or a0, a1, a0
+; RV32ZBB-NEXT:    mv a1, a2
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: smin_i64_negone:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
@@ -5755,37 +5755,31 @@
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB47_2: # %entry
-; CHECK-NOV-NEXT:    mv a4, s1
+; CHECK-NOV-NEXT:    mv a3, s1
 ; CHECK-NOV-NEXT:    blez s1, .LBB47_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    li a4, 1
+; CHECK-NOV-NEXT:    li a3, 1
 ; CHECK-NOV-NEXT:  .LBB47_4: # %entry
-; CHECK-NOV-NEXT:    slti a3, a1, 1
-; CHECK-NOV-NEXT:    neg a3, a3
-; CHECK-NOV-NEXT:    and a3, a3, a0
+; CHECK-NOV-NEXT:    slti a4, a1, 1
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    and a0, a4, a0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    seqz a1, a1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
+; CHECK-NOV-NEXT:    and a1, a1, a0
 ; CHECK-NOV-NEXT:    slti a0, s1, 1
 ; CHECK-NOV-NEXT:    neg a0, a0
 ; CHECK-NOV-NEXT:    and a0, a0, s0
 ; CHECK-NOV-NEXT:    addi s1, s1, -1
-; CHECK-NOV-NEXT:    seqz a5, s1
-; CHECK-NOV-NEXT:    addi a5, a5, -1
-; CHECK-NOV-NEXT:    and a0, a5, a0
-; CHECK-NOV-NEXT:    beqz a4, .LBB47_6
-; CHECK-NOV-NEXT:  # %bb.5: # %entry
-; CHECK-NOV-NEXT:    sgtz a4, a4
-; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    seqz a4, s1
+; CHECK-NOV-NEXT:    addi a4, a4, -1
 ; CHECK-NOV-NEXT:    and a0, a4, a0
-; CHECK-NOV-NEXT:  .LBB47_6: # %entry
-; CHECK-NOV-NEXT:    and a1, a1, a3
-; CHECK-NOV-NEXT:    beqz a2, .LBB47_8
-; CHECK-NOV-NEXT:  # %bb.7: # %entry
-; CHECK-NOV-NEXT:    sgtz a2, a2
-; CHECK-NOV-NEXT:    neg a2, a2
+; CHECK-NOV-NEXT:    slti a3, a3, 0
+; CHECK-NOV-NEXT:    addi a3, a3, -1
+; CHECK-NOV-NEXT:    and a0, a3, a0
+; CHECK-NOV-NEXT:    slti a2, a2, 0
+; CHECK-NOV-NEXT:    addi a2, a2, -1
 ; CHECK-NOV-NEXT:    and a1, a2, a1
-; CHECK-NOV-NEXT:  .LBB47_8: # %entry
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
@@ -5831,33 +5825,27 @@
 ; CHECK-V-NEXT:    addi a4, s0, -1
 ; CHECK-V-NEXT:    seqz a4, a4
 ; CHECK-V-NEXT:    addi a4, a4, -1
-; CHECK-V-NEXT:    slti a5, a1, 1
-; CHECK-V-NEXT:    neg a5, a5
+; CHECK-V-NEXT:    and a3, a4, a3
+; CHECK-V-NEXT:    slti a4, a1, 1
+; CHECK-V-NEXT:    neg a4, a4
+; CHECK-V-NEXT:    and a0, a4, a0
 ; CHECK-V-NEXT:    addi a1, a1, -1
-; CHECK-V-NEXT:    seqz a6, a1
+; CHECK-V-NEXT:    seqz a1, a1
+; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    blez s0, .LBB47_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li s0, 1
 ; CHECK-V-NEXT:  .LBB47_4: # %entry
-; CHECK-V-NEXT:    and a1, a5, a0
-; CHECK-V-NEXT:    addi a5, a6, -1
-; CHECK-V-NEXT:    and a0, a4, a3
-; CHECK-V-NEXT:    beqz s0, .LBB47_6
-; CHECK-V-NEXT:  # %bb.5: # %entry
-; CHECK-V-NEXT:    sgtz a3, s0
-; CHECK-V-NEXT:    neg a3, a3
-; CHECK-V-NEXT:    and a0, a3, a0
-; CHECK-V-NEXT:  .LBB47_6: # %entry
-; CHECK-V-NEXT:    and a1, a5, a1
-; CHECK-V-NEXT:    beqz a2, .LBB47_8
-; CHECK-V-NEXT:  # %bb.7: # %entry
-; CHECK-V-NEXT:    sgtz a2, a2
-; CHECK-V-NEXT:    neg a2, a2
-; CHECK-V-NEXT:    and a1, a2, a1
-; CHECK-V-NEXT:  .LBB47_8: # %entry
+; CHECK-V-NEXT:    slti a1, s0, 0
+; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    and a1, a1, a3
+; CHECK-V-NEXT:    slti a2, a2, 0
+; CHECK-V-NEXT:    addi a2, a2, -1
+; CHECK-V-NEXT:    and a0, a2, a0
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-V-NEXT:    vmv.s.x v8, a1
-; CHECK-V-NEXT:    vmv.s.x v9, a0
+; CHECK-V-NEXT:    vmv.s.x v8, a0
+; CHECK-V-NEXT:    vmv.s.x v9, a1
 ; CHECK-V-NEXT:    vslideup.vi v8, v9, 1
 ; CHECK-V-NEXT:    csrr a0, vlenb
 ; CHECK-V-NEXT:    slli a0, a0, 1
@@ -6226,37 +6214,31 @@
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB50_2: # %entry
-; CHECK-NOV-NEXT:    mv a4, s1
+; CHECK-NOV-NEXT:    mv a3, s1
 ; CHECK-NOV-NEXT:    blez s1, .LBB50_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    li a4, 1
+; CHECK-NOV-NEXT:    li a3, 1
 ; CHECK-NOV-NEXT:  .LBB50_4: # %entry
-; CHECK-NOV-NEXT:    slti a3, a1, 1
-; CHECK-NOV-NEXT:    neg a3, a3
-; CHECK-NOV-NEXT:    and a3, a3, a0
+; CHECK-NOV-NEXT:    slti a4, a1, 1
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    and a0, a4, a0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    seqz a1, a1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
+; CHECK-NOV-NEXT:    and a1, a1, a0
 ; CHECK-NOV-NEXT:    slti a0, s1, 1
 ; CHECK-NOV-NEXT:    neg a0, a0
 ; CHECK-NOV-NEXT:    and a0, a0, s0
 ; CHECK-NOV-NEXT:    addi s1, s1, -1
-; CHECK-NOV-NEXT:    seqz a5, s1
-; CHECK-NOV-NEXT:    addi a5, a5, -1
-; CHECK-NOV-NEXT:    and a0, a5, a0
-; CHECK-NOV-NEXT:    beqz a4, .LBB50_6
-; CHECK-NOV-NEXT:  # %bb.5: # %entry
-; CHECK-NOV-NEXT:    sgtz a4, a4
-; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    seqz a4, s1
+; CHECK-NOV-NEXT:    addi a4, a4, -1
 ; CHECK-NOV-NEXT:    and a0, a4, a0
-; CHECK-NOV-NEXT:  .LBB50_6: # %entry
-; CHECK-NOV-NEXT:    and a1, a1, a3
-; CHECK-NOV-NEXT:    beqz a2, .LBB50_8
-; CHECK-NOV-NEXT:  # %bb.7: # %entry
-; CHECK-NOV-NEXT:    sgtz a2, a2
-; CHECK-NOV-NEXT:    neg a2, a2
+; CHECK-NOV-NEXT:    slti a3, a3, 0
+; CHECK-NOV-NEXT:    addi a3, a3, -1
+; CHECK-NOV-NEXT:    and a0, a3, a0
+; CHECK-NOV-NEXT:    slti a2, a2, 0
+; CHECK-NOV-NEXT:    addi a2, a2, -1
 ; CHECK-NOV-NEXT:    and a1, a2, a1
-; CHECK-NOV-NEXT:  .LBB50_8: # %entry
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
@@ -6302,33 +6284,27 @@
 ; CHECK-V-NEXT:    addi a4, s0, -1
 ; CHECK-V-NEXT:    seqz a4, a4
 ; CHECK-V-NEXT:    addi a4, a4, -1
-; CHECK-V-NEXT:    slti a5, a1, 1
-; CHECK-V-NEXT:    neg a5, a5
+; CHECK-V-NEXT:    and a3, a4, a3
+; CHECK-V-NEXT:    slti a4, a1, 1
+; CHECK-V-NEXT:    neg a4, a4
+; CHECK-V-NEXT:    and a0, a4, a0
+; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    seqz a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
-; CHECK-V-NEXT:    seqz a6, a1
+; CHECK-V-NEXT:    and a0, a1, a0
 ; CHECK-V-NEXT:    blez s0, .LBB50_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
 ; CHECK-V-NEXT:    li s0, 1
 ; CHECK-V-NEXT:  .LBB50_4: # %entry
-; CHECK-V-NEXT:    and a1, a5, a0
-; CHECK-V-NEXT:    addi a5, a6, -1
-; CHECK-V-NEXT:    and a0, a4, a3
-; CHECK-V-NEXT:    beqz s0, .LBB50_6
-; CHECK-V-NEXT:  # %bb.5: # %entry
-; CHECK-V-NEXT:    sgtz a3, s0
-; CHECK-V-NEXT:    neg a3, a3
-; CHECK-V-NEXT:    and a0, a3, a0
-; CHECK-V-NEXT:  .LBB50_6: # %entry
-; CHECK-V-NEXT:    and a1, a5, a1
-; CHECK-V-NEXT:    beqz a2, .LBB50_8
-; CHECK-V-NEXT:  # %bb.7: # %entry
-; CHECK-V-NEXT:    sgtz a2, a2
-; CHECK-V-NEXT:    neg a2, a2
-; CHECK-V-NEXT:    and a1, a2, a1
-; CHECK-V-NEXT:  .LBB50_8: # %entry
+; CHECK-V-NEXT:    slti a1, s0, 0
+; CHECK-V-NEXT:    addi a1, a1, -1
+; CHECK-V-NEXT:    and a1, a1, a3
+; CHECK-V-NEXT:    slti a2, a2, 0
+; CHECK-V-NEXT:    addi a2, a2, -1
+; CHECK-V-NEXT:    and a0, a2, a0
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-V-NEXT:    vmv.s.x v8, a1
-; CHECK-V-NEXT:    vmv.s.x v9, a0
+; CHECK-V-NEXT:    vmv.s.x v8, a0
+; CHECK-V-NEXT:    vmv.s.x v9, a1
 ; CHECK-V-NEXT:    vslideup.vi v8, v9, 1
 ; CHECK-V-NEXT:    csrr a0, vlenb
 ; CHECK-V-NEXT:    slli a0, a0, 1
@@ -6686,37 +6662,31 @@
 ; CHECK-NOV-NEXT:  # %bb.1: # %entry
 ; CHECK-NOV-NEXT:    li a2, 1
 ; CHECK-NOV-NEXT:  .LBB53_2: # %entry
-; CHECK-NOV-NEXT:    mv a4, s1
+; CHECK-NOV-NEXT:    mv a3, s1
 ; CHECK-NOV-NEXT:    blez s1, .LBB53_4
 ; CHECK-NOV-NEXT:  # %bb.3: # %entry
-; CHECK-NOV-NEXT:    li a4, 1
+; CHECK-NOV-NEXT:    li a3, 1
 ; CHECK-NOV-NEXT:  .LBB53_4: # %entry
-; CHECK-NOV-NEXT:    slti a3, a1, 1
-; CHECK-NOV-NEXT:    neg a3, a3
-; CHECK-NOV-NEXT:    and a3, a3, a0
+; CHECK-NOV-NEXT:    slti a4, a1, 1
+; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    and a0, a4, a0
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
 ; CHECK-NOV-NEXT:    seqz a1, a1
 ; CHECK-NOV-NEXT:    addi a1, a1, -1
+; CHECK-NOV-NEXT:    and a1, a1, a0
 ; CHECK-NOV-NEXT:    slti a0, s1, 1
 ; CHECK-NOV-NEXT:    neg a0, a0
 ; CHECK-NOV-NEXT:    and a0, a0, s0
 ; CHECK-NOV-NEXT:    addi s1, s1, -1
-; CHECK-NOV-NEXT:    seqz a5, s1
-; CHECK-NOV-NEXT:    addi a5, a5, -1
-; CHECK-NOV-NEXT:    and a0, a5, a0
-; CHECK-NOV-NEXT:    beqz a4, .LBB53_6
-; CHECK-NOV-NEXT:  # %bb.5: # %entry
-; CHECK-NOV-NEXT:    sgtz a4, a4
-; CHECK-NOV-NEXT:    neg a4, a4
+; CHECK-NOV-NEXT:    seqz a4, s1
+; CHECK-NOV-NEXT:    addi a4, a4, -1
 ; CHECK-NOV-NEXT:    and a0, a4, a0
-; CHECK-NOV-NEXT:  .LBB53_6: # %entry
-; CHECK-NOV-NEXT:    and a1, a1, a3
-; CHECK-NOV-NEXT:    beqz a2, .LBB53_8
-; CHECK-NOV-NEXT:  # %bb.7: # %entry
-; CHECK-NOV-NEXT:    sgtz a2, a2
-; CHECK-NOV-NEXT:    neg a2, a2
+; CHECK-NOV-NEXT:    slti a3, a3, 0
+; CHECK-NOV-NEXT:    addi a3, a3, -1
+; CHECK-NOV-NEXT:    and a0, a3, a0
+; CHECK-NOV-NEXT:    slti a2, a2, 0
+; CHECK-NOV-NEXT:    addi a2, a2, -1
 ; CHECK-NOV-NEXT:    and a1, a2, a1
-; CHECK-NOV-NEXT:  .LBB53_8: # %entry
 ; CHECK-NOV-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; CHECK-NOV-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
@@ -6749,40 +6719,34 @@
 ; CHECK-V-NEXT:  # %bb.1: # %entry
 ; CHECK-V-NEXT:    li a2, 1
 ; CHECK-V-NEXT:  .LBB53_2: # %entry
-; CHECK-V-NEXT:    mv a4, s1
+; CHECK-V-NEXT:    mv a3, s1
 ; CHECK-V-NEXT:    blez s1, .LBB53_4
 ; CHECK-V-NEXT:  # %bb.3: # %entry
-; CHECK-V-NEXT:    li a4, 1
+; CHECK-V-NEXT:    li a3, 1
 ; CHECK-V-NEXT:  .LBB53_4: # %entry
-; CHECK-V-NEXT:    slti a3, a1, 1
-; CHECK-V-NEXT:    neg a3, a3
-; CHECK-V-NEXT:    and a3, a3, a0
+; CHECK-V-NEXT:    slti a4, a1, 1
+; CHECK-V-NEXT:    neg a4, a4
+; CHECK-V-NEXT:    and a0, a4, a0
 ; CHECK-V-NEXT:    addi a1, a1, -1
 ; CHECK-V-NEXT:    seqz a1, a1
 ; CHECK-V-NEXT:    addi a1, a1, -1
-; CHECK-V-NEXT:    slti a0, s1, 1
-; CHECK-V-NEXT:    neg a0, a0
-; CHECK-V-NEXT:    and a0, a0, s0
+; CHECK-V-NEXT:    and a0, a1, a0
+; CHECK-V-NEXT:    slti a1, s1, 1
+; CHECK-V-NEXT:    neg a1, a1
+; CHECK-V-NEXT:    and a1, a1, s0
 ; CHECK-V-NEXT:    addi s1, s1, -1
-; CHECK-V-NEXT:    seqz a5, s1
-; CHECK-V-NEXT:    addi a5, a5, -1
-; CHECK-V-NEXT:    and a0, a5, a0
-; CHECK-V-NEXT:    beqz a4, .LBB53_6
-; CHECK-V-NEXT:  # %bb.5: # %entry
-; CHECK-V-NEXT:    sgtz a4, a4
-; CHECK-V-NEXT:    neg a4, a4
-; CHECK-V-NEXT:    and a0, a4, a0
-; CHECK-V-NEXT:  .LBB53_6: # %entry
-; CHECK-V-NEXT:    and a1, a1, a3
-; CHECK-V-NEXT:    beqz a2, .LBB53_8
-; CHECK-V-NEXT:  # %bb.7: # %entry
-; CHECK-V-NEXT:    sgtz a2, a2
-; CHECK-V-NEXT:    neg a2, a2
-; CHECK-V-NEXT:    and a1, a2, a1
-; CHECK-V-NEXT:  .LBB53_8: # %entry
+; CHECK-V-NEXT:    seqz a4, s1
+; CHECK-V-NEXT:    addi a4, a4, -1
+; CHECK-V-NEXT:    and a1, a4, a1
+; CHECK-V-NEXT:    slti a3, a3, 0
+; CHECK-V-NEXT:    addi a3, a3, -1
+; CHECK-V-NEXT:    and a1, a3, a1
+; CHECK-V-NEXT:    slti a2, a2, 0
+; CHECK-V-NEXT:    addi a2, a2, -1
+; CHECK-V-NEXT:    and a0, a2, a0
 ; CHECK-V-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-V-NEXT:    vmv.s.x v9, a1
-; CHECK-V-NEXT:    vmv.s.x v8, a0
+; CHECK-V-NEXT:    vmv.s.x v9, a0
+; CHECK-V-NEXT:    vmv.s.x v8, a1
 ; CHECK-V-NEXT:    vslideup.vi v8, v9, 1
 ; CHECK-V-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-V-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload