Index: llvm/lib/Target/AArch64/SVEInstrFormats.td =================================================================== --- llvm/lib/Target/AArch64/SVEInstrFormats.td +++ llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -623,7 +623,9 @@ : PatFrags<(ops node:$Pg, node:$Op1, node:$Op2), [ (intrinsic node:$Pg, node:$Op1, node:$Op2), (vselect node:$Pg, (sdnode (SVEAllActive), node:$Op1, node:$Op2), node:$Op1), - ]>; + ], [{ + return N->getOpcode() != ISD::VSELECT || N->getOperand(1).hasOneUse(); + }]>; // // Pseudo -> Instruction mappings Index: llvm/test/CodeGen/AArch64/sve-min-max-pred.ll =================================================================== --- llvm/test/CodeGen/AArch64/sve-min-max-pred.ll +++ llvm/test/CodeGen/AArch64/sve-min-max-pred.ll @@ -177,10 +177,9 @@ ; CHECK-LABEL: umin_select_i64_multiuse: ; CHECK: // %bb.0: ; CHECK-NEXT: ptrue p1.d -; CHECK-NEXT: movprfx z2, z0 -; CHECK-NEXT: umin z2.d, p1/m, z2.d, z1.d -; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d -; CHECK-NEXT: st1d { z2.d }, p1, [x0] +; CHECK-NEXT: umin z1.d, p1/m, z1.d, z0.d +; CHECK-NEXT: mov z0.d, p0/m, z1.d +; CHECK-NEXT: st1d { z1.d }, p1, [x0] ; CHECK-NEXT: ret %sel = call @llvm.umin.nxv2i64( %a, %b) store %sel, ptr %p