diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1421,6 +1421,7 @@
                                  SelectionDAG &DAG) const;
     SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
                                  DAGCombinerInfo &DCI) const;
+    SDValue combineABDS(SDNode *N, DAGCombinerInfo &DCI) const;
 
     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
     /// SETCC with integer subtraction when (1) there is a legal way of doing it
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1397,6 +1397,9 @@
     setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC});
   }
 
+  if (Subtarget.hasP9Altivec())
+    setTargetDAGCombine({ISD::ABDS});
+
   setLibcallName(RTLIB::LOG_F128, "logf128");
   setLibcallName(RTLIB::LOG2_F128, "log2f128");
   setLibcallName(RTLIB::LOG10_F128, "log10f128");
@@ -16231,6 +16234,8 @@
   }
   case ISD::BUILD_VECTOR:
     return DAGCombineBuildVector(N, DCI);
+  case ISD::ABDS:
+    return combineABDS(N, DCI);
   }
 
   return SDValue();
@@ -18524,3 +18529,20 @@
   return Builder.CreateOr(
       Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
 }
+
+SDValue PPCTargetLowering::combineABDS(SDNode *N, DAGCombinerInfo &DCI) const {
+  assert((N->getOpcode() == ISD::ABDS) && "Need ABDS node here");
+  assert(Subtarget.hasP9Altivec() &&
+         "Only combine this when P9 altivec supported!");
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)
+    return SDValue();
+  // If we know sign bits of elements to be zeros, we can convert ABDS to
+  // ABDU.
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  if (!DCI.DAG.SignBitIsZero(Op0) || !DCI.DAG.SignBitIsZero(Op1))
+    return SDValue();
+  SDLoc DL(N);
+  return DCI.DAG.getNode(ISD::ABDU, DL, VT, Op0, Op1);
+}
diff --git a/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll b/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
--- a/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
+++ b/llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll
@@ -20,17 +20,11 @@
 ; CHECK-NEXT:    vperm 1, 4, 3, 1
 ; CHECK-NEXT:    vperm 2, 4, 2, 7
 ; CHECK-NEXT:    vperm 3, 4, 3, 7
-; CHECK-NEXT:    xvnegsp 36, 38
-; CHECK-NEXT:    xvnegsp 35, 35
-; CHECK-NEXT:    xvnegsp 34, 34
+; CHECK-NEXT:    vabsduw 4, 0, 5
 ; CHECK-NEXT:    vabsduw 2, 2, 3
-; CHECK-NEXT:    xvnegsp 35, 33
-; CHECK-NEXT:    vabsduw 3, 4, 3
-; CHECK-NEXT:    xvnegsp 36, 37
-; CHECK-NEXT:    xvnegsp 37, 32
-; CHECK-NEXT:    vpkuwum 2, 2, 2
-; CHECK-NEXT:    vabsduw 4, 5, 4
+; CHECK-NEXT:    vabsduw 3, 6, 1
 ; CHECK-NEXT:    vpkuwum 3, 4, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
 ; CHECK-NEXT:    vpkuhum 2, 2, 3
 ; CHECK-NEXT:    blr
 entry: