diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -278,21 +278,17 @@ continue; if (!MO.isDef()) continue; - // Get the first instruction that uses MO - MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg()); - RI++; - if (RI == MRI->reg_end()) - continue; - MachineInstr *UseMO = RI->getParent(); - unsigned LatencyOp = 0; - if (UseMO && BlockTrace.isDepInTrace(*Root, *UseMO)) { - LatencyOp = TSchedModel.computeOperandLatency( - NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, - UseMO->findRegisterUseOperandIdx(MO.getReg())); - } else { - LatencyOp = TSchedModel.computeInstrLatency(NewRoot); + for (MachineInstr &UseInstr : MRI->use_nodbg_instructions(MO.getReg())) { + unsigned LatencyOp = 0; + if (BlockTrace.isDepInTrace(*Root, UseInstr)) { + LatencyOp = TSchedModel.computeOperandLatency( + NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), &UseInstr, + MO.getOperandNo()); + } else { + LatencyOp = TSchedModel.computeInstrLatency(NewRoot); + } + NewRootLatency = std::max(NewRootLatency, LatencyOp); } - NewRootLatency = std::max(NewRootLatency, LatencyOp); } return NewRootLatency; }