diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
     ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
     HasLegalHalfType = true;
 
   return true;
diff --git a/clang/test/CodeGen/RISCV/Float16-arith.c b/clang/test/CodeGen/RISCV/Float16-arith.c
--- a/clang/test/CodeGen/RISCV/Float16-arith.c
+++ b/clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:    [[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:    [[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:    [[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:    [[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:    [[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:    [[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:    store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:    [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:    store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:    ret void
 //
 void f16_add() {