Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -75,7 +75,7 @@ // If no explicit ABI is given, try to compute the default ABI. auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits); if (!ISAInfo) - report_fatal_error(ISAInfo.takeError()); + report_fatal_error(ISAInfo.takeError(), false); return getTargetABI((*ISAInfo)->computeDefaultABI()); } @@ -107,12 +107,12 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) { if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) - report_fatal_error("RV64 target requires an RV64 CPU"); + report_fatal_error("RV64 target requires an RV64 CPU", false); if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) - report_fatal_error("RV32 target requires an RV32 CPU"); + report_fatal_error("RV32 target requires an RV32 CPU", false); if (FeatureBits[RISCV::Feature32Bit] && FeatureBits[RISCV::Feature64Bit]) - report_fatal_error("RV32 and RV64 can't be combined"); + report_fatal_error("RV32 and RV64 can't be combined", false); } llvm::Expected> Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp =================================================================== --- llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -51,7 +51,7 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, bool EmitStackAlign) { if (STI.hasFeature(RISCV::FeatureRVE)) - report_fatal_error("Codegen not yet implemented for RVE"); + report_fatal_error("Codegen not yet implemented for RVE", false); if (EmitStackAlign) emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16); @@ -59,7 +59,7 @@ auto ParseResult = RISCVFeatures::parseFeatureBits( STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits()); if (!ParseResult) { - report_fatal_error(ParseResult.takeError()); + report_fatal_error(ParseResult.takeError(), false); } else { auto &ISAInfo = *ParseResult; emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -343,7 +343,8 @@ if (!Sym) { // FIXME: Make this work on non-ELF. if (!TM.getTargetTriple().isOSBinFormatELF()) - report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF"); + report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF", + false); std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" + utostr(AccessInfo) + "_short"; Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -436,7 +436,8 @@ unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { report_fatal_error("The V extension does not support EEW=64 for index " - "values when XLEN=32"); + "values when XLEN=32", + false); } const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo( NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast(LMUL), @@ -518,7 +519,8 @@ unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { report_fatal_error("The V extension does not support EEW=64 for index " - "values when XLEN=32"); + "values when XLEN=32", + false); } const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo( NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast(LMUL), @@ -1704,7 +1706,8 @@ unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { report_fatal_error("The V extension does not support EEW=64 for index " - "values when XLEN=32"); + "values when XLEN=32", + false); } const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo( IsMasked, IsOrdered, IndexLog2EEW, static_cast(LMUL), @@ -1902,7 +1905,8 @@ unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits()); if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) { report_fatal_error("The V extension does not support EEW=64 for index " - "values when XLEN=32"); + "values when XLEN=32", + false); } const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo( IsMasked, IsOrdered, IndexLog2EEW, Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -79,7 +79,7 @@ : TargetLowering(TM), Subtarget(STI) { if (Subtarget.isRVE()) - report_fatal_error("Codegen not yet implemented for RVE"); + report_fatal_error("Codegen not yet implemented for RVE", false); RISCVABI::ABI ABI = Subtarget.getTargetABI(); assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI"); @@ -5618,7 +5618,7 @@ // vscale as VLENB / 8. static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!"); if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock) - report_fatal_error("Support for VLEN==32 is incomplete."); + report_fatal_error("Support for VLEN==32 is incomplete.", false); // We assume VLENB is a multiple of 8. We manually choose the best shift // here because SimplifyDemandedBits isn't always able to simplify it. uint64_t Val = Op.getConstantOperandVal(0); @@ -6348,7 +6348,7 @@ switch (getTargetMachine().getCodeModel()) { default: - report_fatal_error("Unsupported code model for lowering"); + report_fatal_error("Unsupported code model for lowering", false); case CodeModel::Small: { // Generate a sequence for accessing addresses within the first 2 GiB of // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)). @@ -6504,7 +6504,7 @@ if (DAG.getMachineFunction().getFunction().getCallingConv() == CallingConv::GHC) - report_fatal_error("In GHC calling convention TLS is not supported"); + report_fatal_error("In GHC calling convention TLS is not supported", false); SDValue Addr; switch (Model) { @@ -16483,7 +16483,7 @@ ISD::ArgFlagsTy ArgFlags, CCState &State) { if (ArgFlags.isNest()) { report_fatal_error( - "Attribute 'nest' is not supported in GHC calling convention"); + "Attribute 'nest' is not supported in GHC calling convention", false); } static const MCPhysReg GPRList[] = { @@ -16535,7 +16535,7 @@ } } - report_fatal_error("No registers left in GHC calling convention"); + report_fatal_error("No registers left in GHC calling convention", false); return true; } @@ -16556,21 +16556,23 @@ case CallingConv::GHC: if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx()) report_fatal_error("GHC calling convention requires the (Zfinx/F) and " - "(Zdinx/D) instruction set extensions"); + "(Zdinx/D) instruction set extensions", + false); } const Function &Func = MF.getFunction(); if (Func.hasFnAttribute("interrupt")) { if (!Func.arg_empty()) report_fatal_error( - "Functions with the interrupt attribute cannot have arguments!"); + "Functions with the interrupt attribute cannot have arguments!", + false); StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine")) - report_fatal_error( - "Function interrupt attribute argument not supported!"); + report_fatal_error("Function interrupt attribute argument not supported!", + false); } EVT PtrVT = getPointerTy(DAG.getDataLayout()); @@ -16803,7 +16805,8 @@ ++NumTailCalls; else if (CLI.CB && CLI.CB->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " - "site marked musttail"); + "site marked musttail", + false); // Get a count of how many bytes are to be pushed on the stack. unsigned NumBytes = ArgCCInfo.getStackSize(); @@ -17115,7 +17118,7 @@ nullptr, RISCV::CC_RISCV); if (CallConv == CallingConv::GHC && !RVLocs.empty()) - report_fatal_error("GHC functions return void only"); + report_fatal_error("GHC functions return void only", false); SDValue Glue; SmallVector RetOps(1, Chain); @@ -17182,7 +17185,8 @@ if (Func.hasFnAttribute("interrupt")) { if (!Func.getReturnType()->isVoidTy()) report_fatal_error( - "Functions with the interrupt attribute must have void return type!"); + "Functions with the interrupt attribute must have void return type!", + false); MachineFunction &MF = DAG.getMachineFunction(); StringRef Kind = Index: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -419,7 +419,8 @@ if (!isInt<32>(Offset.getFixed())) { report_fatal_error( - "Frame offsets outside of the signed 32-bit range not supported"); + "Frame offsets outside of the signed 32-bit range not supported", + false); } if (!IsRVVSpill) { Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -129,7 +129,8 @@ // riscv-v-vector-bits-max should be no less than it. if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen) report_fatal_error("riscv-v-vector-bits-max specified is lower " - "than the Zvl*b limitation"); + "than the Zvl*b limitation", + false); return RVVVectorBitsMax; } @@ -145,7 +146,8 @@ // riscv-v-vector-bits-min should be no less than it. if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen) report_fatal_error("riscv-v-vector-bits-min specified is lower " - "than the Zvl*b limitation"); + "than the Zvl*b limitation", + false); return RVVVectorBitsMin; } Index: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -131,7 +131,7 @@ setSupportsDefaultOutlining(true); if (TT.isOSFuchsia() && !TT.isArch64Bit()) - report_fatal_error("Fuchsia is only supported for 64-bit"); + report_fatal_error("Fuchsia is only supported for 64-bit", false); } const RISCVSubtarget * @@ -206,7 +206,8 @@ auto TargetABI = RISCVABI::getTargetABI(ABIName); if (TargetABI != RISCVABI::ABI_Unknown && ModuleTargetABI->getString() != ABIName) { - report_fatal_error("-target-abi option != target-abi module flag"); + report_fatal_error("-target-abi option != target-abi module flag", + false); } ABIName = ModuleTargetABI->getString(); }