diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -160,6 +160,9 @@ ColWidth("misched-dump-schedule-trace-col-width", cl::Hidden, cl::desc("Set width of the columns showing resource booking."), cl::init(5)); +static cl::opt MISchedSortResourcesInTrace( + "misched-sort-resources-in-trace", cl::Hidden, cl::init(true), + cl::desc("Sort the resources printed in the dump trace")); #endif // DAG subtrees must have at least this many nodes. @@ -949,6 +952,10 @@ static const char *scheduleTableLegend = " i: issue\n x: resource booked"; LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceTopDown() const { + // Bail off when there is no schedule model to query. + if (!SchedModel.hasInstrSchedModel()) + return; + // Nothing to show if there is no or just one instruction. if (BB->size() < 2) return; @@ -993,17 +1000,28 @@ } dbgs() << "|\n"; const MCSchedClassDesc *SC = getSchedClass(SU); - for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), - PE = SchedModel.getWriteProcResEnd(SC); - PI != PE; ++PI) { + + SmallVector ResourcesIt( + make_range(SchedModel.getWriteProcResBegin(SC), + SchedModel.getWriteProcResEnd(SC))); + + if (MISchedSortResourcesInTrace) + llvm::sort(ResourcesIt.begin(), ResourcesIt.end(), + [](const MCWriteProcResEntry &LHS, + const MCWriteProcResEntry &RHS) -> bool { + return LHS.StartAtCycle < RHS.StartAtCycle || + (LHS.StartAtCycle == RHS.StartAtCycle && + LHS.Cycles < RHS.Cycles); + }); + for (const MCWriteProcResEntry &PI : ResourcesIt) { C = FirstCycle; const std::string ResName = - SchedModel.getResourceName(PI->ProcResourceIdx); - dbgs() << llvm::left_justify(ResName, HeaderColWidth); - for (; C < SU->TopReadyCycle; ++C) { + SchedModel.getResourceName(PI.ProcResourceIdx); + dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth); + for (; C < SU->TopReadyCycle + PI.StartAtCycle; ++C) { dbgs() << llvm::left_justify("|", ColWidth); } - for (unsigned i = 0; i < PI->Cycles; ++i, ++C) + for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, ++C) dbgs() << llvm::left_justify("| x", ColWidth); while (C++ <= LastCycle) dbgs() << llvm::left_justify("|", ColWidth); @@ -1014,6 +1032,10 @@ } LLVM_DUMP_METHOD void ScheduleDAGMI::dumpScheduleTraceBottomUp() const { + // Bail off when there is no schedule model to query. + if (!SchedModel.hasInstrSchedModel()) + return; + // Nothing to show if there is no or just one instruction. if (BB->size() < 2) return; @@ -1059,17 +1081,27 @@ } dbgs() << "|\n"; const MCSchedClassDesc *SC = getSchedClass(SU); - for (TargetSchedModel::ProcResIter PI = SchedModel.getWriteProcResBegin(SC), - PE = SchedModel.getWriteProcResEnd(SC); - PI != PE; ++PI) { + SmallVector ResourcesIt( + make_range(SchedModel.getWriteProcResBegin(SC), + SchedModel.getWriteProcResEnd(SC))); + + if (MISchedSortResourcesInTrace) + llvm::sort(ResourcesIt.begin(), ResourcesIt.end(), + [](const MCWriteProcResEntry &LHS, + const MCWriteProcResEntry &RHS) -> bool { + return LHS.StartAtCycle < RHS.StartAtCycle || + (LHS.StartAtCycle == RHS.StartAtCycle && + LHS.Cycles < RHS.Cycles); + }); + for (const MCWriteProcResEntry &PI : ResourcesIt) { C = FirstCycle; const std::string ResName = - SchedModel.getResourceName(PI->ProcResourceIdx); - dbgs() << llvm::left_justify(ResName, HeaderColWidth); - for (; C > (int)SU->BotReadyCycle; --C) { + SchedModel.getResourceName(PI.ProcResourceIdx); + dbgs() << llvm::right_justify(ResName + " ", HeaderColWidth); + for (; C > ((int)SU->BotReadyCycle - (int)PI.StartAtCycle); --C) { dbgs() << llvm::left_justify("|", ColWidth); } - for (unsigned i = 0; i < PI->Cycles; ++i, --C) + for (unsigned I = 0, E = PI.Cycles - PI.StartAtCycle; I != E; ++I, --C) dbgs() << llvm::left_justify("| x", ColWidth); while (C-- >= LastCycle) dbgs() << llvm::left_justify("|", ColWidth); diff --git a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir --- a/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir +++ b/llvm/test/CodeGen/AArch64/dump-schedule-trace.mir @@ -34,15 +34,15 @@ # TOP-NEXT: x: resource booked # TOP-NEXT: Cycle | 0 | 1 | 2 | # TOP-NEXT: SU(0) | i | | | -# TOP-NEXT: CortexA55UnitFPALU | x | x | | +# TOP-NEXT: CortexA55UnitFPALU | x | x | | # TOP-NEXT: SU(1) | i | | | -# TOP-NEXT: CortexA55UnitALU | x | | | +# TOP-NEXT: CortexA55UnitALU | x | | | # TOP-NEXT: SU(2) | | i | | -# TOP-NEXT: CortexA55UnitALU | | x | | +# TOP-NEXT: CortexA55UnitALU | | x | | # TOP-NEXT: SU(3) | | i | | -# TOP-NEXT: CortexA55UnitALU | | x | | +# TOP-NEXT: CortexA55UnitALU | | x | | # TOP-NEXT: SU(4) | | | i | -# TOP-NEXT: CortexA55UnitALU | | | x | +# TOP-NEXT: CortexA55UnitALU | | | x | # TOP-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 3]: dead %0:fpr128 = EXTv16i8 $q0, $q0, 8 # TOP-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 0]: $x3 = ADDXrr $x0, $x0 # TOP-NEXT: SU(2) [TopReadyCycle = 1, BottomReadyCycle = 0]: $x4 = ADDXrr $x1, $x1 @@ -57,13 +57,13 @@ # BOTTOM-NEXT: SU(0) | i | | | | # BOTTOM-NEXT: CortexA55UnitFPALU | x | x | | | # BOTTOM-NEXT: SU(1) | | | i | | -# BOTTOM-NEXT: CortexA55UnitALU | | | x | | +# BOTTOM-NEXT: CortexA55UnitALU | | | x | | # BOTTOM-NEXT: SU(2) | | | i | | -# BOTTOM-NEXT: CortexA55UnitALU | | | x | | +# BOTTOM-NEXT: CortexA55UnitALU | | | x | | # BOTTOM-NEXT: SU(3) | | | | i | -# BOTTOM-NEXT: CortexA55UnitALU | | | | x | +# BOTTOM-NEXT: CortexA55UnitALU | | | | x | # BOTTOM-NEXT: SU(4) | | | | i | -# BOTTOM-NEXT: CortexA55UnitALU | | | | x | +# BOTTOM-NEXT: CortexA55UnitALU | | | | x | # BOTTOM-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 3]: dead %0:fpr128 = EXTv16i8 $q0, $q0, 8 # BOTTOM-NEXT: SU(1) [TopReadyCycle = 0, BottomReadyCycle = 1]: $x3 = ADDXrr $x0, $x0 # BOTTOM-NEXT: SU(2) [TopReadyCycle = 0, BottomReadyCycle = 1]: $x4 = ADDXrr $x1, $x1 diff --git a/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/misched-sort-resource-in-trace.mir @@ -0,0 +1,52 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \ +# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-topdown=true -sched-print-cycles=true \ +# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=true 2>&1 | FileCheck --check-prefix=SORTED %s + +# RUN: llc -mtriple=aarch64-none-linux-gnu -mcpu=exynos-m3 -verify-machineinstrs \ +# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s \ +# RUN: -misched-topdown=true -sched-print-cycles=true \ +# RUN: -misched-dump-schedule-trace=true --misched-sort-resources-in-trace=false 2>&1 | FileCheck --check-prefix=UNSORTED %s + +--- +name: test +tracksRegLiveness: true +body: | + bb.0: + liveins: $x0, $x1, $x3, $x4, $q2 + $x0, $q2 = LD1i32_POST $q2, 0, $x0, $x0 :: ("aarch64-strided-access" load (s32)) + $x1, $q2 = LD1i32_POST $q2, 0, $x1, $x1 :: ("aarch64-strided-access" load (s32)) +... + + +# SORTED-LABEL: *** Final schedule for %bb.0 *** +# SORTED-NEXT: * Schedule table (TopDown): +# SORTED-NEXT: i: issue +# SORTED-NEXT: x: resource booked +# SORTED-NEXT: Cycle | 0 | 1 | 2 | +# SORTED-NEXT: SU(0) | i | | | +# SORTED-NEXT: M3UnitALU | x | | | +# SORTED-NEXT: M3UnitNALU | x | | | +# SORTED-NEXT: M3UnitL | x | x | | +# SORTED-NEXT: SU(1) | | i | | +# SORTED-NEXT: M3UnitALU | | x | | +# SORTED-NEXT: M3UnitNALU | | x | | +# SORTED-NEXT: M3UnitL | | x | x | +# SORTED-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 0]: $x0, $q2 = LD1i32_POST $q2(tied-def 1), 0, $x0(tied-def 0), $x0 :: ("aarch64-strided-access" load (s32)) +# SORTED-NEXT: SU(1) [TopReadyCycle = 1, BottomReadyCycle = 6]: $x1, $q2 = LD1i32_POST $q2(tied-def 1), 0, $x1(tied-def 0), $x1 :: ("aarch64-strided-access" load (s32)) + +# UNSORTED-LABEL: *** Final schedule for %bb.0 *** +# UNSORTED-NEXT: * Schedule table (TopDown): +# UNSORTED-NEXT: i: issue +# UNSORTED-NEXT: x: resource booked +# UNSORTED-NEXT: Cycle | 0 | 1 | 2 | +# UNSORTED-NEXT: SU(0) | i | | | +# UNSORTED-NEXT: M3UnitALU | x | | | +# UNSORTED-NEXT: M3UnitL | x | x | | +# UNSORTED-NEXT: M3UnitNALU | x | | | +# UNSORTED-NEXT: SU(1) | | i | | +# UNSORTED-NEXT: M3UnitALU | | x | | +# UNSORTED-NEXT: M3UnitL | | x | x | +# UNSORTED-NEXT: M3UnitNALU | | x | | +# UNSORTED-NEXT: SU(0) [TopReadyCycle = 0, BottomReadyCycle = 0]: $x0, $q2 = LD1i32_POST $q2(tied-def 1), 0, $x0(tied-def 0), $x0 :: ("aarch64-strided-access" load (s32)) +# UNSORTED-NEXT: SU(1) [TopReadyCycle = 1, BottomReadyCycle = 6]: $x1, $q2 = LD1i32_POST $q2(tied-def 1), 0, $x1(tied-def 0), $x1 :: ("aarch64-strided-access" load (s32))