Index: clang/lib/CodeGen/CGExpr.cpp =================================================================== --- clang/lib/CodeGen/CGExpr.cpp +++ clang/lib/CodeGen/CGExpr.cpp @@ -3799,6 +3799,17 @@ idx, DbgInfo); } + if (!CGF.getLangOpts().isSignedOverflowDefined() && ( + // ISO/IEC 9899:TC3, 6.5.6.8 + CGF.getLangOpts().C99 || + CGF.getLangOpts().CPlusPlus) && + addr.getElementType()->getTypeID() == llvm::Type::ArrayTyID) { + if (isa(eltPtr)) { + llvm::GetElementPtrInst *GEP = dyn_cast(eltPtr); + GEP->setInRangeIndex(1); + } + } + return Address(eltPtr, CGF.ConvertTypeForMem(eltType), eltAlign); } Index: clang/test/CodeGen/2005-01-02-ConstantInits.c =================================================================== --- clang/test/CodeGen/2005-01-02-ConstantInits.c +++ clang/test/CodeGen/2005-01-02-ConstantInits.c @@ -37,7 +37,7 @@ // CHECK-NEXT: [[CALL:%.*]] = call i32 (ptr, ...) @bar(ptr noundef getelementptr inbounds ([100 x i32], ptr @Arr, i64 0, i64 49)) // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[I_ADDR]], align 4 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP0]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @Arr, i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @Arr, inrange i64 0, i64 [[IDXPROM]] // CHECK-NEXT: [[CALL1:%.*]] = call i32 (ptr, ...) @bar(ptr noundef [[ARRAYIDX]]) // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] // CHECK-NEXT: ret i32 [[ADD]] Index: clang/test/CodeGen/2010-07-14-ref-off-end.c =================================================================== --- clang/test/CodeGen/2010-07-14-ref-off-end.c +++ clang/test/CodeGen/2010-07-14-ref-off-end.c @@ -14,7 +14,7 @@ } int main(void) { -// CHECK: getelementptr inbounds [1 x %struct.T], ptr %s, i32 0, i32 0 +// CHECK: getelementptr inbounds [1 x %struct.T], ptr %s, inrange i32 0, i32 0 // CHECK: getelementptr inbounds [1 x %struct.T], ptr %s, i32 0, i32 0 struct T t; t.i=0xff; Index: clang/test/CodeGen/X86/va-arg-sse.c =================================================================== --- clang/test/CodeGen/X86/va-arg-sse.c +++ clang/test/CodeGen/X86/va-arg-sse.c @@ -59,10 +59,10 @@ // CHECK: land.lhs.true: // CHECK-NEXT: [[TMP16:%.*]] = load ptr, ptr [[P]], align 8 // CHECK-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP16]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x float], ptr [[A]], i64 0, i64 2 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [3 x float], ptr [[A]], inrange i64 0, i64 2 // CHECK-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARG]], i32 0, i32 0 -// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [3 x float], ptr [[A5]], i64 0, i64 2 +// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [3 x float], ptr [[A5]], inrange i64 0, i64 2 // CHECK-NEXT: [[TMP18:%.*]] = load float, ptr [[ARRAYIDX6]], align 4 // CHECK-NEXT: [[CMP:%.*]] = fcmp une float [[TMP17]], [[TMP18]] // CHECK-NEXT: br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END]] Index: clang/test/CodeGen/builtin-align-array.c =================================================================== --- clang/test/CodeGen/builtin-align-array.c +++ clang/test/CodeGen/builtin-align-array.c @@ -7,14 +7,14 @@ // CHECK-LABEL: @test_array( // CHECK-NEXT: entry: // CHECK-NEXT: [[BUF:%.*]] = alloca [1024 x i8], align 16 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], i64 0, i64 44 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], inrange i64 0, i64 44 // CHECK-NEXT: [[INTPTR:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK-NEXT: [[ALIGNED_INTPTR:%.*]] = and i64 [[INTPTR]], -16 // CHECK-NEXT: [[DIFF:%.*]] = sub i64 [[ALIGNED_INTPTR]], [[INTPTR]] // CHECK-NEXT: [[ALIGNED_RESULT:%.*]] = getelementptr inbounds i8, ptr [[ARRAYIDX]], i64 [[DIFF]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ALIGNED_RESULT]], i64 16) ] // CHECK-NEXT: [[CALL:%.*]] = call i32 @func(ptr noundef [[ALIGNED_RESULT]]) -// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], i64 0, i64 22 +// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], inrange i64 0, i64 22 // CHECK-NEXT: [[INTPTR2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK-NEXT: [[OVER_BOUNDARY:%.*]] = add i64 [[INTPTR2]], 31 // CHECK-NEXT: [[ALIGNED_INTPTR4:%.*]] = and i64 [[OVER_BOUNDARY]], -32 @@ -22,7 +22,7 @@ // CHECK-NEXT: [[ALIGNED_RESULT6:%.*]] = getelementptr inbounds i8, ptr [[ARRAYIDX1]], i64 [[DIFF5]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ALIGNED_RESULT6]], i64 32) ] // CHECK-NEXT: [[CALL7:%.*]] = call i32 @func(ptr noundef [[ALIGNED_RESULT6]]) -// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], i64 0, i64 16 +// CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], inrange i64 0, i64 16 // CHECK-NEXT: [[SRC_ADDR:%.*]] = ptrtoint ptr [[ARRAYIDX8]] to i64 // CHECK-NEXT: [[SET_BITS:%.*]] = and i64 [[SRC_ADDR]], 63 // CHECK-NEXT: [[IS_ALIGNED:%.*]] = icmp eq i64 [[SET_BITS]], 0 @@ -39,14 +39,14 @@ // CHECK-LABEL: @test_array_should_not_mask( // CHECK-NEXT: entry: // CHECK-NEXT: [[BUF:%.*]] = alloca [1024 x i8], align 32 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], i64 0, i64 64 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], inrange i64 0, i64 64 // CHECK-NEXT: [[INTPTR:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK-NEXT: [[ALIGNED_INTPTR:%.*]] = and i64 [[INTPTR]], -16 // CHECK-NEXT: [[DIFF:%.*]] = sub i64 [[ALIGNED_INTPTR]], [[INTPTR]] // CHECK-NEXT: [[ALIGNED_RESULT:%.*]] = getelementptr inbounds i8, ptr [[ARRAYIDX]], i64 [[DIFF]] // CHECK-NEXT: call void @llvm.assume(i1 true) [ "align"(ptr [[ALIGNED_RESULT]], i64 16) ] // CHECK-NEXT: [[CALL:%.*]] = call i32 @func(ptr noundef [[ALIGNED_RESULT]]) -// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], i64 0, i64 32 +// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [1024 x i8], ptr [[BUF]], inrange i64 0, i64 32 // CHECK-NEXT: [[INTPTR2:%.*]] = ptrtoint ptr [[ARRAYIDX1]] to i64 // CHECK-NEXT: [[OVER_BOUNDARY:%.*]] = add i64 [[INTPTR2]], 31 // CHECK-NEXT: [[ALIGNED_INTPTR4:%.*]] = and i64 [[OVER_BOUNDARY]], -32 Index: clang/test/CodeGen/exprs.c =================================================================== --- clang/test/CodeGen/exprs.c +++ clang/test/CodeGen/exprs.c @@ -129,7 +129,7 @@ // CHECK: [[Xaddr:%[^ ]+]] = alloca i64, align 8 // CHECK: [[A:%.*]] = alloca [100 x i32], align // CHECK: [[X:%.*]] = load {{.*}}, ptr [[Xaddr]] -// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [100 x i32], ptr [[A]], i64 0, i64 [[X]] +// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [100 x i32], ptr [[A]], inrange i64 0, i64 [[X]] // CHECK-NEXT: load i32, ptr [[T0]], align 4 } Index: clang/test/CodeGen/matrix-type-operators.c =================================================================== --- clang/test/CodeGen/matrix-type-operators.c +++ clang/test/CodeGen/matrix-type-operators.c @@ -1153,7 +1153,7 @@ // CHECK-NEXT: [[PTR_IDX:%.*]] = getelementptr inbounds ptr, ptr [[PTR]], i64 1 // NOOPT-NEXT: [[PTR2:%.*]] = load ptr, ptr [[PTR_IDX]], align 8{{$}} // OPT-NEXT: [[PTR2:%.*]] = load ptr, ptr [[PTR_IDX]], align 8, !tbaa !{{[0-9]+}}{{$}} - // CHECK-NEXT: [[PTR2_IDX:%.*]] = getelementptr inbounds [6 x double], ptr [[PTR2]], i64 2 + // CHECK-NEXT: [[PTR2_IDX:%.*]] = getelementptr inbounds [6 x double], ptr [[PTR2]], inrange i64 2 // NOOPT-NEXT: [[MAT:%.*]] = load <6 x double>, ptr [[PTR2_IDX]], align 8{{$}} // OPT-NEXT: [[MAT:%.*]] = load <6 x double>, ptr [[PTR2_IDX]], align 8, !tbaa !{{[0-9]+}}{{$}} // CHECK-NEXT: [[MATEXT:%.*]] = extractelement <6 x double> [[MAT]], i64 [[IDX]] Index: clang/test/CodeGen/ubsan-pointer-overflow.c =================================================================== --- clang/test/CodeGen/ubsan-pointer-overflow.c +++ clang/test/CodeGen/ubsan-pointer-overflow.c @@ -7,7 +7,7 @@ // CHECK-LABEL: define{{.*}} void @fixed_len_array void fixed_len_array(int k) { - // CHECK: getelementptr inbounds [10 x [10 x i32]], ptr [[ARR:%.*]], i64 0, i64 [[IDXPROM:%.*]] + // CHECK: getelementptr inbounds [10 x [10 x i32]], ptr [[ARR:%.*]], inrange i64 0, i64 [[IDXPROM:%.*]] // CHECK-NEXT: [[SMUL:%.*]] = call { i64, i1 } @llvm.smul.with.overflow.i64(i64 40, i64 [[IDXPROM]]), !nosanitize // CHECK-NEXT: [[SMULOFLOW:%.*]] = extractvalue { i64, i1 } [[SMUL]], 1, !nosanitize // CHECK-NEXT: [[OR:%.+]] = or i1 [[SMULOFLOW]], false, !nosanitize @@ -16,7 +16,7 @@ // CHECK-NEXT: [[COMPGEP:%.*]] = add i64 [[BASE]], [[SMULVAL]], !nosanitize // CHECK: call void @__ubsan_handle_pointer_overflow{{.*}}, i64 [[BASE]], i64 [[COMPGEP]]){{.*}}, !nosanitize - // CHECK: getelementptr inbounds [10 x i32], ptr {{.*}}, i64 0, i64 [[IDXPROM1:%.*]] + // CHECK: getelementptr inbounds [10 x i32], ptr {{.*}}, inrange i64 0, i64 [[IDXPROM1:%.*]] // CHECK-NEXT: @llvm.smul.with.overflow.i64(i64 4, i64 [[IDXPROM1]]), !nosanitize // CHECK: call void @__ubsan_handle_pointer_overflow{{.*}} Index: clang/test/CodeGen/unaligned-expr.c =================================================================== --- clang/test/CodeGen/unaligned-expr.c +++ clang/test/CodeGen/unaligned-expr.c @@ -97,7 +97,7 @@ // ------------- void test10(void) { // CHECK: %la = alloca [10 x i32], align 1 - // CHECK: {{%.*}} = getelementptr inbounds [10 x i32], ptr %la, i64 0, i64 3 + // CHECK: {{%.*}} = getelementptr inbounds [10 x i32], ptr %la, inrange i64 0, i64 3 // CHECK: {{%.*}} = load i32, ptr {{%.*}}, align 1 // CHECK: store i32 {{%.*}}, ptr {{%.*}}, align 1 __unaligned int la[10]; Index: clang/test/CodeGen/union-tbaa1.c =================================================================== --- clang/test/CodeGen/union-tbaa1.c +++ clang/test/CodeGen/union-tbaa1.c @@ -13,10 +13,10 @@ // CHECK-NEXT: [[TMP:%.*]] = alloca [4 x [2 x %union.vect32]], align 8 // CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 32, ptr nonnull [[TMP]]) #[[ATTR3:[0-9]+]] // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[INDEX]], align 4, !tbaa [[TBAA2:![0-9]+]] -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARR]], i32 [[TMP0]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARR]], inrange i32 [[TMP0]] // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] // CHECK-NEXT: [[MUL:%.*]] = mul i32 [[TMP1]], [[NUM]] -// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [4 x [2 x %union.vect32]], ptr [[TMP]], i32 0, i32 [[TMP0]] +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [4 x [2 x %union.vect32]], ptr [[TMP]], inrange i32 0, i32 [[TMP0]] // CHECK-NEXT: store i32 [[MUL]], ptr [[ARRAYIDX2]], align 8, !tbaa [[TBAA6:![0-9]+]] // CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARR]], i32 [[TMP0]], i32 1 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] @@ -27,7 +27,7 @@ // CHECK-NEXT: store i32 [[TMP3]], ptr [[VEC]], align 4, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[INDEX]], align 4, !tbaa [[TBAA2]] // CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [4 x [2 x %union.vect32]], ptr [[TMP]], i32 0, i32 [[TMP4]], i32 1 -// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [2 x i16], ptr [[ARRAYIDX14]], i32 0, i32 1 +// CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [2 x i16], ptr [[ARRAYIDX14]], inrange i32 0, i32 1 // CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[ARRAYIDX15]], align 2, !tbaa [[TBAA6]] // CHECK-NEXT: [[CONV16:%.*]] = zext i16 [[TMP5]] to i32 // CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds i32, ptr [[VEC]], i32 1 Index: clang/test/CodeGen/vla.c =================================================================== --- clang/test/CodeGen/vla.c +++ clang/test/CodeGen/vla.c @@ -96,9 +96,9 @@ // CHECK-NEXT: [[N:%.*]] = load i32, ptr [[NV]], align 4 // CHECK-NEXT: [[P:%.*]] = load ptr, ptr [[PV]], align 4 // CHECK-NEXT: [[T0:%.*]] = mul nsw i32 1, [[N]] - // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [5 x double], ptr [[P]], i32 [[T0]] - // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds [5 x double], ptr [[T1]], i32 2 - // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [5 x double], ptr [[T2]], i32 0, i32 3 + // CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [5 x double], ptr [[P]], inrange i32 [[T0]] + // CHECK-NEXT: [[T2:%.*]] = getelementptr inbounds [5 x double], ptr [[T1]], inrange i32 2 + // CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [5 x double], ptr [[T2]], inrange i32 0, i32 3 // CHECK-NEXT: [[T4:%.*]] = load double, ptr [[T3]] // CHECK-NEXT: ret double [[T4]] return p[1][2][3]; Index: clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp =================================================================== --- clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp +++ clang/test/CodeGenCXX/amdgcn-automatic-variable.cpp @@ -30,7 +30,7 @@ // CHECK-NEXT: [[LVC_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[LVC]] to ptr // CHECK-NEXT: store i32 1, ptr [[LV1_ASCAST]], align 4 // CHECK-NEXT: store i32 2, ptr [[LV2_ASCAST]], align 4 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[LA_ASCAST]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[LA_ASCAST]], inrange i64 0, i64 0 // CHECK-NEXT: store i32 3, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store ptr [[LV1_ASCAST]], ptr [[LP1_ASCAST]], align 8 // CHECK-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [100 x i32], ptr [[LA_ASCAST]], i64 0, i64 0 Index: clang/test/CodeGenCXX/compound-literals.cpp =================================================================== --- clang/test/CodeGenCXX/compound-literals.cpp +++ clang/test/CodeGenCXX/compound-literals.cpp @@ -35,7 +35,7 @@ const int (&v)[2] = (int [2]) {1,2}; // CHECK: [[A:%[a-z0-9.]+]] = load ptr, ptr [[V]] - // CHECK-NEXT: [[A0ADDR:%[a-z0-9.]+]] = getelementptr inbounds [2 x i32], ptr [[A]], i32 0, {{.*}} 0 + // CHECK-NEXT: [[A0ADDR:%[a-z0-9.]+]] = getelementptr inbounds [2 x i32], ptr [[A]], inrange i32 0, {{.*}} 0 // CHECK-NEXT: [[A0:%[a-z0-9.]+]] = load i32, ptr [[A0ADDR]] // CHECK-NEXT: ret i32 [[A0]] return v[0]; Index: clang/test/CodeGenCXX/cxx1z-decomposition.cpp =================================================================== --- clang/test/CodeGenCXX/cxx1z-decomposition.cpp +++ clang/test/CodeGenCXX/cxx1z-decomposition.cpp @@ -78,7 +78,7 @@ // CHECK: load i32, i32* %[[b2]] // // CHECK: %[[c1c2:.*]] = load [2 x i32]*, [2 x i32]** @_ZDC2c12c2E - // CHECK: %[[c2:.*]] = getelementptr inbounds [2 x i32], [2 x i32]* %[[c1c2]], i64 0, i64 1 + // CHECK: %[[c2:.*]] = getelementptr inbounds [2 x i32], [2 x i32]* %[[c1c2]], inrange i64 0, i64 1 // CHECK: load i32, i32* %[[c2]] // // CHECK: %[[d1d2:.*]] = load <2 x i32>, <2 x i32>* @_ZDC2d12d2E Index: clang/test/CodeGenCXX/lambda-expressions.cpp =================================================================== --- clang/test/CodeGenCXX/lambda-expressions.cpp +++ clang/test/CodeGenCXX/lambda-expressions.cpp @@ -144,13 +144,13 @@ // CHECK: br label // CHECK: %[[I:.*]] = phi i64 [ 0, %{{.*}} ], [ %[[I_NEXT:.*]], {{.*}} ] // CHECK: %[[DST_I:.*]] = getelementptr {{.*}} ptr %[[DST_0]], i64 %[[I]] - // CHECK: %[[SRC_I:.*]] = getelementptr {{.*}} ptr %[[SRC]], i64 0, i64 %[[I]] + // CHECK: %[[SRC_I:.*]] = getelementptr {{.*}} ptr %[[SRC]], inrange i64 0, i64 %[[I]] // // CHECK: %[[DST_I_0:.*]] = getelementptr {{.*}} ptr %[[DST_I]], i64 0, i64 0 // CHECK: br label // CHECK: %[[J:.*]] = phi i64 [ 0, %{{.*}} ], [ %[[J_NEXT:.*]], {{.*}} ] // CHECK: %[[DST_I_J:.*]] = getelementptr {{.*}} ptr %[[DST_I_0]], i64 %[[J]] - // CHECK: %[[SRC_I_J:.*]] = getelementptr {{.*}} ptr %[[SRC_I]], i64 0, i64 %[[J]] + // CHECK: %[[SRC_I_J:.*]] = getelementptr {{.*}} ptr %[[SRC_I]], inrange i64 0, i64 %[[J]] // // CHECK: invoke void @_ZN7pr285954TempC1Ev // CHECK: invoke void @_ZN7pr285951AC1ERKS0_RKNS_4TempE Index: clang/test/CodeGenCXX/no-odr-use.cpp =================================================================== --- clang/test/CodeGenCXX/no-odr-use.cpp +++ clang/test/CodeGenCXX/no-odr-use.cpp @@ -15,14 +15,14 @@ return [] (int n, int A::*p) { // CHECK: br i1 return (n >= 0 - // CHECK: getelementptr inbounds [3 x i32], ptr getelementptr inbounds ({{.*}} @__const._Z1fi.a, i32 0, i32 2), i64 0, i64 % + // CHECK: getelementptr inbounds [3 x i32], ptr getelementptr inbounds ({{.*}} @__const._Z1fi.a, i32 0, i32 2), inrange i64 0, i64 % ? a.arr[n] // CHECK: br i1 : (n == -1 // CHECK: getelementptr inbounds i8, ptr @__const._Z1fi.a, i64 % // CHECK: load i32 ? a.*p - // CHECK: getelementptr inbounds [2 x i32], ptr getelementptr inbounds ({{.*}} @__const._Z1fi.a, i32 0, i32 1), i64 0, i64 % + // CHECK: getelementptr inbounds [2 x i32], ptr getelementptr inbounds ({{.*}} @__const._Z1fi.a, i32 0, i32 1), inrange i64 0, i64 % // CHECK: load i32 : a.y[2 - n])); }(i, &A::x); @@ -38,8 +38,8 @@ // CHECK-LABEL: define{{.*}} void @_ZN7PR422765State16syncDirtyObjectsEv( void State::syncDirtyObjects() { for (int i = 0; i < sizeof(m) / sizeof(m[0]); ++i) - // CHECK-CXX11: getelementptr inbounds [2 x { i64, i64 }], ptr @_ZN7PR422765State1mE.const, i64 0, i64 % - // CHECK-CXX2A: getelementptr inbounds [2 x { i64, i64 }], ptr @_ZN7PR422765State1mE, i64 0, i64 % + // CHECK-CXX11: getelementptr inbounds [2 x { i64, i64 }], ptr @_ZN7PR422765State1mE.const, inrange i64 0, i64 % + // CHECK-CXX2A: getelementptr inbounds [2 x { i64, i64 }], ptr @_ZN7PR422765State1mE, inrange i64 0, i64 % (this->*m[i])(); } } Index: clang/test/CodeGenCXX/pr45964-decomp-transform.cpp =================================================================== --- clang/test/CodeGenCXX/pr45964-decomp-transform.cpp +++ clang/test/CodeGenCXX/pr45964-decomp-transform.cpp @@ -16,7 +16,7 @@ // CHECK-NEXT: [[BODY]]: // CHECK-NEXT: [[CUR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[NEXT:%.*]], %[[BODY]] ] // CHECK-NEXT: [[DEST:%.*]] = getelementptr inbounds i32, ptr [[BEGIN]], i64 [[CUR]] -// CHECK-NEXT: [[SRC:%.*]] = getelementptr inbounds [1 x i32], ptr @a, i64 0, i64 [[CUR]] +// CHECK-NEXT: [[SRC:%.*]] = getelementptr inbounds [1 x i32], ptr @a, inrange i64 0, i64 [[CUR]] // CHECK-NEXT: [[X:%.*]] = load i32, ptr [[SRC]] // CHECK-NEXT: store i32 [[X]], ptr [[DEST]] // CHECK-NEXT: [[NEXT]] = add nuw i64 [[CUR]], 1 Index: clang/test/CodeGenObjC/arc.m =================================================================== --- clang/test/CodeGenObjC/arc.m +++ clang/test/CodeGenObjC/arc.m @@ -511,7 +511,7 @@ // CHECK-NEXT: [[T1:%.*]] = call i8* @test19_helper(){{.*}} [ "clang.arc.attachedcall"(i8* (i8*)* @llvm.objc.retainAutoreleasedReturnValue) ] // CHECK-NEXT: call void (...) @llvm.objc.clang.arc.noop.use(i8* [[T1]]) - // CHECK-NEXT: [[SLOT:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[X]], i64 0, i64 2 + // CHECK-NEXT: [[SLOT:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[X]], inrange i64 0, i64 2 // CHECK-NEXT: [[T0:%.*]] = load i8*, i8** [[SLOT]] // CHECK-NEXT: store i8* [[T1]], i8** [[SLOT]] // CHECK-NEXT: call void @llvm.objc.release(i8* [[T0]]) [[NUW]] Index: clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl =================================================================== --- clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl +++ clang/test/CodeGenOpenCL/amdgcn-automatic-variable.cl @@ -32,7 +32,7 @@ // CHECK: store i32 2, ptr addrspace(5) %lv2 int lv2 = 2; - // CHECK: %[[arrayidx:.*]] = getelementptr inbounds [100 x i32], ptr addrspace(5) %la, i64 0, i64 0 + // CHECK: %[[arrayidx:.*]] = getelementptr inbounds [100 x i32], ptr addrspace(5) %la, inrange i64 0, i64 0 // CHECK: store i32 3, ptr addrspace(5) %[[arrayidx]], align 4 int la[100]; la[0] = 3; Index: clang/test/OpenMP/align_clause_codegen.cpp =================================================================== --- clang/test/OpenMP/align_clause_codegen.cpp +++ clang/test/OpenMP/align_clause_codegen.cpp @@ -149,7 +149,7 @@ // CHECK-32-NEXT: entry: // CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK-32-NEXT: [[DOTFOO__VOID_ADDR:%.*]] = call ptr @__kmpc_aligned_alloc(i32 [[TMP0]], i32 16, i32 8000, ptr inttoptr (i32 6 to ptr)) -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x double], ptr [[DOTFOO__VOID_ADDR]], i32 0, i32 0 +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x double], ptr [[DOTFOO__VOID_ADDR]], inrange i32 0, i32 0 // CHECK-32-NEXT: [[TMP1:%.*]] = load double, ptr [[ARRAYIDX]], align 8 // CHECK-32-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTFOO__VOID_ADDR]], ptr inttoptr (i32 6 to ptr)) // CHECK-32-NEXT: ret double [[TMP1]] @@ -224,7 +224,7 @@ // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]]) // CHECK-NEXT: [[DOTFOO__VOID_ADDR:%.*]] = call ptr @__kmpc_aligned_alloc(i32 [[TMP0]], i64 16, i64 8000, ptr inttoptr (i64 6 to ptr)) -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x double], ptr [[DOTFOO__VOID_ADDR]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x double], ptr [[DOTFOO__VOID_ADDR]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[ARRAYIDX]], align 16 // CHECK-NEXT: call void @__kmpc_free(i32 [[TMP0]], ptr [[DOTFOO__VOID_ADDR]], ptr inttoptr (i64 6 to ptr)) // CHECK-NEXT: ret double [[TMP1]] Index: clang/test/OpenMP/declare_mapper_codegen.cpp =================================================================== --- clang/test/OpenMP/declare_mapper_codegen.cpp +++ clang/test/OpenMP/declare_mapper_codegen.cpp @@ -956,7 +956,7 @@ // CK3-DAG: [[CBP2:%.+]] = bitcast i8** [[BP2]] to [10 x %class.C]** // CK3-DAG: [[CP2:%.+]] = bitcast i8** [[P2]] to %class.C** // CK3-DAG: store [10 x %class.C]* [[CVAL]], [10 x %class.C]** [[CBP2]] -// CK3-DAG: [[CVALGEP:%.+]] = getelementptr inbounds {{.+}}[[CVAL]], i{{64|32}} 0, i{{64|32}} 0 +// CK3-DAG: [[CVALGEP:%.+]] = getelementptr inbounds {{.+}}[[CVAL]], inrange i{{64|32}} 0, i{{64|32}} 0 // CK3-DAG: store %class.C* [[CVALGEP]], %class.C** [[CP2]] // CK3-DAG: store i8* bitcast (void (i8*, i8*, i8*, i64, i64, i8*)* [[MPRFUNC]] to i8*), i8** [[MPR2]] // CK3: call void [[KERNEL:@.+]](%class.B* [[BVAL]], [10 x %class.C]* [[CVAL]]) Index: clang/test/OpenMP/distribute_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_firstprivate_codegen.cpp +++ clang/test/OpenMP/distribute_firstprivate_codegen.cpp @@ -748,12 +748,12 @@ // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP20]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1069,12 +1069,12 @@ // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1419,11 +1419,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP21]] +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP21]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP20]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1738,11 +1738,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/distribute_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_lastprivate_codegen.cpp +++ clang/test/OpenMP/distribute_lastprivate_codegen.cpp @@ -725,12 +725,12 @@ // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1066,12 +1066,12 @@ // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1433,11 +1433,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1772,11 +1772,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp +++ clang/test/OpenMP/distribute_parallel_for_firstprivate_codegen.cpp @@ -1161,12 +1161,12 @@ // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -1606,12 +1606,12 @@ // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -2082,11 +2082,11 @@ // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2521,11 +2521,11 @@ // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: Index: clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp +++ clang/test/OpenMP/distribute_parallel_for_lastprivate_codegen.cpp @@ -1147,12 +1147,12 @@ // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1630,12 +1630,12 @@ // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2141,11 +2141,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2618,11 +2618,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp +++ clang/test/OpenMP/distribute_parallel_for_private_codegen.cpp @@ -789,12 +789,12 @@ // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1141,12 +1141,12 @@ // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1502,11 +1502,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1848,11 +1848,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -1231,12 +1231,12 @@ // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP9]] // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -1690,12 +1690,12 @@ // CHECK8-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK8-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK8-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK8-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK8-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK8-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK8-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK8-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK8: omp.body.continue: @@ -2180,11 +2180,11 @@ // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2633,11 +2633,11 @@ // CHECK10-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK10-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK10-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK10-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK10-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK10-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2779,12 +2779,12 @@ // CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK12-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK12-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK12-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK12-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: @@ -2886,12 +2886,12 @@ // CHECK12-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK12-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK12-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK12-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK12-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK12-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK12-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK12-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: @@ -3083,11 +3083,11 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK14-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK14-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK14-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK14-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK14-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK14-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -3188,11 +3188,11 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK14-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK14-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK14-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK14-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK14-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK14-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK14-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: Index: clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -1221,12 +1221,12 @@ // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1718,12 +1718,12 @@ // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2243,11 +2243,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2734,11 +2734,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2926,12 +2926,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], inrange i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3094,12 +3094,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], inrange i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3332,11 +3332,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3498,11 +3498,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp +++ clang/test/OpenMP/distribute_parallel_for_simd_private_codegen.cpp @@ -850,12 +850,12 @@ // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1216,12 +1216,12 @@ // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1591,11 +1591,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1951,11 +1951,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2109,12 +2109,12 @@ // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2248,12 +2248,12 @@ // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2458,11 +2458,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2595,11 +2595,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/distribute_private_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_private_codegen.cpp +++ clang/test/OpenMP/distribute_private_codegen.cpp @@ -547,12 +547,12 @@ // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -863,12 +863,12 @@ // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1159,11 +1159,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1473,11 +1473,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/distribute_simd_firstprivate_codegen.cpp @@ -801,12 +801,12 @@ // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM11]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP20]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1129,12 +1129,12 @@ // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1486,11 +1486,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP20:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP21]] +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP21]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP20]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1812,11 +1812,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1958,12 +1958,12 @@ // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2065,12 +2065,12 @@ // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2262,11 +2262,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2367,11 +2367,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/distribute_simd_lastprivate_codegen.cpp @@ -780,12 +780,12 @@ // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1128,12 +1128,12 @@ // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1502,11 +1502,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1848,11 +1848,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2040,12 +2040,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], inrange i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2208,12 +2208,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i64 0, i64 [[IDXPROM9]] +// CHECK13-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], inrange i64 0, i64 [[IDXPROM9]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2446,11 +2446,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR6]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2612,11 +2612,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR4]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC5]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP8]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR6]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/distribute_simd_private_codegen.cpp =================================================================== --- clang/test/OpenMP/distribute_simd_private_codegen.cpp +++ clang/test/OpenMP/distribute_simd_private_codegen.cpp @@ -603,12 +603,12 @@ // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -937,12 +937,12 @@ // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1255,11 +1255,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1587,11 +1587,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1751,12 +1751,12 @@ // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1915,12 +1915,12 @@ // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK13-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK13-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP9]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2131,11 +2131,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2293,11 +2293,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK15-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK15-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK15-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/for_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/for_firstprivate_codegen.cpp +++ clang/test/OpenMP/for_firstprivate_codegen.cpp @@ -338,11 +338,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -610,12 +610,12 @@ // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP9]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM11]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX12]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: Index: clang/test/OpenMP/for_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/for_lastprivate_codegen.cpp +++ clang/test/OpenMP/for_lastprivate_codegen.cpp @@ -518,11 +518,11 @@ // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR5]], align 4 @@ -1260,12 +1260,12 @@ // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 128 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -2942,11 +2942,11 @@ // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX8]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[SIVAR5]], align 4 @@ -3702,12 +3702,12 @@ // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 128 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX10]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP16]]) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: Index: clang/test/OpenMP/for_private_codegen.cpp =================================================================== --- clang/test/OpenMP/for_private_codegen.cpp +++ clang/test/OpenMP/for_private_codegen.cpp @@ -238,12 +238,12 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -508,12 +508,12 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: Index: clang/test/OpenMP/for_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/for_reduction_codegen.cpp +++ clang/test/OpenMP/for_reduction_codegen.cpp @@ -583,7 +583,7 @@ // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB3:[0-9]+]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() @@ -760,12 +760,12 @@ // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP16]] to i32 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1015,7 +1015,7 @@ // CHECK1-NEXT: [[TMP5:%.*]] = mul nsw i64 1, [[TMP1]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP5]] // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64 // CHECK1-NEXT: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, [[TMP7]] @@ -1047,14 +1047,14 @@ // CHECK1-NEXT: [[TMP19:%.*]] = sub i64 [[TMP17]], [[TMP18]] // CHECK1-NEXT: [[TMP20:%.*]] = sdiv exact i64 [[TMP19]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP20]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[TMP4]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[TMP4]], inrange i64 0, i64 1 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[ARRAYIDX8]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], ptr [[ARRAYDECAY]], i64 1 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = sext i32 [[TMP22]] to i64 // CHECK1-NEXT: [[LB_ADD_LEN11:%.*]] = add nsw i64 0, [[TMP23]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[TMP4]], i64 0, i64 [[LB_ADD_LEN11]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [4 x %struct.S]], ptr [[TMP4]], inrange i64 0, i64 [[LB_ADD_LEN11]] // CHECK1-NEXT: [[ARRAYDECAY13:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[ARRAYIDX12]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[ARRAYDECAY13]], i64 2 // CHECK1-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 @@ -2452,8 +2452,8 @@ // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP0]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP0]], i64 0, i64 4 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP0]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[TMP0]], inrange i64 0, i64 4 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S], ptr [[VVAR22]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP1]] @@ -2634,9 +2634,9 @@ // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP2]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP2]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], inrange i64 0, i64 2 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[VAR34]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] @@ -2819,9 +2819,9 @@ // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP2]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], inrange i64 0, i64 1 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[VAR34]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] @@ -3005,9 +3005,9 @@ // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP2]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP2]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], i64 0, i64 3 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S], ptr [[TMP3]], inrange i64 0, i64 3 // CHECK1-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[ARRAYIDX3]] to i64 // CHECK1-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 // CHECK1-NEXT: [[TMP6:%.*]] = sub i64 [[TMP4]], [[TMP5]] @@ -3568,12 +3568,12 @@ // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP5]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -3827,12 +3827,12 @@ // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], inrange i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -3968,8 +3968,8 @@ // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [42 x %struct.S.0], ptr [[TMP0]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [42 x %struct.S.0], ptr [[TMP0]], i64 0, i64 40 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [42 x %struct.S.0], ptr [[TMP0]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [42 x %struct.S.0], ptr [[TMP0]], inrange i64 0, i64 40 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [40 x %struct.S.0], ptr [[ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S_0]], ptr [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] @@ -4018,12 +4018,12 @@ // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP20]], ptr [[ARRAYIDX6]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP3]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP3]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP22]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: Index: clang/test/OpenMP/for_reduction_codegen_UDR.cpp =================================================================== --- clang/test/OpenMP/for_reduction_codegen_UDR.cpp +++ clang/test/OpenMP/for_reduction_codegen_UDR.cpp @@ -657,7 +657,7 @@ // CHECK1-NEXT: store ptr [[S_ARR]], ptr [[VAR3]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VAR]], align 8 // CHECK1-NEXT: call void (ptr, i32, ptr, ...) @__kmpc_fork_call(ptr @[[GLOB1]], i32 6, ptr @main.omp_outlined, ptr [[T_VAR]], ptr [[TMP0]], ptr [[VAR1]], ptr [[T_VAR1]], ptr [[VEC]], ptr [[S_ARR]]) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 // CHECK1-NEXT: [[TMP3:%.*]] = call ptr @llvm.stacksave() @@ -825,12 +825,12 @@ // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[TMP5]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[TMP5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX11]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP19]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1076,7 +1076,7 @@ // CHECK1-NEXT: [[TMP5:%.*]] = mul nsw i64 1, [[TMP1]] // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP2]], i64 [[TMP5]] // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: [[TMP7:%.*]] = sext i32 [[TMP6]] to i64 // CHECK1-NEXT: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, [[TMP7]] @@ -1110,14 +1110,14 @@ // CHECK1-NEXT: [[TMP19:%.*]] = sub i64 [[TMP17]], [[TMP18]] // CHECK1-NEXT: [[TMP20:%.*]] = sdiv exact i64 [[TMP19]], ptrtoint (ptr getelementptr (i32, ptr null, i32 1) to i64) // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[VLA7]], i64 [[TMP20]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], ptr [[TMP4]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], ptr [[TMP4]], inrange i64 0, i64 1 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[ARRAYIDX9]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], ptr [[ARRAYDECAY]], i64 1 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP3]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 // CHECK1-NEXT: [[TMP23:%.*]] = sext i32 [[TMP22]] to i64 // CHECK1-NEXT: [[LB_ADD_LEN12:%.*]] = add nsw i64 0, [[TMP23]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], ptr [[TMP4]], i64 0, i64 [[LB_ADD_LEN12]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [4 x %struct.S.0]], ptr [[TMP4]], inrange i64 0, i64 [[LB_ADD_LEN12]] // CHECK1-NEXT: [[ARRAYDECAY14:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[ARRAYIDX13]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [[STRUCT_S_0]], ptr [[ARRAYDECAY14]], i64 2 // CHECK1-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[ARRAYIDX15]] to i64 @@ -1878,8 +1878,8 @@ // CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[TMP0]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[TMP0]], i64 0, i64 4 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[TMP0]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[TMP0]], inrange i64 0, i64 4 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [5 x %struct.S.0], ptr [[VVAR22]], i32 0, i32 0 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 5 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP1]] @@ -2067,9 +2067,9 @@ // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 // CHECK1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[TMP2]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[TMP2]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[_TMP1]], align 8 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[TMP3]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[TMP3]], inrange i64 0, i64 2 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[VAR34]], i32 0, i32 0 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr [[STRUCT_S_0:%.*]], ptr [[ARRAY_BEGIN]], i64 2 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP4]] @@ -2612,12 +2612,12 @@ // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX11]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP18]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -2868,12 +2868,12 @@ // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], inrange i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP16]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -2981,8 +2981,8 @@ // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_UB]], align 4 // CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [42 x %struct.S], ptr [[TMP0]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [42 x %struct.S], ptr [[TMP0]], i64 0, i64 40 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [42 x %struct.S], ptr [[TMP0]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [42 x %struct.S], ptr [[TMP0]], inrange i64 0, i64 40 // CHECK1-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [40 x %struct.S], ptr [[ARR4]], i32 0, i32 0 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr [[STRUCT_S:%.*]], ptr [[ARRAY_BEGIN]], i64 40 // CHECK1-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP6]] @@ -3035,12 +3035,12 @@ // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP2]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP20]], ptr [[ARRAYIDX8]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP3]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX10]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP22]]) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -3366,12 +3366,12 @@ // CHECK3-NEXT: [[CONV:%.*]] = fptosi float [[TMP3]] to i32 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK3-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP10]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM11]] +// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [4 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM11]] // CHECK3-NEXT: [[CALL13:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX12]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP5]]) // CHECK3-NEXT: br label [[FOR_INC:%.*]] // CHECK3: for.inc: @@ -3380,7 +3380,7 @@ // CHECK3-NEXT: store i32 [[INC]], ptr [[I]], align 4 // CHECK3-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] // CHECK3: for.end: -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 1 +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 1 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64 // CHECK3-NEXT: [[TMP10:%.*]] = call ptr @llvm.stacksave() @@ -3614,12 +3614,12 @@ // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK3-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[_TMP1]], align 8 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK3-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP5]]) // CHECK3-NEXT: br label [[FOR_INC:%.*]] // CHECK3: for.inc: @@ -3642,12 +3642,12 @@ // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I6]], align 4 // CHECK3-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM10]] +// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM10]] // CHECK3-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX11]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[_TMP5]], align 8 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I6]], align 4 // CHECK3-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM12]] +// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM12]] // CHECK3-NEXT: [[CALL14:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX13]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP13]]) // CHECK3-NEXT: br label [[FOR_INC15:%.*]] // CHECK3: for.inc15: @@ -3670,12 +3670,12 @@ // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[I20]], align 4 // CHECK3-NEXT: [[IDXPROM24:%.*]] = sext i32 [[TMP20]] to i64 -// CHECK3-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM24]] +// CHECK3-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM24]] // CHECK3-NEXT: store i32 [[TMP19]], ptr [[ARRAYIDX25]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load ptr, ptr [[_TMP19]], align 8 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[I20]], align 4 // CHECK3-NEXT: [[IDXPROM26:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK3-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM26]] +// CHECK3-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM26]] // CHECK3-NEXT: [[CALL28:%.*]] = call noundef nonnull align 4 dereferenceable(12) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(12) [[ARRAYIDX27]], ptr noundef nonnull align 4 dereferenceable(12) [[TMP21]]) // CHECK3-NEXT: br label [[FOR_INC29:%.*]] // CHECK3: for.inc29: Index: clang/test/OpenMP/for_scan_codegen.cpp =================================================================== --- clang/test/OpenMP/for_scan_codegen.cpp +++ clang/test/OpenMP/for_scan_codegen.cpp @@ -40,7 +40,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -133,7 +133,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) @@ -180,7 +180,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -281,7 +281,7 @@ // CHECK: [[BASE_IDX_SUB_1:%.+]] = sub nuw i64 [[BASE_IDX]], 1 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX_SUB_1]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) Index: clang/test/OpenMP/for_simd_scan_codegen.cpp =================================================================== --- clang/test/OpenMP/for_simd_scan_codegen.cpp +++ clang/test/OpenMP/for_simd_scan_codegen.cpp @@ -40,7 +40,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -133,7 +133,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) @@ -180,7 +180,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -281,7 +281,7 @@ // CHECK: [[BASE_IDX_SUB_1:%.+]] = sub nuw i64 [[BASE_IDX]], 1 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX_SUB_1]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) Index: clang/test/OpenMP/irbuilder_simd_aligned.cpp =================================================================== --- clang/test/OpenMP/irbuilder_simd_aligned.cpp +++ clang/test/OpenMP/irbuilder_simd_aligned.cpp @@ -60,7 +60,7 @@ // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], inrange i64 0, i64 [[IDXPROM]] // CHECK-NEXT: store i32 [[TMP1]], ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: br label [[FOR_INC:%.*]] // CHECK: for.inc: @@ -110,7 +110,7 @@ // CHECK-NEXT: [[ADD8:%.*]] = fadd float [[ADD]], [[CONV7]] // CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[I1]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], i64 0, i64 [[IDXPROM9]] +// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [32 x i32], ptr [[D]], inrange i64 0, i64 [[IDXPROM9]] // CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK-NEXT: [[CONV11:%.*]] = sitofp i32 [[TMP16]] to float // CHECK-NEXT: [[ADD12:%.*]] = fadd float [[ADD8]], [[CONV11]] Index: clang/test/OpenMP/master_taskloop_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/master_taskloop_reduction_codegen.cpp +++ clang/test/OpenMP/master_taskloop_reduction_codegen.cpp @@ -84,9 +84,9 @@ // CHECK-DAG: store ptr @[[RED_COMB1:.+]], ptr [[TMP25]], // CHECK-DAG: [[TMP26:%.*]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK-DAG: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 4, i1 false) -// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 0 +// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 0 // CHECK-DAG: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, % -// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 [[LB_ADD_LEN]] +// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 [[LB_ADD_LEN]] // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], // CHECK-DAG: [[TMP28]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_4:%.+]], i32 0, i32 0 // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], Index: clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp +++ clang/test/OpenMP/master_taskloop_simd_reduction_codegen.cpp @@ -80,9 +80,9 @@ // CHECK-DAG: store ptr @[[RED_COMB1:.+]], ptr [[TMP25]], // CHECK-DAG: [[TMP26:%.*]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK-DAG: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 4, i1 false) -// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 0 +// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 0 // CHECK-DAG: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, % -// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 [[LB_ADD_LEN]] +// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 [[LB_ADD_LEN]] // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], // CHECK-DAG: [[TMP28]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_4:%.+]], i32 0, i32 0 // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], Index: clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp +++ clang/test/OpenMP/nvptx_distribute_parallel_generic_mode_codegen.cpp @@ -299,17 +299,17 @@ // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[CALL]], [[CALL9]] // CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B4]], i64 0, i64 [[IDXPROM]] +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B4]], inrange i64 0, i64 [[IDXPROM]] // CHECK4-NEXT: [[CALL11:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX]]) #[[ATTR8]] // CHECK4-NEXT: [[ADD12:%.*]] = add nsw i32 [[ADD10]], [[CALL11]] // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], ptr [[C5]], i64 0, i64 [[IDXPROM13]] +// CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], ptr [[C5]], inrange i64 0, i64 [[IDXPROM13]] // CHECK4-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX14]]) #[[ATTR8]] // CHECK4-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD12]], [[CALL15]] // CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[I6]], align 4 // CHECK4-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], i64 0, i64 [[IDXPROM17]] +// CHECK4-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], inrange i64 0, i64 [[IDXPROM17]] // CHECK4-NEXT: [[CALL19:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX18]]) #[[ATTR8]] // CHECK4-NEXT: [[ADD20:%.*]] = add nsw i32 [[ADD16]], [[CALL19]] // CHECK4-NEXT: store i32 [[ADD20]], ptr [[TMP1]], align 4 @@ -609,15 +609,15 @@ // CHECK5-NEXT: [[CALL7:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[TMP1]]) #[[ATTR8]] // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CALL]], [[CALL7]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I5]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B3]], i32 0, i32 [[TMP17]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B3]], inrange i32 0, i32 [[TMP17]] // CHECK5-NEXT: [[CALL9:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX]]) #[[ATTR8]] // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD8]], [[CALL9]] // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[I5]], align 4 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[C4]], i32 0, i32 [[TMP18]] +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[C4]], inrange i32 0, i32 [[TMP18]] // CHECK5-NEXT: [[CALL12:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX11]]) #[[ATTR8]] // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i32 [[ADD10]], [[CALL12]] // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[I5]], align 4 -// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], i32 0, i32 [[TMP19]] +// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP4]], inrange i32 0, i32 [[TMP19]] // CHECK5-NEXT: [[CALL15:%.*]] = call noundef i32 @_Z3fooPi(ptr noundef [[ARRAYIDX14]]) #[[ATTR8]] // CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[ADD13]], [[CALL15]] // CHECK5-NEXT: store i32 [[ADD16]], ptr [[TMP1]], align 4 Index: clang/test/OpenMP/nvptx_parallel_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_parallel_codegen.cpp +++ clang/test/OpenMP/nvptx_parallel_codegen.cpp @@ -209,7 +209,7 @@ // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -472,7 +472,7 @@ // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK2-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP7]], 1 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/nvptx_parallel_for_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_parallel_for_codegen.cpp +++ clang/test/OpenMP/nvptx_parallel_for_codegen.cpp @@ -54,7 +54,7 @@ // CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1 // CHECK-NEXT: store ptr [[D]], ptr [[TMP5]], align 8 // CHECK-NEXT: call void @__kmpc_parallel_51(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l13_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 2) -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 3 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 3 // CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX]], align 4 @@ -126,7 +126,7 @@ // CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP14]], [[TMP12]] // CHECK-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/nvptx_target_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_codegen.cpp +++ clang/test/OpenMP/nvptx_target_codegen.cpp @@ -263,7 +263,7 @@ // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP10]] to double // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -275,8 +275,8 @@ // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK1-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK1-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP12:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[TMP12]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -347,7 +347,7 @@ // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK1-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -461,7 +461,7 @@ // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -633,7 +633,7 @@ // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP9]], 1 // CHECK2-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[CONV:%.*]] = fpext float [[TMP10]] to double // CHECK2-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -645,8 +645,8 @@ // CHECK2-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK2-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK2-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP12:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK2-NEXT: [[ADD13:%.*]] = fadd double [[TMP12]], 1.000000e+00 // CHECK2-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -717,7 +717,7 @@ // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK2-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK2-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -831,7 +831,7 @@ // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK2-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/nvptx_target_parallel_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_parallel_codegen.cpp +++ clang/test/OpenMP/nvptx_target_parallel_codegen.cpp @@ -145,7 +145,7 @@ // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -246,7 +246,7 @@ // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp +++ clang/test/OpenMP/nvptx_target_parallel_num_threads_codegen.cpp @@ -143,7 +143,7 @@ // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -247,7 +247,7 @@ // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK2-NEXT: store i16 [[CONV2]], ptr [[TMP1]], align 2 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP2]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/nvptx_target_parallel_proc_bind_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_parallel_proc_bind_codegen.cpp +++ clang/test/OpenMP/nvptx_target_parallel_proc_bind_codegen.cpp @@ -305,7 +305,7 @@ // CHECK45-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK45-64-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK45-64-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK45-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK45-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK45-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -441,7 +441,7 @@ // CHECK45-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK45-32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK45-32-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK45-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK45-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK45-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -577,7 +577,7 @@ // CHECK45-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK45-32-EX-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK45-32-EX-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK45-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK45-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK45-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -713,7 +713,7 @@ // CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK-64-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK-64-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -849,7 +849,7 @@ // CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK-32-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK-32-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -985,7 +985,7 @@ // CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK-32-EX-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK-32-EX-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/nvptx_target_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_simd_codegen.cpp +++ clang/test/OpenMP/nvptx_target_simd_codegen.cpp @@ -103,7 +103,7 @@ // CHECK45-64-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-64: omp.body.continue: @@ -173,7 +173,7 @@ // CHECK45-64-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK45-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], 1 @@ -228,7 +228,7 @@ // CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK45-64-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -279,7 +279,7 @@ // CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK45-64-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -347,7 +347,7 @@ // CHECK45-32-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK45-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32: omp.body.continue: @@ -416,7 +416,7 @@ // CHECK45-32-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK45-32-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK45-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], 1 @@ -470,7 +470,7 @@ // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP4]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP4]] // CHECK45-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK45-32-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -520,7 +520,7 @@ // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP5]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP5]] // CHECK45-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK45-32-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -588,7 +588,7 @@ // CHECK45-32-EX-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK45-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32-EX: omp.body.continue: @@ -657,7 +657,7 @@ // CHECK45-32-EX-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK45-32-EX-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK45-32-EX-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], 1 @@ -711,7 +711,7 @@ // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP4]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP4]] // CHECK45-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK45-32-EX-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -761,7 +761,7 @@ // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP5]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP5]] // CHECK45-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK45-32-EX-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -830,7 +830,7 @@ // CHECK-64-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-64: omp.body.continue: @@ -900,7 +900,7 @@ // CHECK-64-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK-64-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], 1 @@ -955,7 +955,7 @@ // CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK-64-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -1006,7 +1006,7 @@ // CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK-64-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -1074,7 +1074,7 @@ // CHECK-32-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32: omp.body.continue: @@ -1143,7 +1143,7 @@ // CHECK-32-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK-32-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], 1 @@ -1197,7 +1197,7 @@ // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP4]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP4]] // CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK-32-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -1247,7 +1247,7 @@ // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP5]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP5]] // CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK-32-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -1315,7 +1315,7 @@ // CHECK-32-EX-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32-EX: omp.body.continue: @@ -1384,7 +1384,7 @@ // CHECK-32-EX-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD5]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP8]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP8]] // CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: [[CONV:%.*]] = sext i16 [[TMP9]] to i32 // CHECK-32-EX-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV]], 1 @@ -1438,7 +1438,7 @@ // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP4]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP4]] // CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -1488,7 +1488,7 @@ // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP5]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP5]] // CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] Index: clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp +++ clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp @@ -344,7 +344,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4 @@ -611,7 +611,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 // CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1 @@ -802,7 +802,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -1027,10 +1027,10 @@ // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1333,10 +1333,10 @@ // CHECK1-NEXT: [[ADD33:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[I9]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[J10]], align 4 // CHECK1-NEXT: [[IDXPROM34:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK1-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM34]] +// CHECK1-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM34]] // CHECK1-NEXT: store i32 [[ADD33]], ptr [[ARRAYIDX35]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1599,7 +1599,7 @@ // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1894,7 +1894,7 @@ // CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[I4]], align 4 // CHECK2-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4 @@ -2161,7 +2161,7 @@ // CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 // CHECK2-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32 // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1 @@ -2352,7 +2352,7 @@ // CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -2577,10 +2577,10 @@ // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]] // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4 // CHECK2-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] +// CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM11]] // CHECK2-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -2878,10 +2878,10 @@ // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[I9]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[J10]], align 4 // CHECK2-NEXT: [[IDXPROM30:%.*]] = sext i32 [[TMP24]] to i64 -// CHECK2-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM30]] +// CHECK2-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM30]] // CHECK2-NEXT: store i32 [[ADD29]], ptr [[ARRAYIDX31]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -3144,7 +3144,7 @@ // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I4]], align 4 // CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]] +// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM7]] // CHECK2-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -3432,7 +3432,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP19]] // CHECK3-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[I3]], align 4 // CHECK3-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4 @@ -3693,7 +3693,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1 @@ -3878,7 +3878,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK3-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4 @@ -4097,9 +4097,9 @@ // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -4406,9 +4406,9 @@ // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[J12]], align 4 // CHECK3-NEXT: [[ADD36:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[I11]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP23]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP23]] // CHECK3-NEXT: [[TMP24:%.*]] = load i32, ptr [[J12]], align 4 -// CHECK3-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP24]] +// CHECK3-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP24]] // CHECK3-NEXT: store i32 [[ADD36]], ptr [[ARRAYIDX37]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -4664,7 +4664,7 @@ // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i32 [[TMP14]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX5]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp +++ clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp @@ -344,7 +344,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] @@ -635,7 +635,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]] // CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1 @@ -845,7 +845,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] @@ -1085,10 +1085,10 @@ // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM11]] // CHECK1-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1392,7 +1392,7 @@ // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP19]] // CHECK2-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK2-NEXT: store i32 [[TMP20]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP16]] @@ -1677,7 +1677,7 @@ // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP22]] // CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1 @@ -1881,7 +1881,7 @@ // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1 // CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] @@ -2115,9 +2115,9 @@ // CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]] // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP15]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP15]] // CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP16]] +// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP16]] // CHECK2-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: Index: clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp +++ clang/test/OpenMP/nvptx_target_teams_distribute_simd_codegen.cpp @@ -181,7 +181,7 @@ // CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-64-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -341,7 +341,7 @@ // CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK45-64-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK45-64-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 @@ -468,7 +468,7 @@ // CHECK45-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK45-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -612,10 +612,10 @@ // CHECK45-64-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] // CHECK45-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK45-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-64-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK45-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] +// CHECK45-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM11]] // CHECK45-64-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-64: omp.body.continue: @@ -763,7 +763,7 @@ // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK45-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -922,7 +922,7 @@ // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK45-32-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK45-32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 @@ -1048,7 +1048,7 @@ // CHECK45-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK45-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK45-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -1191,9 +1191,9 @@ // CHECK45-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] // CHECK45-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK45-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK45-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] +// CHECK45-32-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP18]] // CHECK45-32-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32: omp.body.continue: @@ -1341,7 +1341,7 @@ // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK45-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK45-32-EX-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -1500,7 +1500,7 @@ // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK45-32-EX-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK45-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 @@ -1626,7 +1626,7 @@ // CHECK45-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK45-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK45-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK45-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK45-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -1769,9 +1769,9 @@ // CHECK45-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-EX-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] // CHECK45-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK45-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK45-32-EX-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] +// CHECK45-32-EX-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP18]] // CHECK45-32-EX-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK45-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45-32-EX: omp.body.continue: @@ -1920,7 +1920,7 @@ // CHECK-64-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-64-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -2080,7 +2080,7 @@ // CHECK-64-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK-64-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK-64-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 @@ -2207,7 +2207,7 @@ // CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK-64-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -2351,10 +2351,10 @@ // CHECK-64-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] // CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-64-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK-64-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-64-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]] +// CHECK-64-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM11]] // CHECK-64-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-64: omp.body.continue: @@ -2502,7 +2502,7 @@ // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK-32-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -2661,7 +2661,7 @@ // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK-32-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK-32-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK-32-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 @@ -2787,7 +2787,7 @@ // CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK-32-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -2930,9 +2930,9 @@ // CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] // CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK-32-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] +// CHECK-32-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP18]] // CHECK-32-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32: omp.body.continue: @@ -3080,7 +3080,7 @@ // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK-32-EX-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK-32-EX-NEXT: store i32 [[TMP18]], ptr [[L_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] @@ -3239,7 +3239,7 @@ // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP16]] // CHECK-32-EX-NEXT: [[CONV:%.*]] = sext i16 [[TMP18]] to i32 // CHECK-32-EX-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV]], 1 @@ -3365,7 +3365,7 @@ // CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], 1 // CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] @@ -3508,9 +3508,9 @@ // CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-EX-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP16]] // CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK-32-EX-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK-32-EX-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP18]] +// CHECK-32-EX-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP18]] // CHECK-32-EX-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX11]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK-32-EX: omp.body.continue: Index: clang/test/OpenMP/ordered_codegen.cpp =================================================================== --- clang/test/OpenMP/ordered_codegen.cpp +++ clang/test/OpenMP/ordered_codegen.cpp @@ -581,7 +581,7 @@ // CHECK1-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK1-NEXT: call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -654,7 +654,7 @@ // CHECK1-NEXT: store i32 [[ADD34]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 -// CHECK1-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]] +// CHECK1-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM35]] // CHECK1-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] @@ -701,7 +701,7 @@ // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret void // @@ -714,7 +714,7 @@ // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret void // @@ -1201,7 +1201,7 @@ // CHECK1-IRBUILDER-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK1-IRBUILDER-NEXT: [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK1-IRBUILDER-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK1-IRBUILDER-NEXT: call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]] // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] @@ -1278,7 +1278,7 @@ // CHECK1-IRBUILDER-NEXT: store i32 [[ADD35]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-IRBUILDER-NEXT: [[TMP31:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-IRBUILDER-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]] +// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM36]] // CHECK1-IRBUILDER-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK1-IRBUILDER-NEXT: call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]] // CHECK1-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]] @@ -1329,7 +1329,7 @@ // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK1-IRBUILDER-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK1-IRBUILDER-NEXT: ret void // @@ -1342,7 +1342,7 @@ // CHECK1-IRBUILDER-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK1-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK1-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK1-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK1-IRBUILDER-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK1-IRBUILDER-NEXT: ret void // @@ -1806,7 +1806,7 @@ // CHECK3-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK3-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK3-NEXT: call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1879,7 +1879,7 @@ // CHECK3-NEXT: store i32 [[ADD34]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: [[IDXPROM35:%.*]] = sext i32 [[TMP32]] to i64 -// CHECK3-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM35]] +// CHECK3-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM35]] // CHECK3-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX36]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE37:%.*]] @@ -1926,7 +1926,7 @@ // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret void // @@ -1939,7 +1939,7 @@ // CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK3-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret void // @@ -2426,7 +2426,7 @@ // CHECK3-IRBUILDER-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK3-IRBUILDER-NEXT: [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK3-IRBUILDER-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK3-IRBUILDER-NEXT: call void @__captured_stmt(ptr [[I5]]), !llvm.access.group [[ACC_GRP3]] // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY_ORDERED_AFTER:%.*]] @@ -2503,7 +2503,7 @@ // CHECK3-IRBUILDER-NEXT: store i32 [[ADD35]], ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-IRBUILDER-NEXT: [[TMP31:%.*]] = load i32, ptr [[I28]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-IRBUILDER-NEXT: [[IDXPROM36:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM36]] +// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX37:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM36]] // CHECK3-IRBUILDER-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX37]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-IRBUILDER-NEXT: call void @__captured_stmt.1(ptr [[I28]]), !llvm.access.group [[ACC_GRP7]] // CHECK3-IRBUILDER-NEXT: br label [[OMP_INNER_FOR_BODY33_ORDERED_AFTER:%.*]] @@ -2554,7 +2554,7 @@ // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK3-IRBUILDER-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK3-IRBUILDER-NEXT: ret void // @@ -2567,7 +2567,7 @@ // CHECK3-IRBUILDER-NEXT: [[TMP0:%.*]] = load ptr, ptr [[I_ADDR]], align 8 // CHECK3-IRBUILDER-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4 // CHECK3-IRBUILDER-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK3-IRBUILDER-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK3-IRBUILDER-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX]], align 4 // CHECK3-IRBUILDER-NEXT: ret void // @@ -2868,11 +2868,11 @@ // CHECK5-NEXT: store i32 [[ADD8]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2934,11 +2934,11 @@ // CHECK5-NEXT: store i32 [[ADD37]], ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[TMP30:%.*]] = load i32, ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[IDXPROM38:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM38]] +// CHECK5-NEXT: [[ARRAYIDX39:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM38]] // CHECK5-NEXT: store float 0.000000e+00, ptr [[ARRAYIDX39]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[TMP31:%.*]] = load i32, ptr [[I31]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[IDXPROM40:%.*]] = sext i32 [[TMP31]] to i64 -// CHECK5-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], ptr @f, i64 0, i64 [[IDXPROM40]] +// CHECK5-NEXT: [[ARRAYIDX41:%.*]] = getelementptr inbounds [10 x float], ptr @f, inrange i64 0, i64 [[IDXPROM40]] // CHECK5-NEXT: store float 1.000000e+00, ptr [[ARRAYIDX41]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE42:%.*]] // CHECK5: omp.body.continue42: Index: clang/test/OpenMP/parallel_copyin_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_copyin_codegen.cpp +++ clang/test/OpenMP/parallel_copyin_codegen.cpp @@ -413,11 +413,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5t_var, i64 4, ptr @_ZZ4mainE5t_var.cache.) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3vec, i64 8, ptr @_ZZ4mainE3vec.cache.) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE3var, i64 4, ptr @_ZZ4mainE3var.cache.) // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ4mainE5s_arr, i64 8, ptr @_ZZ4mainE5s_arr.cache.) -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP14]], inrange i64 0, i64 0 // CHECK1-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) // CHECK1-NEXT: ret void // @@ -690,11 +690,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5t_var, i64 4, ptr @_ZZ5tmainIiET_vE5t_var.cache.) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 128 // CHECK1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3vec, i64 8, ptr @_ZZ5tmainIiET_vE3vec.cache.) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP12]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 128 // CHECK1-NEXT: [[TMP13:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE3var, i64 4, ptr @_ZZ5tmainIiET_vE3var.cache.) // CHECK1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP1]], ptr @_ZZ5tmainIiET_vE5s_arr, i64 8, ptr @_ZZ5tmainIiET_vE5s_arr.cache.) -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP14]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP14]], inrange i64 0, i64 0 // CHECK1-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP13]]) // CHECK1-NEXT: ret void // @@ -1160,11 +1160,11 @@ // CHECK11-NEXT: [[TMP15:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5t_var) // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3vec) -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], i64 0, i64 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], inrange i64 0, i64 0 // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE3var) // CHECK11-NEXT: [[TMP19:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZZ4mainE5s_arr) -// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP19]], i64 0, i64 0 +// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP19]], inrange i64 0, i64 0 // CHECK11-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]]) // CHECK11-NEXT: ret void // @@ -1392,11 +1392,11 @@ // CHECK11-NEXT: [[TMP15:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5t_var) // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP15]], align 128 // CHECK11-NEXT: [[TMP17:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3vec) -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], i64 0, i64 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP17]], inrange i64 0, i64 0 // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 128 // CHECK11-NEXT: [[TMP18:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE3var) // CHECK11-NEXT: [[TMP19:%.*]] = call align 128 ptr @llvm.threadlocal.address.p0(ptr align 128 @_ZZ5tmainIiET_vE5s_arr) -// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP19]], i64 0, i64 0 +// CHECK11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP19]], inrange i64 0, i64 0 // CHECK11-NEXT: [[CALL4:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], ptr noundef nonnull align 4 dereferenceable(4) [[TMP18]]) // CHECK11-NEXT: ret void // Index: clang/test/OpenMP/parallel_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_firstprivate_codegen.cpp +++ clang/test/OpenMP/parallel_firstprivate_codegen.cpp @@ -374,9 +374,9 @@ // CHECK1-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK1-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] @@ -599,7 +599,7 @@ // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP7]], 1 // CHECK1-NEXT: store i32 [[DIV]], ptr [[TMP6]], align 4 // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i32 0, i32 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], inrange i32 0, i32 2 // CHECK1-NEXT: store i32 1111, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret void // @@ -763,9 +763,9 @@ // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], inrange i32 0, i32 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false) // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 @@ -1556,9 +1556,9 @@ // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] @@ -1781,7 +1781,7 @@ // CHECK9-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP7]], 1 // CHECK9-NEXT: store i32 [[DIV]], ptr [[TMP6]], align 4 // CHECK9-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP4]], align 8 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[TMP8]], inrange i64 0, i64 2 // CHECK9-NEXT: store i32 1111, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: ret void // @@ -1945,9 +1945,9 @@ // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], inrange i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false) // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 Index: clang/test/OpenMP/parallel_for_scan_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_for_scan_codegen.cpp +++ clang/test/OpenMP/parallel_for_scan_codegen.cpp @@ -59,7 +59,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -152,7 +152,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) @@ -189,7 +189,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -290,7 +290,7 @@ // CHECK: [[BASE_IDX_SUB_1:%.+]] = sub nuw i64 [[BASE_IDX]], 1 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX_SUB_1]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) Index: clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp +++ clang/test/OpenMP/parallel_for_simd_scan_codegen.cpp @@ -52,7 +52,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -145,7 +145,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) @@ -182,7 +182,7 @@ // CHECK: [[BASE_IDX:%.+]] = zext i32 [[BASE_IDX_I]] to i64 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX]], [[NUM_ELEMS:%.+]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF:%.+]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_BUF_IDX]], ptr {{.*}}[[A_PRIV]], i64 [[BYTES]], i1 false) @@ -283,7 +283,7 @@ // CHECK: [[BASE_IDX_SUB_1:%.+]] = sub nuw i64 [[BASE_IDX]], 1 // CHECK: [[IDX:%.+]] = mul nsw i64 [[BASE_IDX_SUB_1]], [[NUM_ELEMS]] // CHECK: [[A_BUF_IDX:%.+]] = getelementptr inbounds float, ptr [[A_BUF]], i64 [[IDX]] - // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], i64 0, i64 0 + // CHECK: [[A_PRIV:%.+]] = getelementptr inbounds [10 x float], ptr [[A_PRIV_ADDR:%.+]], inrange i64 0, i64 0 // CHECK: [[BYTES:%.+]] = mul nuw i64 [[NUM_ELEMS:%.+]], 4 // CHECK: call void @llvm.memcpy.p0.p0.i64(ptr {{.*}}[[A_PRIV]], ptr {{.*}}[[A_BUF_IDX]], i64 [[BYTES]], i1 false) Index: clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp +++ clang/test/OpenMP/parallel_master_taskloop_firstprivate_codegen.cpp @@ -482,9 +482,9 @@ // CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14 // CHECK-NEXT: store i32 [[TMP34]], i32* [[I_I]], align 4, !noalias !14 // CHECK-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP27]], align 4 -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], inrange i64 0, i64 0 // CHECK-NEXT: store i32 [[TMP35]], i32* [[ARRAYIDX_I]], align 4 -// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[ARRAYIDX6_I]] to i8* // CHECK-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP26]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP36]], i8* align 8 [[TMP37]], i64 8, i1 false) @@ -908,9 +908,9 @@ // CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !28 // CHECK-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !28 // CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP26]], align 128 -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], inrange i64 0, i64 0 // CHECK-NEXT: store i32 [[TMP34]], i32* [[ARRAYIDX_I]], align 4 -// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5_I]] to i8* // CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false) @@ -1600,9 +1600,9 @@ // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY0: for.body: // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) @@ -1701,9 +1701,9 @@ // SIMD-ONLY0-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY0: for.body: // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // SIMD-ONLY0-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) @@ -1929,9 +1929,9 @@ // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY1: for.body: // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = bitcast %struct.S* [[ARRAYIDX1]] to i8* // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = bitcast %struct.S* [[VAR]] to i8* // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP3]], i8* align 8 [[TMP4]], i64 8, i1 false) @@ -2030,9 +2030,9 @@ // SIMD-ONLY1-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] // SIMD-ONLY1: for.body: // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[T_VAR]], align 128 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP2]], i32* [[ARRAYIDX]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: [[TMP3:%.*]] = bitcast %struct.S.0* [[ARRAYIDX1]] to i8* // SIMD-ONLY1-NEXT: [[TMP4:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP3]], i8* align 4 [[TMP4]], i64 4, i1 false) Index: clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp +++ clang/test/OpenMP/parallel_master_taskloop_reduction_codegen.cpp @@ -84,9 +84,9 @@ // CHECK-DAG: store ptr @[[RED_COMB1:.+]], ptr [[TMP25]], // CHECK-DAG: [[TMP26:%.*]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK-DAG: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 4, i1 false) -// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C:%.+]], i64 0, i64 0 +// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C:%.+]], inrange i64 0, i64 0 // CHECK-DAG: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, % -// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 [[LB_ADD_LEN]] +// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 [[LB_ADD_LEN]] // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], // CHECK-DAG: [[TMP28]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_4:%.+]], i32 0, i32 0 // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], Index: clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/parallel_master_taskloop_simd_firstprivate_codegen.cpp @@ -482,9 +482,9 @@ // CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] // CHECK-NEXT: store i32 [[TMP34]], i32* [[I_I]], align 4, !noalias !14, !llvm.access.group [[ACC_GRP15]] // CHECK-NEXT: [[TMP35:%.*]] = load i32, i32* [[TMP27]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP29]], inrange i64 0, i64 0 // CHECK-NEXT: store i32 [[TMP35]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX6_I:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP28]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S* [[ARRAYIDX6_I]] to i8* // CHECK-NEXT: [[TMP37:%.*]] = bitcast %struct.S* [[TMP26]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP36]], i8* align 8 [[TMP37]], i64 8, i1 false), !llvm.access.group [[ACC_GRP15]] @@ -908,9 +908,9 @@ // CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_IV_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] // CHECK-NEXT: store i32 [[TMP33]], i32* [[I_I]], align 4, !noalias !32, !llvm.access.group [[ACC_GRP33]] // CHECK-NEXT: [[TMP34:%.*]] = load i32, i32* [[TMP26]], align 128, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP27]], inrange i64 0, i64 0 // CHECK-NEXT: store i32 [[TMP34]], i32* [[ARRAYIDX_I]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX5_I:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP28]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP35:%.*]] = bitcast %struct.S.0* [[ARRAYIDX5_I]] to i8* // CHECK-NEXT: [[TMP36:%.*]] = bitcast %struct.S.0* [[TMP29]] to i8* // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP35]], i8* align 4 [[TMP36]], i64 4, i1 false), !llvm.access.group [[ACC_GRP33]] @@ -1614,9 +1614,9 @@ // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[VAR]] to i8* // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP6]], i8* align 8 [[TMP7]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] @@ -1732,9 +1732,9 @@ // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // SIMD-ONLY0-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] @@ -1977,9 +1977,9 @@ // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: [[TMP6:%.*]] = bitcast %struct.S* [[ARRAYIDX2]] to i8* // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = bitcast %struct.S* [[VAR]] to i8* // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 16 [[TMP6]], i8* align 8 [[TMP7]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] @@ -2095,9 +2095,9 @@ // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // SIMD-ONLY1-NEXT: [[TMP5:%.*]] = load i32, i32* [[T_VAR]], align 128, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[VEC]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: store i32 [[TMP5]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], i64 0, i64 0 +// SIMD-ONLY1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[S_ARR]], inrange i64 0, i64 0 // SIMD-ONLY1-NEXT: [[TMP6:%.*]] = bitcast %struct.S.0* [[ARRAYIDX2]] to i8* // SIMD-ONLY1-NEXT: [[TMP7:%.*]] = bitcast %struct.S.0* [[VAR]] to i8* // SIMD-ONLY1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 [[TMP7]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] Index: clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/parallel_master_taskloop_simd_lastprivate_codegen.cpp @@ -1791,9 +1791,9 @@ // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 0 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 0 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[ARRAYIDX6]], ptr align 8 [[VAR1]], i64 8, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: store i32 33, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] @@ -1947,9 +1947,9 @@ // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR1]], align 128, !llvm.access.group [[ACC_GRP6]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp +++ clang/test/OpenMP/parallel_master_taskloop_simd_reduction_codegen.cpp @@ -84,9 +84,9 @@ // CHECK-DAG: store ptr @[[RED_COMB1:.+]], ptr [[TMP25]], // CHECK-DAG: [[TMP26:%.*]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK-DAG: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 4, i1 false) -// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C:%.+]], i64 0, i64 0 +// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C:%.+]], inrange i64 0, i64 0 // CHECK-DAG: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, % -// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 [[LB_ADD_LEN]] +// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 [[LB_ADD_LEN]] // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], // CHECK-DAG: [[TMP28]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_4:%.+]], i32 0, i32 0 // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], Index: clang/test/OpenMP/parallel_private_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_private_codegen.cpp +++ clang/test/OpenMP/parallel_private_codegen.cpp @@ -266,9 +266,9 @@ // CHECK1: arrayctor.cont: // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 3, ptr [[SIVAR]], align 4 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] @@ -475,9 +475,9 @@ // CHECK1: arrayctor.cont: // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 Index: clang/test/OpenMP/parallel_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/parallel_reduction_codegen.cpp +++ clang/test/OpenMP/parallel_reduction_codegen.cpp @@ -621,9 +621,9 @@ // CHECK1-NEXT: store float 0x47EFFFFFE0000000, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load float, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP7]], align 8 @@ -860,9 +860,9 @@ // CHECK1: while.body: // CHECK1-NEXT: [[TMP6:%.*]] = load float, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP2]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: br label [[WHILE_COND]], !llvm.loop [[LOOP5:![0-9]+]] // @@ -1294,9 +1294,9 @@ // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR14]]) // CHECK1-NEXT: store i32 2147483647, ptr [[T_VAR15]], align 128 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR2]], align 128 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP2]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 128 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x ptr], ptr [[DOTOMP_REDUCTION_RED_LIST]], i64 0, i64 0 // CHECK1-NEXT: store ptr [[T_VAR2]], ptr [[TMP7]], align 8 Index: clang/test/OpenMP/reduction_implicit_map.cpp =================================================================== --- clang/test/OpenMP/reduction_implicit_map.cpp +++ clang/test/OpenMP/reduction_implicit_map.cpp @@ -309,7 +309,7 @@ // CHECK1-NEXT: [[ARRAYCTOR_DONE:%.*]] = icmp eq ptr [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]] // CHECK1-NEXT: br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]] // CHECK1: arrayctor.cont: -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %class.S2], ptr [[O]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %class.S2], ptr [[O]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 // CHECK1-NEXT: store ptr [[O]], ptr [[TMP0]], align 8 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x ptr], ptr [[DOTOFFLOAD_PTRS]], i32 0, i32 0 @@ -428,7 +428,7 @@ // CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8 // CHECK1-NEXT: store ptr [[O]], ptr [[O_ADDR]], align 8 // CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[O_ADDR]], align 8 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %class.S2], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x %class.S2], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @_ZN2S2C1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[O1]]) // CHECK1-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK1-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 @@ -529,14 +529,14 @@ // CHECK1-NEXT: store i64 9, ptr [[DOTOMP_UB]], align 8 // CHECK1-NEXT: store i64 1, ptr [[DOTOMP_STRIDE]], align 8 // CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK1-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x [10 x double]], ptr [[ARRAYIDX]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY]], i64 2 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY]], inrange i64 2 // CHECK1-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX1]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY2]], i64 1 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], inrange i64 0, i64 1 // CHECK1-NEXT: [[ARRAYDECAY5:%.*]] = getelementptr inbounds [10 x [10 x double]], ptr [[ARRAYIDX4]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY5]], i64 5 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY5]], inrange i64 5 // CHECK1-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX6]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY7]], i64 1 // CHECK1-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[ARRAYIDX8]] to i64 @@ -566,14 +566,14 @@ // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr double, ptr [[VLA]], i64 [[TMP12]] // CHECK1-NEXT: [[DOTRD_INPUT_GEP_:%.*]] = getelementptr inbounds [1 x %struct.kmp_taskred_input_t], ptr [[DOTRD_INPUT_]], i64 0, i64 0 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASKRED_INPUT_T:%.*]], ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK1-NEXT: [[ARRAYDECAY10:%.*]] = getelementptr inbounds [10 x [10 x double]], ptr [[ARRAYIDX9]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY10]], i64 2 +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY10]], inrange i64 2 // CHECK1-NEXT: [[ARRAYDECAY12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY12]], i64 1 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x double]]], ptr [[TMP0]], inrange i64 0, i64 1 // CHECK1-NEXT: [[ARRAYDECAY15:%.*]] = getelementptr inbounds [10 x [10 x double]], ptr [[ARRAYIDX14]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY15]], i64 5 +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYDECAY15]], inrange i64 5 // CHECK1-NEXT: [[ARRAYDECAY17:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX16]], i64 0, i64 0 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, ptr [[ARRAYDECAY17]], i64 1 // CHECK1-NEXT: store ptr [[VLA]], ptr [[TMP14]], align 8 @@ -1014,7 +1014,7 @@ // CHECK2-NEXT: [[TMP86:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP86]], ptr [[SIZE_CASTED21]], align 4 // CHECK2-NEXT: [[TMP87:%.*]] = load i32, ptr [[SIZE_CASTED21]], align 4 -// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 0 +// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 0 // CHECK2-NEXT: [[TMP88:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS23]], i32 0, i32 0 // CHECK2-NEXT: store i32 [[TMP87]], ptr [[TMP88]], align 4 // CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS24]], i32 0, i32 0 @@ -1065,7 +1065,7 @@ // CHECK2-NEXT: [[TMP111:%.*]] = load i32, ptr [[SIZE_ADDR]], align 4 // CHECK2-NEXT: store i32 [[TMP111]], ptr [[SIZE_CASTED29]], align 4 // CHECK2-NEXT: [[TMP112:%.*]] = load i32, ptr [[SIZE_CASTED29]], align 4 -// CHECK2-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 3 +// CHECK2-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 3 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_BASEPTRS31]], i32 0, i32 0 // CHECK2-NEXT: store i32 [[TMP112]], ptr [[TMP113]], align 4 // CHECK2-NEXT: [[TMP114:%.*]] = getelementptr inbounds [2 x ptr], ptr [[DOTOFFLOAD_PTRS32]], i32 0, i32 0 @@ -1885,8 +1885,8 @@ // CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 0 -// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 1 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 0 +// CHECK2-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 1 // CHECK2-NEXT: [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x i32], ptr [[A2]], i32 0, i32 0 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[ARRAY_BEGIN]], i32 2 // CHECK2-NEXT: [[OMP_ARRAYINIT_ISEMPTY:%.*]] = icmp eq ptr [[ARRAY_BEGIN]], [[TMP1]] @@ -2026,7 +2026,7 @@ // CHECK2-NEXT: store i32 [[SIZE]], ptr [[SIZE_ADDR]], align 4 // CHECK2-NEXT: store ptr [[A]], ptr [[A_ADDR]], align 4 // CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 3 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 3 // CHECK2-NEXT: store i32 0, ptr [[A1]], align 4 // CHECK2-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[TMP0]] to i64 // CHECK2-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[ARRAYIDX]] to i64 Index: clang/test/OpenMP/sections_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/sections_firstprivate_codegen.cpp +++ clang/test/OpenMP/sections_firstprivate_codegen.cpp @@ -325,9 +325,9 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 31, ptr [[SIVAR]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -570,11 +570,11 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case7: -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: Index: clang/test/OpenMP/sections_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/sections_lastprivate_codegen.cpp +++ clang/test/OpenMP/sections_lastprivate_codegen.cpp @@ -318,9 +318,9 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: store i32 31, ptr [[SIVAR5]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -611,11 +611,11 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case5: -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK1-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -996,9 +996,9 @@ // CHECK5-NEXT: ] // CHECK5: .omp.sections.case: // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIfEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: store i32 31, ptr [[SIVAR5]], align 4 // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -1307,11 +1307,11 @@ // CHECK5-NEXT: ] // CHECK5: .omp.sections.case: // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK5-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.case5: -// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK5-NEXT: [[CALL:%.*]] = call noundef nonnull align 4 dereferenceable(4) ptr @_ZN1SIiEaSERKS0_(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYIDX6]], ptr noundef nonnull align 4 dereferenceable(4) [[VAR4]]) // CHECK5-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK5: .omp.sections.exit: Index: clang/test/OpenMP/sections_private_codegen.cpp =================================================================== --- clang/test/OpenMP/sections_private_codegen.cpp +++ clang/test/OpenMP/sections_private_codegen.cpp @@ -218,9 +218,9 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 2, ptr [[SIVAR]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] @@ -408,11 +408,11 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case1: -// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: Index: clang/test/OpenMP/sections_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/sections_reduction_codegen.cpp +++ clang/test/OpenMP/sections_reduction_codegen.cpp @@ -315,15 +315,15 @@ // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP15:%.*]] = load float, ptr [[T_VAR2]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fptosi float [[TMP15]] to i32 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: [[TMP16:%.*]] = load float, ptr [[T_VAR15]], align 4 // CHECK1-NEXT: [[CONV7:%.*]] = fptosi float [[TMP16]] to i32 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 1 // CHECK1-NEXT: store i32 [[CONV7]], ptr [[ARRAYIDX8]], align 4 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP5]], inrange i64 0, i64 1 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR14]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: @@ -702,11 +702,11 @@ // CHECK1-NEXT: ] // CHECK1: .omp.sections.case: // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP4]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.case6: -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[TMP5]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR3]], i64 4, i1 false) // CHECK1-NEXT: br label [[DOTOMP_SECTIONS_EXIT]] // CHECK1: .omp.sections.exit: Index: clang/test/OpenMP/single_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/single_firstprivate_codegen.cpp +++ clang/test/OpenMP/single_firstprivate_codegen.cpp @@ -287,9 +287,9 @@ // CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4 // CHECK1-NEXT: store i32 [[TMP5]], ptr [[SIVAR]], align 4 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 41, ptr [[SIVAR]], align 4 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR2]] @@ -500,9 +500,9 @@ // CHECK1-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR5]], ptr nonnull align 4 dereferenceable(4) [[TMP3]], ptr [[AGG_TMP6]]) // CHECK1-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP6]]) #[[ATTR2]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR5]]) #[[ATTR2]] // CHECK1-NEXT: [[ARRAY_BEGIN8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 0 Index: clang/test/OpenMP/single_private_codegen.cpp =================================================================== --- clang/test/OpenMP/single_private_codegen.cpp +++ clang/test/OpenMP/single_private_codegen.cpp @@ -181,9 +181,9 @@ // CHECK1: arrayctor.cont: // CHECK1-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: store i32 303, ptr [[SIVAR]], align 4 // CHECK1-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] @@ -335,9 +335,9 @@ // CHECK1: arrayctor.cont: // CHECK1-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK1-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR5]] // CHECK1-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 Index: clang/test/OpenMP/target_codegen.cpp =================================================================== --- clang/test/OpenMP/target_codegen.cpp +++ clang/test/OpenMP/target_codegen.cpp @@ -497,9 +497,9 @@ // Use captures. // CHECK-64-DAG: load i32, i32* [[REF_A]] // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] -// CHECK-DAG: getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 +// CHECK-DAG: getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], inrange i[[SZ]] 0, i[[SZ]] 2 // CHECK-DAG: getelementptr inbounds float, float* [[REF_BN]], i[[SZ]] 3 -// CHECK-DAG: getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], i[[SZ]] 0, i[[SZ]] 1 +// CHECK-DAG: getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], inrange i[[SZ]] 0, i[[SZ]] 1 // CHECK-DAG: getelementptr inbounds double, double* [[REF_CN]], i[[SZ]] %{{.+}} // CHECK-DAG: getelementptr inbounds [[TT]], [[TT]]* [[REF_D]], i32 0, i32 0 @@ -840,7 +840,7 @@ // CHECK-DAG: load i16, i16* [[REF_AA]] // CHECK-DAG: load i8, i8* [[REF_AAA]] // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] -// CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 +// CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], inrange i[[SZ]] 0, i[[SZ]] 2 // CHECK: define internal void [[HVT5]] // Create local storage for each capture. @@ -858,7 +858,7 @@ // CHECK-64-DAG: load i32, i32* [[REF_A]] // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] // CHECK-DAG: load i16, i16* [[REF_AA]] -// CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 +// CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], inrange i[[SZ]] 0, i[[SZ]] 2 // OMP50: define internal void @__omp_offloading_{{.+}}_{{.+}}bar{{.+}}_l{{[0-9]+}}(i[[SZ]] noundef %{{.+}}) Index: clang/test/OpenMP/target_data_use_device_addr_codegen.cpp =================================================================== --- clang/test/OpenMP/target_data_use_device_addr_codegen.cpp +++ clang/test/OpenMP/target_data_use_device_addr_codegen.cpp @@ -61,7 +61,7 @@ // CHECK-NEXT: [[ARR_IDX1:%.+]] = getelementptr inbounds float, ptr [[P6]], i64 0 // CHECK: [[P7:%.+]] = load ptr, ptr [[REF_ADDR]], // CHECK-NEXT: [[REF:%.+]] = load ptr, ptr [[REF_ADDR]], -// CHECK-NEXT: [[ARR_IDX2:%.+]] = getelementptr inbounds [4 x float], ptr [[ARR_ADDR]], i64 0, i64 0 +// CHECK-NEXT: [[ARR_IDX2:%.+]] = getelementptr inbounds [4 x float], ptr [[ARR_ADDR]], inrange i64 0, i64 0 // CHECK: [[P10:%.+]] = mul nuw i64 {{.+}}, 4 // CHECK-NEXT: [[ARR_IDX5:%.+]] = getelementptr inbounds float, ptr [[VLA_ADDR]], i64 0 // CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[SIZES]], ptr align 8 [[SIZES1]], i64 48, i1 false) @@ -114,7 +114,7 @@ // CHECK: [[REF:%.+]] = load float, ptr [[REF_ADDR]], // CHECK: [[INC:%.+]] = fadd float [[REF]], 1.000000e+00 // CHECK: store float [[INC]], ptr [[REF_ADDR]], -// CHECK: [[ARR0_ADDR:%.+]] = getelementptr inbounds [4 x float], ptr [[ARR_REF]], i64 0, i64 0 +// CHECK: [[ARR0_ADDR:%.+]] = getelementptr inbounds [4 x float], ptr [[ARR_REF]], inrange i64 0, i64 0 // CHECK: [[ARR0:%.+]] = load float, ptr [[ARR0_ADDR]], // CHECK: [[INC:%.+]] = fadd float [[ARR0]], 1.000000e+00 // CHECK: store float [[INC]], ptr [[ARR0_ADDR]], @@ -141,7 +141,7 @@ // CHECK: [[ARR_IDX5:%.+]] = getelementptr inbounds i32, ptr {{.+}}, i64 0 // CHECK: [[ARR_ADDR:%.+]] = getelementptr inbounds %struct.S, ptr [[THIS]], i32 0, i32 3 -// CHECK: [[ARR_IDX6:%.+]] = getelementptr inbounds [4 x i32], ptr [[ARR_ADDR]], i64 0, i64 0 +// CHECK: [[ARR_IDX6:%.+]] = getelementptr inbounds [4 x i32], ptr [[ARR_ADDR]], inrange i64 0, i64 0 // CHECK: [[A_ADDR2:%.+]] = getelementptr inbounds %struct.S, ptr [[THIS]], i32 0, i32 0 // CHECK: [[P4:%.+]] = mul nuw i64 [[CONV:%.+]], 4 // CHECK: [[ARR_END:%.+]] = getelementptr i32, ptr [[ARR_IDX6]], i32 1 @@ -206,7 +206,7 @@ // CHECK: [[INC:%.+]] = add nsw i32 [[VAL]], 1 // CHECK: store i32 [[INC]], ptr [[REF_PTR]], // CHECK: [[ARR_ADDR:%.+]] = load ptr, ptr [[ARR_REF]], -// CHECK: [[ARR0_ADDR:%.+]] = getelementptr inbounds [4 x i32], ptr [[ARR_ADDR]], i64 0, i64 0 +// CHECK: [[ARR0_ADDR:%.+]] = getelementptr inbounds [4 x i32], ptr [[ARR_ADDR]], inrange i64 0, i64 0 // CHECK: [[VAL:%.+]] = load i32, ptr [[ARR0_ADDR]], // CHECK: [[INC:%.+]] = add nsw i32 [[VAL]], 1 // CHECK: store i32 [[INC]], ptr [[ARR0_ADDR]], Index: clang/test/OpenMP/target_defaultmap_codegen_01.cpp =================================================================== --- clang/test/OpenMP/target_defaultmap_codegen_01.cpp +++ clang/test/OpenMP/target_defaultmap_codegen_01.cpp @@ -285,7 +285,7 @@ // CK5: [[ADDR:%.+]] = alloca ptr, // CK5: store ptr [[ARG]], ptr [[ADDR]], // CK5: [[REF:%.+]] = load ptr, ptr [[ADDR]], -// CK5: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 +// CK5: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], inrange i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK6 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK6 @@ -338,7 +338,7 @@ // CK6: [[ADDR:%.+]] = alloca ptr, // CK6: store ptr [[ARG]], ptr [[ADDR]], // CK6: [[REF:%.+]] = load ptr, ptr [[ADDR]], -// CK6: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 +// CK6: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], inrange i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK7 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK7 @@ -392,7 +392,7 @@ // CK7: [[ADDR:%.+]] = alloca ptr, // CK7: store ptr [[ARG]], ptr [[ADDR]], // CK7: [[REF:%.+]] = load ptr, ptr [[ADDR]], -// CK7: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 +// CK7: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], inrange i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// // RUN: %clang_cc1 -no-enable-noundef-analysis -DCK8 -verify -fopenmp -fopenmp-version=50 -fopenmp-targets=powerpc64le-ibm-linux-gnu -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix CK8 @@ -445,7 +445,7 @@ // CK8: [[ADDR:%.+]] = alloca ptr, // CK8: store ptr [[ARG]], ptr [[ADDR]], // CK8: [[REF:%.+]] = load ptr, ptr [[ADDR]], -// CK8: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 +// CK8: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], inrange i{{64|32}} 0, i{{64|32}} 0 #endif ///==========================================================================/// Index: clang/test/OpenMP/target_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_firstprivate_codegen.cpp +++ clang/test/OpenMP/target_firstprivate_codegen.cpp @@ -6460,12 +6460,12 @@ // CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // CHECK0-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // CHECK0-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i64 0, i64 2 // CHECK0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // CHECK0-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 // CHECK0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 +// CHECK0-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i64 0, i64 1 +// CHECK0-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i64 0, i64 2 // CHECK0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // CHECK0-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK0-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] @@ -6901,7 +6901,7 @@ // CHECK0-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK0-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK0-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], inrange i64 0, i64 2 // CHECK0-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK0-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK0-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 @@ -6924,7 +6924,7 @@ // CHECK0-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 // CHECK0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK0-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 +// CHECK0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i64 0, i64 2 // CHECK0-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK0-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK0-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -7320,12 +7320,12 @@ // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // CHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // CHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i64 0, i64 2 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 // CHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i64 0, i64 2 // CHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // CHECK1-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] @@ -7761,7 +7761,7 @@ // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK1-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 @@ -7784,7 +7784,7 @@ // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -8176,12 +8176,12 @@ // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // CHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // CHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i32 0, i32 2 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 // CHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i32 0, i32 1 +// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i32 0, i32 2 // CHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // CHECK2-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] @@ -8612,7 +8612,7 @@ // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 // CHECK2-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 @@ -8634,7 +8634,7 @@ // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -9026,12 +9026,12 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // CHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i32 0, i32 2 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 // CHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i32 0, i32 2 // CHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // CHECK3-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] @@ -9462,7 +9462,7 @@ // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 // CHECK3-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 @@ -9484,7 +9484,7 @@ // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -9540,12 +9540,12 @@ // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY0-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 // SIMD-ONLY0-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i64 0, i64 1 +// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i64 0, i64 2 // SIMD-ONLY0-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] // SIMD-ONLY0-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] @@ -9672,7 +9672,7 @@ // SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY0-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY0-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY0-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY0-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -9691,7 +9691,7 @@ // SIMD-ONLY0-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY0-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY0-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY0-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY0-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -9741,12 +9741,12 @@ // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY01-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY01-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY01-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 // SIMD-ONLY01-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY01-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i64 0, i64 1 +// SIMD-ONLY01-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i64 0, i64 2 // SIMD-ONLY01-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY01-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] // SIMD-ONLY01-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] @@ -9873,7 +9873,7 @@ // SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY01-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY01-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY01-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY01-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY01-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -9892,7 +9892,7 @@ // SIMD-ONLY01-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY01-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY01-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY01-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY01-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY01-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY01-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -9940,12 +9940,12 @@ // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY02-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY02-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY02-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 // SIMD-ONLY02-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i32 0, i32 1 +// SIMD-ONLY02-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i32 0, i32 2 // SIMD-ONLY02-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY02-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] // SIMD-ONLY02-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] @@ -10071,7 +10071,7 @@ // SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY02-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY02-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY02-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY02-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY02-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -10090,7 +10090,7 @@ // SIMD-ONLY02-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY02-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY02-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY02-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY02-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY02-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY02-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -10138,12 +10138,12 @@ // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY03-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY03-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY03-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 // SIMD-ONLY03-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i32 0, i32 1 +// SIMD-ONLY03-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i32 0, i32 2 // SIMD-ONLY03-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY03-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] // SIMD-ONLY03-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] @@ -10269,7 +10269,7 @@ // SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY03-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY03-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY03-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY03-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY03-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -10288,7 +10288,7 @@ // SIMD-ONLY03-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY03-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY03-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY03-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY03-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY03-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY03-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -10378,12 +10378,12 @@ // TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // TCHECK-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // TCHECK-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i64 0, i64 2 // TCHECK-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // TCHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 // TCHECK-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 +// TCHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i64 0, i64 1 +// TCHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i64 0, i64 2 // TCHECK-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // TCHECK-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] // TCHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] @@ -10444,7 +10444,7 @@ // TCHECK-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // TCHECK-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // TCHECK-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], inrange i64 0, i64 2 // TCHECK-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 // TCHECK-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 @@ -10518,7 +10518,7 @@ // TCHECK-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 // TCHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // TCHECK-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 +// TCHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i64 0, i64 2 // TCHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // TCHECK-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -10607,12 +10607,12 @@ // TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // TCHECK1-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // TCHECK1-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i64 0, i64 2 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i64 0, i64 2 // TCHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // TCHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i64 3 // TCHECK1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i64 0, i64 1 -// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i64 0, i64 2 +// TCHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i64 0, i64 1 +// TCHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i64 0, i64 2 // TCHECK1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // TCHECK1-NEXT: [[TMP24:%.*]] = mul nsw i64 1, [[TMP5]] // TCHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i64 [[TMP24]] @@ -10673,7 +10673,7 @@ // TCHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // TCHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // TCHECK1-NEXT: store i8 [[CONV5]], i8* [[CONV1]], align 1 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], i64 0, i64 2 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B2]], inrange i64 0, i64 2 // TCHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP5]], 1 // TCHECK1-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4 @@ -10747,7 +10747,7 @@ // TCHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 4 // TCHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // TCHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 -// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i64 0, i64 2 +// TCHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i64 0, i64 2 // TCHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // TCHECK1-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -10834,12 +10834,12 @@ // TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // TCHECK2-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // TCHECK2-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i32 0, i32 2 // TCHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // TCHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 // TCHECK2-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 +// TCHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i32 0, i32 1 +// TCHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i32 0, i32 2 // TCHECK2-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // TCHECK2-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] // TCHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] @@ -10899,7 +10899,7 @@ // TCHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // TCHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 // TCHECK2-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // TCHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 // TCHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 @@ -10971,7 +10971,7 @@ // TCHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // TCHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // TCHECK2-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// TCHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // TCHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // TCHECK2-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -11058,12 +11058,12 @@ // TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], 1 // TCHECK3-NEXT: [[CONV11:%.*]] = trunc i32 [[ADD]] to i16 // TCHECK3-NEXT: store i16 [[CONV11]], i16* [[CONV]], align 2 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], i32 0, i32 2 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B5]], inrange i32 0, i32 2 // TCHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // TCHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA6]], i32 3 // TCHECK3-NEXT: store float 1.000000e+00, float* [[ARRAYIDX12]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], i32 0, i32 1 -// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], i32 0, i32 2 +// TCHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C7]], inrange i32 0, i32 1 +// TCHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX13]], inrange i32 0, i32 2 // TCHECK3-NEXT: store double 1.000000e+00, double* [[ARRAYIDX14]], align 8 // TCHECK3-NEXT: [[TMP24:%.*]] = mul nsw i32 1, [[TMP5]] // TCHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[VLA8]], i32 [[TMP24]] @@ -11123,7 +11123,7 @@ // TCHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 // TCHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i8 // TCHECK3-NEXT: store i8 [[CONV4]], i8* [[CONV]], align 1 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // TCHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP5]], 1 // TCHECK3-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 @@ -11195,7 +11195,7 @@ // TCHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 // TCHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1 // TCHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 -// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], i32 0, i32 2 +// TCHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B1]], inrange i32 0, i32 2 // TCHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // TCHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP4]], 1 // TCHECK3-NEXT: store i32 [[ADD2]], i32* [[ARRAYIDX]], align 4 @@ -11244,12 +11244,12 @@ // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY1-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 // SIMD-ONLY1-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i64 0, i64 1 +// SIMD-ONLY1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i64 0, i64 2 // SIMD-ONLY1-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY1-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] // SIMD-ONLY1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] @@ -11376,7 +11376,7 @@ // SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY1-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY1-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY1-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -11395,7 +11395,7 @@ // SIMD-ONLY1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY1-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY1-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -11445,12 +11445,12 @@ // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY11-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY11-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY11-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 // SIMD-ONLY11-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 -// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i64 0, i64 1 +// SIMD-ONLY11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i64 0, i64 2 // SIMD-ONLY11-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY11-NEXT: [[TMP9:%.*]] = mul nsw i64 1, [[TMP4]] // SIMD-ONLY11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP9]] @@ -11577,7 +11577,7 @@ // SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY11-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY11-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY11-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -11596,7 +11596,7 @@ // SIMD-ONLY11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 +// SIMD-ONLY11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i64 0, i64 2 // SIMD-ONLY11-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY11-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -11644,12 +11644,12 @@ // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY12-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY12-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY12-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 // SIMD-ONLY12-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i32 0, i32 1 +// SIMD-ONLY12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i32 0, i32 2 // SIMD-ONLY12-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY12-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] // SIMD-ONLY12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] @@ -11775,7 +11775,7 @@ // SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY12-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY12-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY12-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY12-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -11794,7 +11794,7 @@ // SIMD-ONLY12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY12-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY12-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY12-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY12-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 @@ -11842,12 +11842,12 @@ // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 // SIMD-ONLY13-NEXT: store i16 [[CONV2]], i16* [[AA]], align 2 -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY13-NEXT: store float 1.000000e+00, float* [[ARRAYIDX]], align 4 // SIMD-ONLY13-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 // SIMD-ONLY13-NEXT: store float 1.000000e+00, float* [[ARRAYIDX3]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 -// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i32 0, i32 1 +// SIMD-ONLY13-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX4]], inrange i32 0, i32 2 // SIMD-ONLY13-NEXT: store double 1.000000e+00, double* [[ARRAYIDX5]], align 8 // SIMD-ONLY13-NEXT: [[TMP7:%.*]] = mul nsw i32 1, [[TMP2]] // SIMD-ONLY13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP7]] @@ -11973,7 +11973,7 @@ // SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // SIMD-ONLY13-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i8 // SIMD-ONLY13-NEXT: store i8 [[CONV2]], i8* [[AAA]], align 1 -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY13-NEXT: [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY13-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1 // SIMD-ONLY13-NEXT: store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4 @@ -11992,7 +11992,7 @@ // SIMD-ONLY13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 // SIMD-ONLY13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 // SIMD-ONLY13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 -// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 +// SIMD-ONLY13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], inrange i32 0, i32 2 // SIMD-ONLY13-NEXT: [[TMP1:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 // SIMD-ONLY13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP1]], 1 // SIMD-ONLY13-NEXT: store i32 [[ADD1]], i32* [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/target_has_device_addr_codegen.cpp =================================================================== --- clang/test/OpenMP/target_has_device_addr_codegen.cpp +++ clang/test/OpenMP/target_has_device_addr_codegen.cpp @@ -612,7 +612,7 @@ // CHECK-NEXT: [[AA_ADDR:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: ret void // @@ -627,7 +627,7 @@ // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[RAA_ADDR]], align 8 // CHECK-NEXT: store ptr [[TMP0]], ptr [[TMP]], align 8 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP1]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP2]], ptr [[A]], align 4 // CHECK-NEXT: ret void @@ -640,7 +640,7 @@ // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[H]], ptr [[H_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], i64 0, i64 1 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], inrange i64 0, i64 1 // CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S6:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A1]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -654,7 +654,7 @@ // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[DA]], ptr [[DA_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DA_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x i32], ptr [[TMP0]], i64 0, i64 1 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [5 x i32], ptr [[TMP0]], inrange i64 0, i64 1 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 // CHECK-NEXT: ret void @@ -1106,7 +1106,7 @@ // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 // CHECK-NEXT: ret void @@ -1119,7 +1119,7 @@ // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[H]], ptr [[H_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S6:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A1]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -1160,7 +1160,7 @@ // CHECK-NEXT: [[A:%.*]] = alloca ptr, align 8 // CHECK-NEXT: store ptr [[AA]], ptr [[AA_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[AA_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 // CHECK-NEXT: store ptr [[TMP1]], ptr [[A]], align 8 // CHECK-NEXT: ret void @@ -1173,7 +1173,7 @@ // CHECK-NEXT: [[A:%.*]] = alloca i32, align 4 // CHECK-NEXT: store ptr [[H]], ptr [[H_ADDR]], align 8 // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[H_ADDR]], align 8 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[TMP0]], inrange i64 0, i64 0 // CHECK-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S6:%.*]], ptr [[ARRAYIDX]], i32 0, i32 0 // CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A1]], align 4 // CHECK-NEXT: store i32 [[TMP1]], ptr [[A]], align 4 @@ -1438,20 +1438,20 @@ // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP4]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[AA]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[AA]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: store i32 1, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[RAA]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP6]], ptr [[_TMP2]], align 8 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load ptr, ptr [[RAA]], align 8 // SIMD-ONLY0-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP8]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP8]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP9]], ptr [[A]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], i64 0, i64 1 +// SIMD-ONLY0-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], inrange i64 0, i64 1 // SIMD-ONLY0-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S6:%.*]], ptr [[ARRAYIDX5]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load i32, ptr [[A6]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP10]], ptr [[A4]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x i32], ptr [[DA]], i64 0, i64 1 +// SIMD-ONLY0-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [5 x i32], ptr [[DA]], inrange i64 0, i64 1 // SIMD-ONLY0-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX8]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP11]], ptr [[A7]], align 4 // SIMD-ONLY0-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARGC_ADDR]], align 4 @@ -1494,10 +1494,10 @@ // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds i32, ptr [[TMP5]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP4]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[AA]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[AA]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP6]], ptr [[A]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S6:%.*]], ptr [[ARRAYIDX3]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[A4]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP7]], ptr [[A2]], align 4 @@ -1536,10 +1536,10 @@ // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP4]], align 8 // SIMD-ONLY0-NEXT: [[INCDEC_PTR1:%.*]] = getelementptr inbounds ptr, ptr [[TMP5]], i32 1 // SIMD-ONLY0-NEXT: store ptr [[INCDEC_PTR1]], ptr [[TMP4]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[AA]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x ptr], ptr [[AA]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8 // SIMD-ONLY0-NEXT: store ptr [[TMP6]], ptr [[A]], align 8 -// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x %struct.S6], ptr [[H]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S6:%.*]], ptr [[ARRAYIDX3]], i32 0, i32 0 // SIMD-ONLY0-NEXT: [[TMP7:%.*]] = load i32, ptr [[A4]], align 4 // SIMD-ONLY0-NEXT: store i32 [[TMP7]], ptr [[A2]], align 4 Index: clang/test/OpenMP/target_has_device_addr_codegen_01.cpp =================================================================== --- clang/test/OpenMP/target_has_device_addr_codegen_01.cpp +++ clang/test/OpenMP/target_has_device_addr_codegen_01.cpp @@ -279,7 +279,7 @@ // CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP8]], align 4 // CHECK-NEXT: [[INC4:%.*]] = fadd float [[TMP9]], 1.000000e+00 // CHECK-NEXT: store float [[INC4]], ptr [[TMP8]], align 4 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP2]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x float], ptr [[TMP2]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK-NEXT: [[INC5:%.*]] = fadd float [[TMP10]], 1.000000e+00 // CHECK-NEXT: store float [[INC5]], ptr [[ARRAYIDX]], align 4 @@ -328,7 +328,7 @@ // CHECK-NEXT: [[INC2:%.*]] = add nsw i32 [[TMP5]], 1 // CHECK-NEXT: store i32 [[INC2]], ptr [[TMP4]], align 4 // CHECK-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[TMP0]], i32 0, i32 3 -// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 0 +// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], inrange i64 0, i64 0 // CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 8 // CHECK-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK-NEXT: store i32 [[INC3]], ptr [[ARRAYIDX]], align 8 @@ -381,7 +381,7 @@ // SIMD-ONLY0-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP8]], align 4 // SIMD-ONLY0-NEXT: [[INC2:%.*]] = fadd float [[TMP9]], 1.000000e+00 // SIMD-ONLY0-NEXT: store float [[INC2]], ptr [[TMP8]], align 4 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x float], ptr [[ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x float], ptr [[ARR]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // SIMD-ONLY0-NEXT: [[INC3:%.*]] = fadd float [[TMP10]], 1.000000e+00 // SIMD-ONLY0-NEXT: store float [[INC3]], ptr [[ARRAYIDX]], align 4 @@ -429,7 +429,7 @@ // SIMD-ONLY0-NEXT: [[INC3:%.*]] = add nsw i32 [[TMP4]], 1 // SIMD-ONLY0-NEXT: store i32 [[INC3]], ptr [[TMP3]], align 4 // SIMD-ONLY0-NEXT: [[ARR:%.*]] = getelementptr inbounds [[STRUCT_S]], ptr [[THIS1]], i32 0, i32 3 -// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], i64 0, i64 0 +// SIMD-ONLY0-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [4 x i32], ptr [[ARR]], inrange i64 0, i64 0 // SIMD-ONLY0-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 8 // SIMD-ONLY0-NEXT: [[INC4:%.*]] = add nsw i32 [[TMP5]], 1 // SIMD-ONLY0-NEXT: store i32 [[INC4]], ptr [[ARRAYIDX]], align 8 Index: clang/test/OpenMP/target_map_codegen_08.cpp =================================================================== --- clang/test/OpenMP/target_map_codegen_08.cpp +++ clang/test/OpenMP/target_map_codegen_08.cpp @@ -67,6 +67,6 @@ // CK9: [[ADDR:%.+]] = alloca ptr, // CK9: store ptr [[ARG]], ptr [[ADDR]], // CK9: [[REF:%.+]] = load ptr, ptr [[ADDR]], -// CK9: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], i{{64|32}} 0, i{{64|32}} 0 +// CK9: {{.+}} = getelementptr inbounds [2 x double], ptr [[REF]], inrange i{{64|32}} 0, i{{64|32}} 0 #endif // CK9 #endif Index: clang/test/OpenMP/target_map_codegen_18.inc =================================================================== --- clang/test/OpenMP/target_map_codegen_18.inc +++ clang/test/OpenMP/target_map_codegen_18.inc @@ -1463,7 +1463,7 @@ // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to [12 x [13 x double]]** // CK19-DAG: store [11 x [12 x [13 x double]]]* [[VAR0:%.+]], [11 x [12 x [13 x double]]]** [[CBP0]] // CK19-DAG: store [12 x [13 x double]]* [[SEC0:%.+]], [12 x [13 x double]]** [[CP0]] - // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], i[[Z]] 0, i[[Z]] 0 + // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], inrange i[[Z]] 0, i[[Z]] 0 // CK19-USE: call void [[CALL33:@.+]]([11 x [12 x [13 x double]]]* {{[^,]+}}) // CK19-NOUSE: call void [[CALL33:@.+]]() @@ -1489,7 +1489,7 @@ // CK19-DAG: [[CP0:%.+]] = bitcast i8** [[P0]] to [12 x [13 x double]]** // CK19-DAG: store [11 x [12 x [13 x double]]]* [[VAR0:%.+]], [11 x [12 x [13 x double]]]** [[CBP0]] // CK19-DAG: store [12 x [13 x double]]* [[SEC0:%.+]], [12 x [13 x double]]** [[CP0]] - // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], i[[Z]] 0, i[[Z]] 0 + // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], inrange i[[Z]] 0, i[[Z]] 0 // CK19-USE: call void [[CALL34:@.+]]([11 x [12 x [13 x double]]]* {{[^,]+}}) // CK19-NOUSE: call void [[CALL34:@.+]]() @@ -1521,8 +1521,8 @@ // CK19-DAG: store [11 x [12 x [13 x double]]]* [[VAR0:%.+]], [11 x [12 x [13 x double]]]** [[CBP0]] // CK19-DAG: store [13 x double]* [[SEC0:%.+]], [13 x double]** [[CP0]] // CK19-DAG: store i64 [[CSVAL0:%[^,]+]], i64* [[S0]] - // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[12 x [13 x double]]* [[SEC00:%[^,]+]], i[[Z]] 0, i[[Z]] 0 - // CK19-DAG: [[SEC00]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], i[[Z]] 0, i[[Z]] 1 + // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[12 x [13 x double]]* [[SEC00:%[^,]+]], inrange i[[Z]] 0, i[[Z]] 0 + // CK19-DAG: [[SEC00]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], inrange i[[Z]] 0, i[[Z]] 1 // CK19-DAG: [[CSVAL0]] = {{mul nuw i64 %[^,]+, 104|sext i32 .+ to i64}} // CK19-USE: call void [[CALL35:@.+]]([11 x [12 x [13 x double]]]* {{[^,]+}}) @@ -1651,7 +1651,7 @@ // CK19-USE-DAG: store [13 x double]* [[VAR2:%.+]], [13 x double]** [[CBP2]] // CK19-USE-DAG: store [13 x double]* [[SEC2:%.+]], [13 x double]** [[CP2]] // CK19-USE-DAG: store i64 [[CSVAL2:%[^,]+]], i64* [[S2]] - // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[VAR2]], i[[Z]] [[SEC22:%[^,]+]] + // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[VAR2]], inrange i[[Z]] [[SEC22:%[^,]+]] // CK19-USE-DAG: [[SEC22]] = mul nsw i[[Z]] 0, %{{[^,]+}} // CK19-USE-DAG: [[CSVAL2]] = {{mul nuw i64 %[^,]+, 104|sext i32 .+ to i64}} @@ -1663,7 +1663,7 @@ // CK19-NOUSE-DAG: store [13 x double]* [[VAR0:%.+]], [13 x double]** [[CBP0]] // CK19-NOUSE-DAG: store [13 x double]* [[SEC0:%.+]], [13 x double]** [[CP0]] // CK19-NOUSE-DAG: store i64 [[CSVAL0:%[^,]+]], i64* [[S0]] - // CK19-NOUSE-DAG: [[SEC0]] = getelementptr {{.+}}[13 x double]* [[VAR0]], i[[Z]] [[SEC00:%[^,]+]] + // CK19-NOUSE-DAG: [[SEC0]] = getelementptr {{.+}}[13 x double]* [[VAR0]], inrange i[[Z]] [[SEC00:%[^,]+]] // CK19-NOUSE-DAG: [[SEC00]] = mul nsw i[[Z]] 0, %{{[^,]+}} // CK19-NOUSE-DAG: [[CSVAL0]] = {{mul nuw i64 %[^,]+, 104|sext i32 .+ to i64}} @@ -1710,7 +1710,7 @@ // CK19-USE-DAG: store [13 x double]* [[VAR2:%.+]], [13 x double]** [[CBP2]] // CK19-USE-DAG: store [13 x double]* [[SEC2:%.+]], [13 x double]** [[CP2]] // CK19-USE-DAG: store i64 [[CSVAL2:%[^,]+]], i64* [[S2]] - // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[VAR2]], i[[Z]] [[SEC22:%[^,]+]] + // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[VAR2]], inrange i[[Z]] [[SEC22:%[^,]+]] // CK19-USE-DAG: [[SEC22]] = mul nsw i[[Z]] 0, %{{[^,]+}} // CK19-USE-DAG: [[CSVAL2]] = {{mul nuw i64 %[^,]+, 104|sext i32 .+ to i64}} @@ -1722,7 +1722,7 @@ // CK19-NOUSE-DAG: store [13 x double]* [[VAR0:%.+]], [13 x double]** [[CBP0]] // CK19-NOUSE-DAG: store [13 x double]* [[SEC0:%.+]], [13 x double]** [[CP0]] // CK19-NOUSE-DAG: store i64 [[CSVAL0:%[^,]+]], i64* [[S0]] - // CK19-NOUSE-DAG: [[SEC0]] = getelementptr {{.+}}[13 x double]* [[VAR0]], i[[Z]] [[SEC00:%[^,]+]] + // CK19-NOUSE-DAG: [[SEC0]] = getelementptr {{.+}}[13 x double]* [[VAR0]], inrange i[[Z]] [[SEC00:%[^,]+]] // CK19-NOUSE-DAG: [[SEC00]] = mul nsw i[[Z]] 0, %{{[^,]+}} // CK19-NOUSE-DAG: [[CSVAL0]] = {{mul nuw i64 %[^,]+, 104|sext i32 .+ to i64}} @@ -1769,8 +1769,8 @@ // CK19-USE-DAG: store [13 x double]* [[VAR2:%.+]], [13 x double]** [[CBP2]] // CK19-USE-DAG: store [13 x double]* [[SEC2:%.+]], [13 x double]** [[CP2]] // CK19-USE-DAG: store i64 [[CSVAL2:%[^,]+]], i64* [[S2]] - // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[SEC22:%[^,]+]], i[[Z]] 0 - // CK19-USE-DAG: [[SEC22]] = getelementptr {{.+}}[13 x double]* [[VAR2]], i[[Z]] [[SEC222:%[^,]+]] + // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[SEC22:%[^,]+]], inrange i[[Z]] 0 + // CK19-USE-DAG: [[SEC22]] = getelementptr {{.+}}[13 x double]* [[VAR2]], inrange i[[Z]] [[SEC222:%[^,]+]] // CK19-USE-DAG: [[SEC222]] = mul nsw i[[Z]] 1, %{{[^,]+}} // CK19-NOUSE-DAG: [[SIZES]] = getelementptr inbounds {{.+}}[[S:%[^,]+]] @@ -1782,8 +1782,8 @@ // CK19-NOUSE-DAG: store [13 x double]* [[VAR0:%.+]], [13 x double]** [[CBP0]] // CK19-NOUSE-DAG: store [13 x double]* [[SEC0:%.+]], [13 x double]** [[CP0]] // CK19-NOUSE-DAG: store i64 [[CSVAL0:%[^,]+]], i64* [[S0]] - // CK19-NOUSE-DAG: [[SEC0]] = getelementptr {{.+}}[13 x double]* [[SEC00:%[^,]+]], i[[Z]] 0 - // CK19-NOUSE-DAG: [[SEC00]] = getelementptr {{.+}}[13 x double]* [[VAR0]], i[[Z]] [[SEC000:%[^,]+]] + // CK19-NOUSE-DAG: [[SEC0]] = getelementptr {{.+}}[13 x double]* [[SEC00:%[^,]+]], inrange i[[Z]] 0 + // CK19-NOUSE-DAG: [[SEC00]] = getelementptr {{.+}}[13 x double]* [[VAR0]], inrange i[[Z]] [[SEC000:%[^,]+]] // CK19-NOUSE-DAG: [[SEC000]] = mul nsw i[[Z]] 1, %{{[^,]+}} // CK19-USE: call void [[CALL40:@.+]](i[[Z]] 11, i[[Z]] %{{[^,]+}}, [13 x double]* %{{[^,]+}}) @@ -1824,8 +1824,8 @@ // CK19-USE-DAG: [[CP2:%.+]] = bitcast i8** [[P2]] to [13 x double]** // CK19-USE-DAG: store [13 x double]* [[VAR2:%.+]], [13 x double]** [[CBP2]] // CK19-USE-DAG: store [13 x double]* [[SEC2:%.+]], [13 x double]** [[CP2]] - // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[SEC22:%[^,]+]], i[[Z]] 0 - // CK19-USE-DAG: [[SEC22]] = getelementptr {{.+}}[13 x double]* [[VAR2]], i[[Z]] [[SEC222:%[^,]+]] + // CK19-USE-DAG: [[SEC2]] = getelementptr {{.+}}[13 x double]* [[SEC22:%[^,]+]], inrange i[[Z]] 0 + // CK19-USE-DAG: [[SEC22]] = getelementptr {{.+}}[13 x double]* [[VAR2]], inrange i[[Z]] [[SEC222:%[^,]+]] // CK19-USE-DAG: [[SEC222]] = mul nsw i[[Z]] 0, %{{[^,]+}} // CK19-USE-DAG: [[BP2:%.+]] = getelementptr inbounds {{.+}}[[BP]], i{{.+}} 0, i{{.+}} 2 @@ -1920,8 +1920,8 @@ // CK19-DAG: store [11 x [12 x [13 x double]]]* [[VAR0:%.+]], [11 x [12 x [13 x double]]]** [[CBP0]] // CK19-DAG: store [13 x double]* [[SEC0:%.+]], [13 x double]** [[CP0]] // CK19-DAG: store i64 [[CSVAL0:%[^,]+]], i64* [[S0]] - // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[12 x [13 x double]]* [[SEC00:%[^,]+]], i[[Z]] 0, i[[Z]] 0 - // CK19-DAG: [[SEC00]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], i[[Z]] 0, i[[Z]] 1 + // CK19-DAG: [[SEC0]] = getelementptr {{.+}}[12 x [13 x double]]* [[SEC00:%[^,]+]], inrange i[[Z]] 0, i[[Z]] 0 + // CK19-DAG: [[SEC00]] = getelementptr {{.+}}[11 x [12 x [13 x double]]]* [[VAR0]], inrange i[[Z]] 0, i[[Z]] 1 // CK19-DAG: [[CSVAL0]] = {{mul nuw i64 %[^,]+, 104|sext i32 .+ to i64}} // CK19-USE: call void [[CALL43:@.+]]([11 x [12 x [13 x double]]]* {{[^,]+}}) Index: clang/test/OpenMP/target_map_member_expr_array_section_codegen.cpp =================================================================== --- clang/test/OpenMP/target_map_member_expr_array_section_codegen.cpp +++ clang/test/OpenMP/target_map_member_expr_array_section_codegen.cpp @@ -28,12 +28,12 @@ // CHECK: getelementptr inbounds // CHECK: [[S_ADDR:%.+]] = getelementptr inbounds %struct.maptest, ptr [[THIS:%.+]], i32 0, i32 0 // CHECK: [[S_DATA_ADDR:%.+]] = getelementptr inbounds %struct.S, ptr [[S_ADDR]], i32 0, i32 0 - // CHECK: [[S_DATA_0_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], i64 0, i64 0 + // CHECK: [[S_DATA_0_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], inrange i64 0, i64 0 // SZ = &this->s.data[6]-&this->s.data[0] // CHECK: [[S_ADDR:%.+]] = getelementptr inbounds %struct.maptest, ptr [[THIS]], i32 0, i32 0 // CHECK: [[S_DATA_ADDR:%.+]] = getelementptr inbounds %struct.S, ptr [[S_ADDR]], i32 0, i32 0 - // CHECK: [[S_DATA_5_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], i64 0, i64 5 + // CHECK: [[S_DATA_5_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], inrange i64 0, i64 5 // CHECK: [[S_DATA_6_ADDR:%.+]] = getelementptr float, ptr [[S_DATA_5_ADDR]], i32 1 // CHECK: [[END_BC:%.+]] = ptrtoint ptr [[S_DATA_6_ADDR]] to i64 // CHECK: [[BEG_BC:%.+]] = ptrtoint ptr [[S_DATA_0_ADDR]] to i64 @@ -64,12 +64,12 @@ // CHECK: [[SIZE:%.+]] = alloca [2 x i64], // CHECK: [[S_ADDR:%.+]] = getelementptr inbounds %struct.maptest, ptr [[THIS:%.+]], i32 0, i32 0 // CHECK: [[S_DATA_ADDR:%.+]] = getelementptr inbounds %struct.S, ptr [[S_ADDR]], i32 0, i32 0 - // CHECK: [[S_DATA_0_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], i64 0, i64 0 + // CHECK: [[S_DATA_0_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], inrange i64 0, i64 0 // SZ = &this->s.data[6]-&this->s.data[0] // CHECK: [[S_ADDR:%.+]] = getelementptr inbounds %struct.maptest, ptr [[THIS]], i32 0, i32 0 // CHECK: [[S_DATA_ADDR:%.+]] = getelementptr inbounds %struct.S, ptr [[S_ADDR]], i32 0, i32 0 - // CHECK: [[S_DATA_5_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], i64 0, i64 5 + // CHECK: [[S_DATA_5_ADDR:%.+]] = getelementptr inbounds [6 x float], ptr [[S_DATA_ADDR]], inrange i64 0, i64 5 // CHECK: [[S_DATA_6_ADDR:%.+]] = getelementptr float, ptr [[S_DATA_5_ADDR]], i32 1 // CHECK: [[END_BC:%.+]] = ptrtoint ptr [[S_DATA_6_ADDR]] to i64 // CHECK: [[BEG_BC:%.+]] = ptrtoint ptr [[S_DATA_0_ADDR]] to i64 Index: clang/test/OpenMP/target_parallel_codegen.cpp =================================================================== --- clang/test/OpenMP/target_parallel_codegen.cpp +++ clang/test/OpenMP/target_parallel_codegen.cpp @@ -830,7 +830,7 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -842,8 +842,8 @@ // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK1-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK1-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -1329,7 +1329,7 @@ // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK1-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -1380,7 +1380,7 @@ // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -1933,7 +1933,7 @@ // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -1945,8 +1945,8 @@ // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK3-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -2432,7 +2432,7 @@ // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK3-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -2483,7 +2483,7 @@ // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -2667,7 +2667,7 @@ // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -2679,8 +2679,8 @@ // CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK9-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK9-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK9-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK9-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -2760,7 +2760,7 @@ // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK9-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -2874,7 +2874,7 @@ // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -3051,7 +3051,7 @@ // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -3063,8 +3063,8 @@ // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK11-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK11-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -3144,7 +3144,7 @@ // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK11-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -3258,7 +3258,7 @@ // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK11-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/target_parallel_debug_codegen.cpp =================================================================== --- clang/test/OpenMP/target_parallel_debug_codegen.cpp +++ clang/test/OpenMP/target_parallel_debug_codegen.cpp @@ -162,45 +162,45 @@ // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[B3]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[B3]], ptr align 4 [[TMP4]], i64 400, i1 false), !dbg [[DBG70]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META72:![0-9]+]], metadata !DIExpression()), !dbg [[DBG75:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG76:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG76]] -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG76]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 1, !dbg [[DBG76:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG76]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], inrange i64 0, i64 1, !dbg [[DBG76]] // CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[DBG75]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78:![0-9]+]] // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG78]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG80:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 1, !dbg [[DBG81:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG81]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], inrange i64 0, i64 1, !dbg [[DBG81:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], inrange i64 0, i64 1, !dbg [[DBG81]] // CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[DBG80]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META82:![0-9]+]], metadata !DIExpression()), !dbg [[DBG83:![0-9]+]] // CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG83]] // CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG84:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG85:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], inrange i64 0, i64 0, !dbg [[DBG85:![0-9]+]] // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG86:![0-9]+]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG85]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG85]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], inrange i64 0, i64 [[IDXPROM]], !dbg [[DBG85]] // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG87:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG88:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG88]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG88:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], inrange i64 0, i64 0, !dbg [[DBG88]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG89:![0-9]+]] // CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG88]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG88]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 [[IDXPROM12]], !dbg [[DBG88]] // CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG90:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG91:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG91]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG91:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], inrange i64 0, i64 0, !dbg [[DBG91]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG92:![0-9]+]] // CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG91]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG91]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], inrange i64 0, i64 [[IDXPROM16]], !dbg [[DBG91]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG91]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG93:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], inrange i64 0, i64 0, !dbg [[DBG93:![0-9]+]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG94:![0-9]+]] // CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG93]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG93]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], inrange i64 0, i64 [[IDXPROM19]], !dbg [[DBG93]] // CHECK1-NEXT: store i32 [[TMP11]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG95:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], i64 0, i64 0, !dbg [[DBG96:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B3]], inrange i64 0, i64 0, !dbg [[DBG96:![0-9]+]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG97:![0-9]+]] // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG96]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG96]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], inrange i64 0, i64 [[IDXPROM22]], !dbg [[DBG96]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG96]] // CHECK1-NEXT: [[TMP15:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG98:![0-9]+]] // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP15]] to i1, !dbg [[DBG98]] @@ -373,40 +373,40 @@ // CHECK1-NEXT: store ptr [[TMP7]], ptr [[_TMP2]], align 8, !dbg [[DBG156]] // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[_TMP2]], align 8, !dbg [[DBG156]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG159:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG160:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG160]] -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG160]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 1, !dbg [[DBG160:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG160]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX3]], inrange i64 0, i64 1, !dbg [[DBG160]] // CHECK1-NEXT: store ptr [[ARRAYIDX4]], ptr [[F]], align 8, !dbg [[DBG159]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG162]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META163:![0-9]+]], metadata !DIExpression()), !dbg [[DBG164:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG165:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX5]], i64 0, i64 1, !dbg [[DBG165]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], inrange i64 0, i64 1, !dbg [[DBG165:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX5]], inrange i64 0, i64 1, !dbg [[DBG165]] // CHECK1-NEXT: store ptr [[ARRAYIDX6]], ptr [[H]], align 8, !dbg [[DBG164]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG167:![0-9]+]] // CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG167]] // CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG168:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG169:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], inrange i64 0, i64 0, !dbg [[DBG169:![0-9]+]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG170:![0-9]+]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG169]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 [[IDXPROM]], !dbg [[DBG169]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], inrange i64 0, i64 [[IDXPROM]], !dbg [[DBG169]] // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX8]], align 4, !dbg [[DBG171:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG172:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX9]], i64 0, i64 0, !dbg [[DBG172]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG172:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX9]], inrange i64 0, i64 0, !dbg [[DBG172]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG173:![0-9]+]] // CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG172]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM11]], !dbg [[DBG172]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], inrange i64 0, i64 [[IDXPROM11]], !dbg [[DBG172]] // CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG174:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG175:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG175]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG175:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], inrange i64 0, i64 0, !dbg [[DBG175]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG176:![0-9]+]] // CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG175]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG175]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], inrange i64 0, i64 [[IDXPROM15]], !dbg [[DBG175]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG175]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG177:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], inrange i64 0, i64 0, !dbg [[DBG177:![0-9]+]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG178:![0-9]+]] // CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG177]] -// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG177]] +// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], inrange i64 0, i64 [[IDXPROM18]], !dbg [[DBG177]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX19]], align 4, !dbg [[DBG179:![0-9]+]] // CHECK1-NEXT: [[TMP14:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG180:![0-9]+]] // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1, !dbg [[DBG180]] @@ -583,45 +583,45 @@ // CHECK1-NEXT: store ptr [[TMP10]], ptr [[_TMP3]], align 8, !dbg [[DBG231]] // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP3]], align 8, !dbg [[DBG231]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG234:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG235:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG235]] -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], i64 0, i64 1, !dbg [[DBG235]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 1, !dbg [[DBG235:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG235]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX4]], inrange i64 0, i64 1, !dbg [[DBG235]] // CHECK1-NEXT: store ptr [[ARRAYIDX5]], ptr [[F]], align 8, !dbg [[DBG234]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META236:![0-9]+]], metadata !DIExpression()), !dbg [[DBG237:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG237]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG239:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG240:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG240]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 1, !dbg [[DBG240:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], inrange i64 0, i64 1, !dbg [[DBG240]] // CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[H]], align 8, !dbg [[DBG239]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG242]] // CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG243:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG244:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 0, !dbg [[DBG244:![0-9]+]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG245:![0-9]+]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG244]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 [[IDXPROM]], !dbg [[DBG244]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], inrange i64 0, i64 [[IDXPROM]], !dbg [[DBG244]] // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX9]], align 4, !dbg [[DBG246:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG247:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], i64 0, i64 0, !dbg [[DBG247]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG247:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX10]], inrange i64 0, i64 0, !dbg [[DBG247]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG248:![0-9]+]] // CHECK1-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG247]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM12]], !dbg [[DBG247]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 [[IDXPROM12]], !dbg [[DBG247]] // CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX13]], align 4, !dbg [[DBG249:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG250:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], i64 0, i64 0, !dbg [[DBG250]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG250:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX14]], inrange i64 0, i64 0, !dbg [[DBG250]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG251:![0-9]+]] // CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG250]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG250]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX15]], inrange i64 0, i64 [[IDXPROM16]], !dbg [[DBG250]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX17]], align 4, !dbg [[DBG250]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG252:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 0, !dbg [[DBG252:![0-9]+]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG253:![0-9]+]] // CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG252]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG252]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], inrange i64 0, i64 [[IDXPROM19]], !dbg [[DBG252]] // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX20]], align 4, !dbg [[DBG254:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG255:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 0, !dbg [[DBG255:![0-9]+]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG256:![0-9]+]] // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP17]] to i64, !dbg [[DBG255]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG255]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], inrange i64 0, i64 [[IDXPROM22]], !dbg [[DBG255]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX23]], align 4, !dbg [[DBG255]] // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP18]], 0, !dbg [[DBG255]] // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG257:![0-9]+]] Index: clang/test/OpenMP/target_parallel_for_codegen.cpp =================================================================== --- clang/test/OpenMP/target_parallel_for_codegen.cpp +++ clang/test/OpenMP/target_parallel_for_codegen.cpp @@ -1311,7 +1311,7 @@ // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -1323,8 +1323,8 @@ // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 @@ -1956,7 +1956,7 @@ // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -2981,7 +2981,7 @@ // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -2993,8 +2993,8 @@ // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4 -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 @@ -3626,7 +3626,7 @@ // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -4096,7 +4096,7 @@ // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -4108,8 +4108,8 @@ // CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4 -// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 // CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 @@ -4398,7 +4398,7 @@ // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -4861,7 +4861,7 @@ // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -4873,8 +4873,8 @@ // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4 -// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 @@ -5163,7 +5163,7 @@ // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -6187,7 +6187,7 @@ // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -6199,8 +6199,8 @@ // CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4 -// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 // CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 @@ -6832,7 +6832,7 @@ // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -7857,7 +7857,7 @@ // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -7869,8 +7869,8 @@ // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4 -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8 @@ -8502,7 +8502,7 @@ // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/target_parallel_for_debug_codegen.cpp =================================================================== --- clang/test/OpenMP/target_parallel_for_debug_codegen.cpp +++ clang/test/OpenMP/target_parallel_for_debug_codegen.cpp @@ -210,45 +210,45 @@ // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG75]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG75]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META76:![0-9]+]], metadata !DIExpression()), !dbg [[DBG79:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG80:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG80]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG80]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 1, !dbg [[DBG80:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG80]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], inrange i64 0, i64 1, !dbg [[DBG80]] // CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG79]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82:![0-9]+]] // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG82]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META83:![0-9]+]], metadata !DIExpression()), !dbg [[DBG84:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 1, !dbg [[DBG85:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG85]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], inrange i64 0, i64 1, !dbg [[DBG85:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], inrange i64 0, i64 1, !dbg [[DBG85]] // CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG84]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META86:![0-9]+]], metadata !DIExpression()), !dbg [[DBG87:![0-9]+]] // CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG87]] // CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG88:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG89:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], inrange i64 0, i64 0, !dbg [[DBG89:![0-9]+]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG90:![0-9]+]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG89]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG89]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 [[IDXPROM]], !dbg [[DBG89]] // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG91:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG92:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG92]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG92:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], inrange i64 0, i64 0, !dbg [[DBG92]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG93:![0-9]+]] // CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG92]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG92]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], inrange i64 0, i64 [[IDXPROM15]], !dbg [[DBG92]] // CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG94:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG95:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG95]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG95:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], inrange i64 0, i64 0, !dbg [[DBG95]] // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG96:![0-9]+]] // CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG95]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG95]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], inrange i64 0, i64 [[IDXPROM19]], !dbg [[DBG95]] // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG95]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG97:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], inrange i64 0, i64 0, !dbg [[DBG97:![0-9]+]] // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG98:![0-9]+]] // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG97]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG97]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], inrange i64 0, i64 [[IDXPROM22]], !dbg [[DBG97]] // CHECK1-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG99:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], i64 0, i64 0, !dbg [[DBG100:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[B4]], inrange i64 0, i64 0, !dbg [[DBG100:![0-9]+]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG101:![0-9]+]] // CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG100]] -// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG100]] +// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], inrange i64 0, i64 [[IDXPROM25]], !dbg [[DBG100]] // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG100]] // CHECK1-NEXT: [[TMP25:%.*]] = load i8, ptr [[TMP7]], align 1, !dbg [[DBG102:![0-9]+]] // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP25]] to i1, !dbg [[DBG102]] @@ -499,40 +499,40 @@ // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG174]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG174]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META175:![0-9]+]], metadata !DIExpression()), !dbg [[DBG177:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG178:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG178]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG178]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 1, !dbg [[DBG178:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG178]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX6]], inrange i64 0, i64 1, !dbg [[DBG178]] // CHECK1-NEXT: store ptr [[ARRAYIDX7]], ptr [[F]], align 8, !dbg [[DBG177]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]] // CHECK1-NEXT: store ptr [[A_ADDR]], ptr [[G]], align 8, !dbg [[DBG180]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META181:![0-9]+]], metadata !DIExpression()), !dbg [[DBG182:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 1, !dbg [[DBG183:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG183]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], inrange i64 0, i64 1, !dbg [[DBG183:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX8]], inrange i64 0, i64 1, !dbg [[DBG183]] // CHECK1-NEXT: store ptr [[ARRAYIDX9]], ptr [[H]], align 8, !dbg [[DBG182]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]] // CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG185]] // CHECK1-NEXT: store i32 5, ptr [[A_ADDR]], align 4, !dbg [[DBG186:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], inrange i64 0, i64 0, !dbg [[DBG187:![0-9]+]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG188:![0-9]+]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG187]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG187]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX10]], inrange i64 0, i64 [[IDXPROM]], !dbg [[DBG187]] // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX11]], align 4, !dbg [[DBG189:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG190:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG190]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG190:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX12]], inrange i64 0, i64 0, !dbg [[DBG190]] // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG191:![0-9]+]] // CHECK1-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG190]] -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG190]] +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX13]], inrange i64 0, i64 [[IDXPROM14]], !dbg [[DBG190]] // CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX15]], align 4, !dbg [[DBG192:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG193:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG193]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG193:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX16]], inrange i64 0, i64 0, !dbg [[DBG193]] // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] // CHECK1-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG193]] -// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG193]] +// CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX17]], inrange i64 0, i64 [[IDXPROM18]], !dbg [[DBG193]] // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4, !dbg [[DBG193]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], i64 0, i64 0, !dbg [[DBG195:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP5]], inrange i64 0, i64 0, !dbg [[DBG195:![0-9]+]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG196:![0-9]+]] // CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG195]] -// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG195]] +// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX20]], inrange i64 0, i64 [[IDXPROM21]], !dbg [[DBG195]] // CHECK1-NEXT: store i32 [[TMP22]], ptr [[ARRAYIDX22]], align 4, !dbg [[DBG197:![0-9]+]] // CHECK1-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP8]], align 1, !dbg [[DBG198:![0-9]+]] // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP24]] to i1, !dbg [[DBG198]] @@ -782,45 +782,45 @@ // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG264]] // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !dbg [[DBG264]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[F]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG267:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 1, !dbg [[DBG268:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG268]] -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG268]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 1, !dbg [[DBG268:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG268]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX7]], inrange i64 0, i64 1, !dbg [[DBG268]] // CHECK1-NEXT: store ptr [[ARRAYIDX8]], ptr [[F]], align 8, !dbg [[DBG267]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[G]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] // CHECK1-NEXT: store ptr [[TMP5]], ptr [[G]], align 8, !dbg [[DBG270]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[H]], metadata [[META271:![0-9]+]], metadata !DIExpression()), !dbg [[DBG272:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 1, !dbg [[DBG273:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG273]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 1, !dbg [[DBG273:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX9]], inrange i64 0, i64 1, !dbg [[DBG273]] // CHECK1-NEXT: store ptr [[ARRAYIDX10]], ptr [[H]], align 8, !dbg [[DBG272]] // CHECK1-NEXT: call void @llvm.dbg.declare(metadata ptr [[D]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG275:![0-9]+]] // CHECK1-NEXT: store i32 15, ptr [[D]], align 4, !dbg [[DBG275]] // CHECK1-NEXT: store i32 5, ptr [[TMP5]], align 4, !dbg [[DBG276:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG277:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 0, !dbg [[DBG277:![0-9]+]] // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG278:![0-9]+]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG277]] -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG277]] +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 [[IDXPROM]], !dbg [[DBG277]] // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX12]], align 4, !dbg [[DBG279:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG280:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG280]] +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG280:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX13]], inrange i64 0, i64 0, !dbg [[DBG280]] // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG281:![0-9]+]] // CHECK1-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG280]] -// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG280]] +// CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX14]], inrange i64 0, i64 [[IDXPROM15]], !dbg [[DBG280]] // CHECK1-NEXT: store i32 11, ptr [[ARRAYIDX16]], align 4, !dbg [[DBG282:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], i64 0, i64 0, !dbg [[DBG283:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG283]] +// CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], ptr [[TMP2]], inrange i64 0, i64 0, !dbg [[DBG283:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[ARRAYIDX17]], inrange i64 0, i64 0, !dbg [[DBG283]] // CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG284:![0-9]+]] // CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG283]] -// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG283]] +// CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX18]], inrange i64 0, i64 [[IDXPROM19]], !dbg [[DBG283]] // CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4, !dbg [[DBG283]] -// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG285:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 0, !dbg [[DBG285:![0-9]+]] // CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG286:![0-9]+]] // CHECK1-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG285]] -// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG285]] +// CHECK1-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX21]], inrange i64 0, i64 [[IDXPROM22]], !dbg [[DBG285]] // CHECK1-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX23]], align 4, !dbg [[DBG287:![0-9]+]] -// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], i64 0, i64 0, !dbg [[DBG288:![0-9]+]] +// CHECK1-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], ptr [[TMP8]], inrange i64 0, i64 0, !dbg [[DBG288:![0-9]+]] // CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG289:![0-9]+]] // CHECK1-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG288]] -// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG288]] +// CHECK1-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX24]], inrange i64 0, i64 [[IDXPROM25]], !dbg [[DBG288]] // CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[ARRAYIDX26]], align 4, !dbg [[DBG288]] // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG288]] // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG290:![0-9]+]] Index: clang/test/OpenMP/target_parallel_for_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/target_parallel_for_simd_codegen.cpp +++ clang/test/OpenMP/target_parallel_for_simd_codegen.cpp @@ -1232,7 +1232,7 @@ // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -1244,8 +1244,8 @@ // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] @@ -1891,7 +1891,7 @@ // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP41]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] @@ -2857,7 +2857,7 @@ // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -2869,8 +2869,8 @@ // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] @@ -3516,7 +3516,7 @@ // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP42]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] @@ -4488,7 +4488,7 @@ // CHECK5-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK5-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK5-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK5-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -4500,8 +4500,8 @@ // CHECK5-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK5-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK5-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK5-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK5-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP35]] @@ -5254,7 +5254,7 @@ // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] @@ -6220,7 +6220,7 @@ // CHECK7-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK7-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -6232,8 +6232,8 @@ // CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK7-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK7-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] @@ -6986,7 +6986,7 @@ // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] @@ -7263,7 +7263,7 @@ // CHECK9-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 // CHECK9-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double // CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 @@ -7275,8 +7275,8 @@ // CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 // CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float // CHECK9-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 -// CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i64 0, i64 1 +// CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 // CHECK9-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] @@ -7480,7 +7480,7 @@ // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] @@ -7740,7 +7740,7 @@ // CHECK11-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 // CHECK11-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double // CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 @@ -7752,8 +7752,8 @@ // CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 // CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float // CHECK11-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 -// CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i32 0, i32 1 +// CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 // CHECK11-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] @@ -7956,7 +7956,7 @@ // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -8218,7 +8218,7 @@ // CHECK13-NEXT: [[TMP49:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 // CHECK13-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP50:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double // CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 @@ -8230,8 +8230,8 @@ // CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 // CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float // CHECK13-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i64 0, i64 1 +// CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP52:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 // CHECK13-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] @@ -8482,7 +8482,7 @@ // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] @@ -8742,7 +8742,7 @@ // CHECK15-NEXT: [[TMP47:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 // CHECK15-NEXT: store i32 [[ADD79]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP48:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double // CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 @@ -8754,8 +8754,8 @@ // CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 // CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float // CHECK15-NEXT: store float [[CONV86]], ptr [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i32 0, i32 1 +// CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX87]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP50:%.*]] = load double, ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 // CHECK15-NEXT: store double [[ADD89]], ptr [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] @@ -9005,7 +9005,7 @@ // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] @@ -9471,7 +9471,7 @@ // CHECK17-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK17-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK17-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK17-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -9483,8 +9483,8 @@ // CHECK17-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK17-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK17-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK17-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK17-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] @@ -9787,7 +9787,7 @@ // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP29]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] @@ -10261,7 +10261,7 @@ // CHECK19-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK19-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -10273,8 +10273,8 @@ // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK19-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK19-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] @@ -10577,7 +10577,7 @@ // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP30]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] @@ -11051,7 +11051,7 @@ // CHECK21-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK21-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK21-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK21-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -11063,8 +11063,8 @@ // CHECK21-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK21-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK21-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK21-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK21-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK21-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] @@ -11453,7 +11453,7 @@ // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP32]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] @@ -11927,7 +11927,7 @@ // CHECK23-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK23-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double // CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 @@ -11939,8 +11939,8 @@ // CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK23-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK23-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] @@ -12329,7 +12329,7 @@ // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] Index: clang/test/OpenMP/target_private_codegen.cpp =================================================================== --- clang/test/OpenMP/target_private_codegen.cpp +++ clang/test/OpenMP/target_private_codegen.cpp @@ -110,7 +110,7 @@ // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A]], // b[2] = 1.0 - // TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 + // TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 2 // TCHECK: store float 1.0{{.*}}, float* [[B_GEP]], // bn[3] = 1.0 @@ -118,8 +118,8 @@ // TCHECK: store float 1.0{{.*}}, float* [[BN_GEP]], // c[1][2] = 1.0 - // TCHECK: [[C_GEP1:%.+]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i{{[0-9]+}} 0, i{{[0-9]+}} 1 - // TCHECK: [[C_GEP2:%.+]] = getelementptr inbounds [10 x double], [10 x double]* [[C_GEP1]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 + // TCHECK: [[C_GEP1:%.+]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 1 + // TCHECK: [[C_GEP2:%.+]] = getelementptr inbounds [10 x double], [10 x double]* [[C_GEP1]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 2 // TCHECK: store double 1.0{{.*}}, double* [[C_GEP2]], // cn[1][3] = 1.0 @@ -187,7 +187,7 @@ // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A2]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A3]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 +// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 2 // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[B_GEP]], // TCHECK: ret void @@ -267,7 +267,7 @@ // TCHECK: [[B:%.+]] = alloca [10 x i{{[0-9]+}}], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A2]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 +// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 2 // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[B_GEP]], // TCHECK: ret void Index: clang/test/OpenMP/target_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/target_reduction_codegen.cpp +++ clang/test/OpenMP/target_reduction_codegen.cpp @@ -134,7 +134,7 @@ // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A_REF]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[AA_REF]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A3_REF]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 +// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B_REF]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 2 // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[B_GEP]], // TCHECK: ret void @@ -218,7 +218,7 @@ // TCHECK: [[B_REF:%.+]] = load {{.+}}*, {{.+}}** [[B]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[A_REF]], // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[AA_REF]], -// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B_REF]], i{{[0-9]+}} 0, i{{[0-9]+}} 2 +// TCHECK: [[B_GEP:%.+]] = getelementptr inbounds [10 x i{{[0-9]+}}], [10 x i{{[0-9]+}}]* [[B_REF]], inrange i{{[0-9]+}} 0, i{{[0-9]+}} 2 // TCHECK: store i{{[0-9]+}} 1, i{{[0-9]+}}* [[B_GEP]], // TCHECK: ret void Index: clang/test/OpenMP/target_teams_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_codegen.cpp +++ clang/test/OpenMP/target_teams_codegen.cpp @@ -1070,7 +1070,7 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK1-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK1-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -1082,8 +1082,8 @@ // CHECK1-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK1-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK1-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK1-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -1731,7 +1731,7 @@ // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK1-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -1782,7 +1782,7 @@ // CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK1-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -2564,7 +2564,7 @@ // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK3-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -2576,8 +2576,8 @@ // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK3-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -3224,7 +3224,7 @@ // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK3-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -3275,7 +3275,7 @@ // CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK3-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK3-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -3466,7 +3466,7 @@ // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK9-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK9-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -3478,8 +3478,8 @@ // CHECK9-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK9-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK9-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK9-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK9-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -3664,7 +3664,7 @@ // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK9-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK9-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -3778,7 +3778,7 @@ // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK9-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK9-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 @@ -3962,7 +3962,7 @@ // CHECK11-NEXT: [[TMP8:%.*]] = load i32, ptr [[A_ADDR]], align 4 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 // CHECK11-NEXT: store i32 [[ADD]], ptr [[A_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -3974,8 +3974,8 @@ // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float // CHECK11-NEXT: store float [[CONV10]], ptr [[ARRAYIDX7]], align 4 -// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX11]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP11:%.*]] = load double, ptr [[ARRAYIDX12]], align 8 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 // CHECK11-NEXT: store double [[ADD13]], ptr [[ARRAYIDX12]], align 8 @@ -4160,7 +4160,7 @@ // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 // CHECK11-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8 // CHECK11-NEXT: store i8 [[CONV5]], ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP4]], 1 // CHECK11-NEXT: store i32 [[ADD6]], ptr [[ARRAYIDX]], align 4 @@ -4274,7 +4274,7 @@ // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[CONV]], 1 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16 // CHECK11-NEXT: store i16 [[CONV2]], ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP3]], 1 // CHECK11-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/target_teams_distribute_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_codegen.cpp @@ -1232,7 +1232,7 @@ // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK1-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double // CHECK1-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -1244,8 +1244,8 @@ // CHECK1-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK1-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK1-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]] // CHECK1-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP22]] @@ -1908,7 +1908,7 @@ // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 @@ -2013,7 +2013,7 @@ // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -2977,7 +2977,7 @@ // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK3-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -2989,8 +2989,8 @@ // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK3-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP23]] -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP23]] @@ -3653,7 +3653,7 @@ // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 @@ -3758,7 +3758,7 @@ // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -4165,7 +4165,7 @@ // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK9-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double // CHECK9-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -4177,8 +4177,8 @@ // CHECK9-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK9-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK9-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]] // CHECK9-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK9-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP13]] @@ -4354,7 +4354,7 @@ // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK9-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK9-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK9-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 @@ -4572,7 +4572,7 @@ // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK9-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK9-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 @@ -4972,7 +4972,7 @@ // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], 1 // CHECK11-NEXT: store i32 [[ADD7]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP20:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP20]] to double // CHECK11-NEXT: [[ADD8:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -4984,8 +4984,8 @@ // CHECK11-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 // CHECK11-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float // CHECK11-NEXT: store float [[CONV13]], ptr [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX14]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP22:%.*]] = load double, ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]] // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 // CHECK11-NEXT: store double [[ADD16]], ptr [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP14]] @@ -5161,7 +5161,7 @@ // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK11-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK11-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK11-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4 @@ -5379,7 +5379,7 @@ // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK11-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK11-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4 Index: clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_collapse_codegen.cpp @@ -157,8 +157,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -235,10 +235,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -325,8 +325,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -402,9 +402,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -870,10 +870,10 @@ // CHECK9-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1335,9 +1335,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_dist_schedule_codegen.cpp @@ -278,7 +278,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -344,7 +344,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -422,7 +422,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -507,7 +507,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -697,7 +697,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -762,7 +762,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -839,7 +839,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -923,7 +923,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1810,7 +1810,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1887,7 +1887,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1971,7 +1971,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2856,7 +2856,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2932,7 +2932,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3015,7 +3015,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_firstprivate_codegen.cpp @@ -454,11 +454,11 @@ // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -814,12 +814,12 @@ // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1262,10 +1262,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1620,11 +1620,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_lastprivate_codegen.cpp @@ -723,12 +723,12 @@ // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP14]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1062,12 +1062,12 @@ // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1430,11 +1430,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1767,11 +1767,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP14]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_codegen.cpp @@ -110,7 +110,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED3]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[G_ADDR]], align 8 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i64 [[TMP10]], ptr [[A]], ptr [[TMP11]]) #[[ATTR2]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP12]] // @@ -310,7 +310,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 @@ -544,7 +544,7 @@ // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX7]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -752,7 +752,7 @@ // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i64 [[TMP47]], ptr [[A]], ptr [[TMP48]]) #[[ATTR2]] // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]] // CHECK2: omp_offload.cont20: -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i64 0, i64 0 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i64 0, i64 0 // CHECK2-NEXT: [[TMP79:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: ret i32 [[TMP79]] // @@ -952,7 +952,7 @@ // CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 @@ -1186,7 +1186,7 @@ // CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX7]], align 4 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -1401,7 +1401,7 @@ // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i32 [[TMP47]], ptr [[A]], ptr [[TMP48]]) #[[ATTR2]] // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT20]] // CHECK4: omp_offload.cont20: -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i32 0, i32 0 +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i32 0, i32 0 // CHECK4-NEXT: [[TMP79:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK4-NEXT: ret i32 [[TMP79]] // @@ -1596,7 +1596,7 @@ // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK4-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK4-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 @@ -1825,7 +1825,7 @@ // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP19]] // CHECK4-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK4: omp.body.continue: @@ -2048,7 +2048,7 @@ // CHECK10-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK10-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK10-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 @@ -2282,7 +2282,7 @@ // CHECK10-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK10-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4 // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK10-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX7]], align 4 // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK10: omp.body.continue: @@ -2493,7 +2493,7 @@ // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK12-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK12-NEXT: [[TMP17:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP17]] +// CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP17]] // CHECK12-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4 @@ -2722,7 +2722,7 @@ // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0 // CHECK12-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP19]] // CHECK12-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK12: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_collapse_codegen.cpp @@ -162,8 +162,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -315,10 +315,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -405,8 +405,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -553,9 +553,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1222,10 +1222,10 @@ // CHECK9-NEXT: store i32 [[ADD7]], ptr [[J]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1888,9 +1888,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -290,7 +290,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -429,7 +429,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -580,7 +580,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -751,7 +751,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -931,7 +931,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -1065,7 +1065,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1211,7 +1211,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1377,7 +1377,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2669,7 +2669,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2819,7 +2819,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3004,7 +3004,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -4278,7 +4278,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4423,7 +4423,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4603,7 +4603,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -680,11 +680,11 @@ // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1150,12 +1150,12 @@ // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1744,10 +1744,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -2208,11 +2208,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2945,11 +2945,11 @@ // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -3253,12 +3253,12 @@ // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3656,10 +3656,10 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP15]] // CHECK15-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -3958,11 +3958,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -1138,12 +1138,12 @@ // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1622,12 +1622,12 @@ // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2140,11 +2140,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2618,11 +2618,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_private_codegen.cpp @@ -511,11 +511,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -822,12 +822,12 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1246,10 +1246,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1551,11 +1551,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2135,11 +2135,11 @@ // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -2373,12 +2373,12 @@ // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2640,10 +2640,10 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -2872,11 +2872,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_schedule_codegen.cpp @@ -444,7 +444,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK1: omp_offload.cont33: // CHECK1-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP100]] // @@ -583,7 +583,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -734,7 +734,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -896,7 +896,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1054,7 +1054,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1203,7 +1203,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1478,7 +1478,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK3: omp_offload.cont33: // CHECK3-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP100]] // @@ -1612,7 +1612,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1758,7 +1758,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1913,7 +1913,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2066,7 +2066,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2210,7 +2210,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2485,7 +2485,7 @@ // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK5: omp_offload.cont33: // CHECK5-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: ret i32 [[TMP100]] // @@ -2624,7 +2624,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2775,7 +2775,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2937,7 +2937,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3095,7 +3095,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3244,7 +3244,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3519,7 +3519,7 @@ // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK7: omp_offload.cont33: // CHECK7-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: ret i32 [[TMP100]] // @@ -3653,7 +3653,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -3799,7 +3799,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -3954,7 +3954,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4107,7 +4107,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4251,7 +4251,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -6263,7 +6263,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6413,7 +6413,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6589,7 +6589,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6746,7 +6746,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6909,7 +6909,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -8895,7 +8895,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9040,7 +9040,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9209,7 +9209,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9361,7 +9361,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9519,7 +9519,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -11531,7 +11531,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -11681,7 +11681,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -11857,7 +11857,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -12014,7 +12014,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -12177,7 +12177,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -14163,7 +14163,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14308,7 +14308,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14477,7 +14477,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14629,7 +14629,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14787,7 +14787,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_codegen.cpp @@ -280,7 +280,7 @@ // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56(i64 [[TMP52]], ptr [[A]], ptr [[TMP53]]) #[[ATTR4]] // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] // CHECK1: omp_offload.cont20: -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP84:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP84]] // @@ -520,7 +520,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I5]], align 4 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[I5]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -769,7 +769,7 @@ // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1222,7 +1222,7 @@ // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l56(i32 [[TMP52]], ptr [[A]], ptr [[TMP53]]) #[[ATTR4]] // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT20]] // CHECK3: omp_offload.cont20: -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP84:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP84]] // @@ -1457,7 +1457,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP21]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP21]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1701,7 +1701,7 @@ // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP19]] // CHECK3-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2028,7 +2028,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I7]], align 4 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, ptr [[I7]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2080,7 +2080,7 @@ // CHECK5-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK5-NEXT: [[TMP26:%.*]] = load i32, ptr [[I27]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK5-NEXT: [[IDXPROM34:%.*]] = sext i32 [[TMP26]] to i64 -// CHECK5-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i64 0, i64 [[IDXPROM34]] +// CHECK5-NEXT: [[ARRAYIDX35:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM34]] // CHECK5-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX35]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE36:%.*]] // CHECK5: omp.body.continue36: @@ -2099,7 +2099,7 @@ // CHECK5-NEXT: store i32 [[ADD43]], ptr [[I27]], align 4 // CHECK5-NEXT: br label [[SIMD_IF_END44]] // CHECK5: simd.if.end44: -// CHECK5-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX45]], align 4 // CHECK5-NEXT: ret i32 [[TMP29]] // @@ -2220,7 +2220,7 @@ // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], ptr [[I7]], align 4 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, ptr [[I7]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i32 0, i32 [[TMP13]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i32 0, i32 [[TMP13]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2271,7 +2271,7 @@ // CHECK7-NEXT: [[ARRAYIDX33:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i32 0 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX33]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP26:%.*]] = load i32, ptr [[I27]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK7-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i32 0, i32 [[TMP26]] +// CHECK7-NEXT: [[ARRAYIDX34:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i32 0, i32 [[TMP26]] // CHECK7-NEXT: store i32 [[TMP25]], ptr [[ARRAYIDX34]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE35:%.*]] // CHECK7: omp.body.continue35: @@ -2290,7 +2290,7 @@ // CHECK7-NEXT: store i32 [[ADD42]], ptr [[I27]], align 4 // CHECK7-NEXT: br label [[SIMD_IF_END43]] // CHECK7: simd.if.end43: -// CHECK7-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX44:%.*]] = getelementptr inbounds [1000 x i32], ptr [[A]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX44]], align 4 // CHECK7-NEXT: ret i32 [[TMP29]] // @@ -2571,7 +2571,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I5]], align 4 // CHECK9-NEXT: [[TMP21:%.*]] = load i32, ptr [[I5]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2820,7 +2820,7 @@ // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3244,7 +3244,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP21]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP21]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3488,7 +3488,7 @@ // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_collapse_codegen.cpp @@ -162,8 +162,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -323,10 +323,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -421,8 +421,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -577,9 +577,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -659,10 +659,10 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -676,8 +676,8 @@ // CHECK5-NEXT: store i32 123, ptr [[I]], align 4 // CHECK5-NEXT: store i32 456, ptr [[J]], align 4 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], inrange i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 // CHECK5-NEXT: ret i32 [[TMP9]] // @@ -729,9 +729,9 @@ // CHECK7-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -745,8 +745,8 @@ // CHECK7-NEXT: store i32 123, ptr [[I]], align 4 // CHECK7-NEXT: store i32 456, ptr [[J]], align 4 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], inrange i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 // CHECK7-NEXT: ret i32 [[TMP9]] // @@ -1438,10 +1438,10 @@ // CHECK9-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2156,9 +2156,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2374,10 +2374,10 @@ // CHECK13-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] +// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM6]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2572,9 +2572,9 @@ // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] // CHECK15-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp @@ -290,7 +290,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -436,7 +436,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -601,7 +601,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -786,7 +786,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -973,7 +973,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -1114,7 +1114,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1274,7 +1274,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1454,7 +1454,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1532,7 +1532,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1562,7 +1562,7 @@ // CHECK5-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i64 0, i64 [[IDXPROM14]] +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i64 0, i64 [[IDXPROM14]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX15]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] // CHECK5: omp.body.continue16: @@ -1592,7 +1592,7 @@ // CHECK5-NEXT: [[A30:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], i64 0, i64 [[IDXPROM31]] +// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], inrange i64 0, i64 [[IDXPROM31]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK5: omp.body.continue33: @@ -1605,7 +1605,7 @@ // CHECK5: omp.inner.for.end36: // CHECK5-NEXT: store i32 123, ptr [[I24]], align 4 // CHECK5-NEXT: [[A37:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX38]], align 4 // CHECK5-NEXT: ret i32 [[TMP18]] // @@ -1656,7 +1656,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1685,7 +1685,7 @@ // CHECK7-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK7: omp.body.continue15: @@ -1714,7 +1714,7 @@ // CHECK7-NEXT: store i32 [[ADD28]], ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], inrange i32 0, i32 [[TMP16]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX30]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE31:%.*]] // CHECK7: omp.body.continue31: @@ -1727,7 +1727,7 @@ // CHECK7: omp.inner.for.end34: // CHECK7-NEXT: store i32 123, ptr [[I23]], align 4 // CHECK7-NEXT: [[A35:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX36]], align 4 // CHECK7-NEXT: ret i32 [[TMP18]] // @@ -3079,7 +3079,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3243,7 +3243,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3442,7 +3442,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -4802,7 +4802,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4961,7 +4961,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -5155,7 +5155,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -5431,7 +5431,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -5460,7 +5460,7 @@ // CHECK13-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM12]] +// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM12]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK13: omp.body.continue14: @@ -5491,7 +5491,7 @@ // CHECK13-NEXT: store i32 [[ADD27]], ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM28]] +// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM28]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX29]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE30:%.*]] // CHECK13: omp.body.continue30: @@ -5746,7 +5746,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -5774,7 +5774,7 @@ // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK15-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK15: omp.body.continue13: @@ -5804,7 +5804,7 @@ // CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] // CHECK15-NEXT: store i32 [[ADD26]], ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP17]] +// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP17]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX27]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] // CHECK15: omp.body.continue28: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -685,11 +685,11 @@ // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] @@ -1169,12 +1169,12 @@ // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1777,10 +1777,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -2255,11 +2255,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2835,11 +2835,11 @@ // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i64 0, i64 [[IDXPROM]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i64 0, i64 [[IDXPROM1]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -2905,12 +2905,12 @@ // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK7-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -3157,10 +3157,10 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i32 0, i32 [[TMP5]] // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i32 0, i32 [[TMP6]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -3225,11 +3225,11 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK9-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP10:%.*]] = load ptr, ptr [[TMP]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3794,11 +3794,11 @@ // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -4116,12 +4116,12 @@ // CHECK13-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK13-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM10]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -4533,10 +4533,10 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP15]] // CHECK15-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] @@ -4849,11 +4849,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK15-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -1173,12 +1173,12 @@ // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1671,12 +1671,12 @@ // CHECK5-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2203,11 +2203,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2695,11 +2695,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK7-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK7-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK7-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP17]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2919,12 +2919,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3083,12 +3083,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3317,11 +3317,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3479,11 +3479,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_private_codegen.cpp @@ -518,11 +518,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] @@ -843,12 +843,12 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1281,10 +1281,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -1600,11 +1600,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2141,11 +2141,11 @@ // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM1]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -2237,12 +2237,12 @@ // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -2518,10 +2518,10 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP5]] // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP6]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK9-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -2612,11 +2612,11 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3096,11 +3096,11 @@ // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK13-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK13-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -3348,12 +3348,12 @@ // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3629,10 +3629,10 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK15-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP11]] @@ -3875,11 +3875,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_parallel_for_simd_schedule_codegen.cpp @@ -444,7 +444,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK1: omp_offload.cont33: // CHECK1-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP100]] // @@ -590,7 +590,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -755,7 +755,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -931,7 +931,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1103,7 +1103,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1266,7 +1266,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1548,7 +1548,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK3: omp_offload.cont33: // CHECK3-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP100]] // @@ -1689,7 +1689,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1849,7 +1849,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2018,7 +2018,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2185,7 +2185,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2343,7 +2343,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2625,7 +2625,7 @@ // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK5: omp_offload.cont33: // CHECK5-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: ret i32 [[TMP100]] // @@ -2771,7 +2771,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2936,7 +2936,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3112,7 +3112,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3284,7 +3284,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3447,7 +3447,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3729,7 +3729,7 @@ // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK7: omp_offload.cont33: // CHECK7-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: ret i32 [[TMP100]] // @@ -3870,7 +3870,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4030,7 +4030,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4199,7 +4199,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4366,7 +4366,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4524,7 +4524,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4613,7 +4613,7 @@ // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -4643,7 +4643,7 @@ // CHECK9-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i64 0, i64 [[IDXPROM14]] +// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i64 0, i64 [[IDXPROM14]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX15]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] // CHECK9: omp.body.continue16: @@ -4673,7 +4673,7 @@ // CHECK9-NEXT: [[A30:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], i64 0, i64 [[IDXPROM31]] +// CHECK9-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], inrange i64 0, i64 [[IDXPROM31]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK9: omp.body.continue33: @@ -4703,7 +4703,7 @@ // CHECK9-NEXT: [[A47:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[I41]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK9-NEXT: [[IDXPROM48:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK9-NEXT: [[ARRAYIDX49:%.*]] = getelementptr inbounds [123 x i32], ptr [[A47]], i64 0, i64 [[IDXPROM48]] +// CHECK9-NEXT: [[ARRAYIDX49:%.*]] = getelementptr inbounds [123 x i32], ptr [[A47]], inrange i64 0, i64 [[IDXPROM48]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX49]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] // CHECK9: omp.body.continue50: @@ -4733,7 +4733,7 @@ // CHECK9-NEXT: [[A64:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK9-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds [123 x i32], ptr [[A64]], i64 0, i64 [[IDXPROM65]] +// CHECK9-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds [123 x i32], ptr [[A64]], inrange i64 0, i64 [[IDXPROM65]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX66]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE67:%.*]] // CHECK9: omp.body.continue67: @@ -4746,7 +4746,7 @@ // CHECK9: omp.inner.for.end70: // CHECK9-NEXT: store i32 123, ptr [[I58]], align 4 // CHECK9-NEXT: [[A71:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [123 x i32], ptr [[A71]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [123 x i32], ptr [[A71]], inrange i64 0, i64 0 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX72]], align 4 // CHECK9-NEXT: ret i32 [[TMP30]] // @@ -4807,7 +4807,7 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4836,7 +4836,7 @@ // CHECK11-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i32 0, i32 [[TMP10]] +// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i32 0, i32 [[TMP10]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK11: omp.body.continue15: @@ -4865,7 +4865,7 @@ // CHECK11-NEXT: store i32 [[ADD28]], ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX30]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE31:%.*]] // CHECK11: omp.body.continue31: @@ -4894,7 +4894,7 @@ // CHECK11-NEXT: store i32 [[ADD44]], ptr [[I39]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK11-NEXT: [[A45:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[I39]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK11-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds [123 x i32], ptr [[A45]], i32 0, i32 [[TMP22]] +// CHECK11-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds [123 x i32], ptr [[A45]], inrange i32 0, i32 [[TMP22]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX46]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE47:%.*]] // CHECK11: omp.body.continue47: @@ -4923,7 +4923,7 @@ // CHECK11-NEXT: store i32 [[ADD60]], ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[A61:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [123 x i32], ptr [[A61]], i32 0, i32 [[TMP28]] +// CHECK11-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [123 x i32], ptr [[A61]], inrange i32 0, i32 [[TMP28]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX62]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE63:%.*]] // CHECK11: omp.body.continue63: @@ -4936,7 +4936,7 @@ // CHECK11: omp.inner.for.end66: // CHECK11-NEXT: store i32 123, ptr [[I55]], align 4 // CHECK11-NEXT: [[A67:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds [123 x i32], ptr [[A67]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds [123 x i32], ptr [[A67]], inrange i32 0, i32 0 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX68]], align 4 // CHECK11-NEXT: ret i32 [[TMP30]] // @@ -7055,7 +7055,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7219,7 +7219,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7409,7 +7409,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7580,7 +7580,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7757,7 +7757,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -9877,7 +9877,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -10036,7 +10036,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -10219,7 +10219,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -10385,7 +10385,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -10557,7 +10557,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -12703,7 +12703,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -12867,7 +12867,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -13057,7 +13057,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -13228,7 +13228,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -13405,7 +13405,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -15525,7 +15525,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -15684,7 +15684,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -15867,7 +15867,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -16033,7 +16033,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -16205,7 +16205,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -16610,7 +16610,7 @@ // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: @@ -16639,7 +16639,7 @@ // CHECK21-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM12]] +// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM12]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK21: omp.body.continue14: @@ -16670,7 +16670,7 @@ // CHECK21-NEXT: store i32 [[ADD27]], ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK21-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM28]] +// CHECK21-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM28]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX29]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE30:%.*]] // CHECK21: omp.body.continue30: @@ -16699,7 +16699,7 @@ // CHECK21-NEXT: store i32 [[ADD43]], ptr [[I38]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[I38]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[IDXPROM44:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK21-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM44]] +// CHECK21-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM44]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX45]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]] // CHECK21: omp.body.continue46: @@ -16730,7 +16730,7 @@ // CHECK21-NEXT: store i32 [[ADD60]], ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[IDXPROM61:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK21-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM61]] +// CHECK21-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM61]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX62]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE63:%.*]] // CHECK21: omp.body.continue63: @@ -17111,7 +17111,7 @@ // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: @@ -17139,7 +17139,7 @@ // CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK23-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK23-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK23-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK23: omp.body.continue13: @@ -17169,7 +17169,7 @@ // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] // CHECK23-NEXT: store i32 [[ADD26]], ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP17]] +// CHECK23-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP17]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX27]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] // CHECK23: omp.body.continue28: @@ -17197,7 +17197,7 @@ // CHECK23-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] // CHECK23-NEXT: store i32 [[ADD41]], ptr [[I36]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[I36]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK23-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP23]] +// CHECK23-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP23]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX42]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE43:%.*]] // CHECK23: omp.body.continue43: @@ -17227,7 +17227,7 @@ // CHECK23-NEXT: [[ADD57:%.*]] = add nsw i32 0, [[MUL56]] // CHECK23-NEXT: store i32 [[ADD57]], ptr [[I52]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[I52]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK23-NEXT: [[ARRAYIDX58:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP30]] +// CHECK23-NEXT: [[ARRAYIDX58:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP30]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX58]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE59:%.*]] // CHECK23: omp.body.continue59: Index: clang/test/OpenMP/target_teams_distribute_private_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_private_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_private_codegen.cpp @@ -349,11 +349,11 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -556,12 +556,12 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -883,10 +883,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1088,11 +1088,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_reduction_codegen.cpp @@ -2832,7 +2832,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], [[TMP11]] @@ -2964,7 +2964,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP10]], [[TMP12]] // CHECK1-NEXT: store i32 [[MUL3]], ptr [[T_VAR1]], align 4 @@ -3112,7 +3112,7 @@ // CHECK1: land.rhs: // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[REM:%.*]] = srem i32 [[TMP12]], 2 // CHECK1-NEXT: [[CMP3:%.*]] = icmp eq i32 [[REM]], 0 @@ -3289,7 +3289,7 @@ // CHECK1: lor.rhs: // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[REM:%.*]] = srem i32 [[TMP12]], 2 // CHECK1-NEXT: [[CMP3:%.*]] = icmp eq i32 [[REM]], 0 @@ -3461,7 +3461,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[BIT_VAR1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[AND:%.*]] = and i32 [[TMP10]], [[TMP12]] // CHECK1-NEXT: store i32 [[AND]], ptr [[BIT_VAR1]], align 4 @@ -3590,7 +3590,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[BIT_VAR1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[OR:%.*]] = or i32 [[TMP10]], [[TMP12]] // CHECK1-NEXT: store i32 [[OR]], ptr [[BIT_VAR1]], align 4 @@ -3719,7 +3719,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[BIT_VAR1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[XOR:%.*]] = xor i32 [[TMP10]], [[TMP12]] // CHECK1-NEXT: store i32 [[XOR]], ptr [[BIT_VAR1]], align 4 @@ -3848,7 +3848,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sge i32 [[TMP10]], [[TMP12]] // CHECK1-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]] @@ -3858,7 +3858,7 @@ // CHECK1: cond.false5: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM6]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM6]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4 // CHECK1-NEXT: br label [[COND_END8]] // CHECK1: cond.end8: @@ -4007,7 +4007,7 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP12]] // CHECK1-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]] @@ -4017,7 +4017,7 @@ // CHECK1: cond.false5: // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM6]] +// CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM6]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4 // CHECK1-NEXT: br label [[COND_END8]] // CHECK1: cond.end8: @@ -6666,7 +6666,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP10]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP12]], [[TMP11]] @@ -6797,7 +6797,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[TMP10]], [[TMP12]] // CHECK3-NEXT: store i32 [[MUL3]], ptr [[T_VAR1]], align 4 @@ -6944,7 +6944,7 @@ // CHECK3-NEXT: br i1 [[TOBOOL]], label [[LAND_RHS:%.*]], label [[LAND_END:%.*]] // CHECK3: land.rhs: // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[REM:%.*]] = srem i32 [[TMP12]], 2 // CHECK3-NEXT: [[CMP3:%.*]] = icmp eq i32 [[REM]], 0 @@ -7120,7 +7120,7 @@ // CHECK3-NEXT: br i1 [[TOBOOL]], label [[LOR_END:%.*]], label [[LOR_RHS:%.*]] // CHECK3: lor.rhs: // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[REM:%.*]] = srem i32 [[TMP12]], 2 // CHECK3-NEXT: [[CMP3:%.*]] = icmp eq i32 [[REM]], 0 @@ -7291,7 +7291,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[BIT_VAR1]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[AND:%.*]] = and i32 [[TMP10]], [[TMP12]] // CHECK3-NEXT: store i32 [[AND]], ptr [[BIT_VAR1]], align 4 @@ -7419,7 +7419,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[BIT_VAR1]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[OR:%.*]] = or i32 [[TMP10]], [[TMP12]] // CHECK3-NEXT: store i32 [[OR]], ptr [[BIT_VAR1]], align 4 @@ -7547,7 +7547,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[BIT_VAR1]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[XOR:%.*]] = xor i32 [[TMP10]], [[TMP12]] // CHECK3-NEXT: store i32 [[XOR]], ptr [[BIT_VAR1]], align 4 @@ -7675,7 +7675,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sge i32 [[TMP10]], [[TMP12]] // CHECK3-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]] @@ -7684,7 +7684,7 @@ // CHECK3-NEXT: br label [[COND_END7:%.*]] // CHECK3: cond.false5: // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4 // CHECK3-NEXT: br label [[COND_END7]] // CHECK3: cond.end7: @@ -7832,7 +7832,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR1]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[CMP3:%.*]] = icmp sle i32 [[TMP10]], [[TMP12]] // CHECK3-NEXT: br i1 [[CMP3]], label [[COND_TRUE4:%.*]], label [[COND_FALSE5:%.*]] @@ -7841,7 +7841,7 @@ // CHECK3-NEXT: br label [[COND_END7:%.*]] // CHECK3: cond.false5: // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX6]], align 4 // CHECK3-NEXT: br label [[COND_END7]] // CHECK3: cond.end7: Index: clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_simd_codegen.cpp @@ -1230,7 +1230,7 @@ // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK1-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK1-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -1242,8 +1242,8 @@ // CHECK1-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK1-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK1-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP35]] -// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]] // CHECK1-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK1-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP35]] @@ -1910,7 +1910,7 @@ // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK1-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK1-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP41]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] // CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK1-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] @@ -2031,7 +2031,7 @@ // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK1-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP44]] -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK1-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] @@ -3001,7 +3001,7 @@ // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK3-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK3-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -3013,8 +3013,8 @@ // CHECK3-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK3-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK3-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK3-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK3-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] @@ -3681,7 +3681,7 @@ // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK3-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK3-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP42]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] // CHECK3-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK3-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] @@ -3802,7 +3802,7 @@ // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK3-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP45]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK3-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] @@ -4772,7 +4772,7 @@ // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK5-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK5-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -4784,8 +4784,8 @@ // CHECK5-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK5-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK5-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP36]] -// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK5-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] // CHECK5-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK5-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP36]] @@ -5521,7 +5521,7 @@ // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK5-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK5-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP44]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] // CHECK5-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK5-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] @@ -5642,7 +5642,7 @@ // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK5-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK5-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP47]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]] // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK5-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP47]] @@ -6612,7 +6612,7 @@ // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK7-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK7-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -6624,8 +6624,8 @@ // CHECK7-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK7-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK7-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP37]] -// CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]] // CHECK7-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK7-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP37]] @@ -7361,7 +7361,7 @@ // CHECK7-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK7-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK7-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP45]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK7-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK7-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] @@ -7482,7 +7482,7 @@ // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK7-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK7-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP48]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]] // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK7-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP48]] @@ -7712,7 +7712,7 @@ // CHECK9-NEXT: [[TMP37:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 // CHECK9-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP38:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double // CHECK9-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 @@ -7724,8 +7724,8 @@ // CHECK9-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 // CHECK9-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float // CHECK9-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 -// CHECK9-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i64 0, i64 1 +// CHECK9-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP40:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 // CHECK9-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP15]] @@ -7941,7 +7941,7 @@ // CHECK9-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK9-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 // CHECK9-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP21]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK9-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] @@ -8008,7 +8008,7 @@ // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK9-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i64 0, i64 2 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK9-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] @@ -8221,7 +8221,7 @@ // CHECK11-NEXT: [[TMP35:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 // CHECK11-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP36:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double // CHECK11-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 @@ -8233,8 +8233,8 @@ // CHECK11-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 // CHECK11-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float // CHECK11-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 -// CHECK11-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i32 0, i32 1 +// CHECK11-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP38:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 // CHECK11-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]] @@ -8449,7 +8449,7 @@ // CHECK11-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK11-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 // CHECK11-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK11-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] @@ -8516,7 +8516,7 @@ // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK11-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i32 0, i32 2 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK11-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] @@ -8731,7 +8731,7 @@ // CHECK13-NEXT: [[TMP37:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK13-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP37]], 1 // CHECK13-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP38:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK13-NEXT: [[CONV65:%.*]] = fpext float [[TMP38]] to double // CHECK13-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 @@ -8743,8 +8743,8 @@ // CHECK13-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 // CHECK13-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float // CHECK13-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK13-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i64 0, i64 1 -// CHECK13-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i64 0, i64 1 +// CHECK13-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP40:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]] // CHECK13-NEXT: [[ADD74:%.*]] = fadd double [[TMP40]], 1.000000e+00 // CHECK13-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP16]] @@ -9007,7 +9007,7 @@ // CHECK13-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK13-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 // CHECK13-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP24]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK13-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] @@ -9074,7 +9074,7 @@ // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK13-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP27]] -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i64 0, i64 2 +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i64 0, i64 2 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK13-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] @@ -9287,7 +9287,7 @@ // CHECK15-NEXT: [[TMP35:%.*]] = load i32, ptr [[A]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK15-NEXT: [[ADD64:%.*]] = add nsw i32 [[TMP35]], 1 // CHECK15-NEXT: store i32 [[ADD64]], ptr [[A]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[B]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP36:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK15-NEXT: [[CONV65:%.*]] = fpext float [[TMP36]] to double // CHECK15-NEXT: [[ADD66:%.*]] = fadd double [[CONV65]], 1.000000e+00 @@ -9299,8 +9299,8 @@ // CHECK15-NEXT: [[ADD70:%.*]] = fadd double [[CONV69]], 1.000000e+00 // CHECK15-NEXT: [[CONV71:%.*]] = fptrunc double [[ADD70]] to float // CHECK15-NEXT: store float [[CONV71]], ptr [[ARRAYIDX68]], align 4, !llvm.access.group [[ACC_GRP17]] -// CHECK15-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], i32 0, i32 1 -// CHECK15-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[C]], inrange i32 0, i32 1 +// CHECK15-NEXT: [[ARRAYIDX73:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX72]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP38:%.*]] = load double, ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK15-NEXT: [[ADD74:%.*]] = fadd double [[TMP38]], 1.000000e+00 // CHECK15-NEXT: store double [[ADD74]], ptr [[ARRAYIDX73]], align 8, !llvm.access.group [[ACC_GRP17]] @@ -9562,7 +9562,7 @@ // CHECK15-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 // CHECK15-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i8 // CHECK15-NEXT: store i8 [[CONV14]], ptr [[AAA]], align 1, !llvm.access.group [[ACC_GRP25]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK15-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] @@ -9629,7 +9629,7 @@ // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 // CHECK15-NEXT: store i16 [[CONV3]], ptr [[AA]], align 2, !llvm.access.group [[ACC_GRP28]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], i32 0, i32 2 +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[B]], inrange i32 0, i32 2 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 // CHECK15-NEXT: store i32 [[ADD4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] @@ -10035,7 +10035,7 @@ // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK17-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK17-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -10047,8 +10047,8 @@ // CHECK17-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK17-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK17-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK17-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK17-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] @@ -10221,7 +10221,7 @@ // CHECK17-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK17-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK17-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK17-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK17-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] @@ -10462,7 +10462,7 @@ // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK17-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP33]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK17-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] @@ -10876,7 +10876,7 @@ // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK19-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK19-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -10888,8 +10888,8 @@ // CHECK19-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK19-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK19-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK19-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK19-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] @@ -11062,7 +11062,7 @@ // CHECK19-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK19-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK19-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK19-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK19-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] @@ -11303,7 +11303,7 @@ // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK19-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP34]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK19-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] @@ -11717,7 +11717,7 @@ // CHECK21-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK21-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK21-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -11729,8 +11729,8 @@ // CHECK21-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK21-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK21-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP24]] -// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i64 0, i64 1 -// CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i64 0, i64 1 +// CHECK21-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK21-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP24]] @@ -11903,7 +11903,7 @@ // CHECK21-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK21-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK21-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP27]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK21-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] @@ -12196,7 +12196,7 @@ // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK21-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK21-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP35]] -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 2 +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 2 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK21-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] @@ -12610,7 +12610,7 @@ // CHECK23-NEXT: [[TMP16:%.*]] = load i32, ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP16]], 1 // CHECK23-NEXT: store i32 [[ADD6]], ptr [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP17:%.*]] = load float, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[CONV:%.*]] = fpext float [[TMP17]] to double // CHECK23-NEXT: [[ADD7:%.*]] = fadd double [[CONV]], 1.000000e+00 @@ -12622,8 +12622,8 @@ // CHECK23-NEXT: [[ADD11:%.*]] = fadd double [[CONV10]], 1.000000e+00 // CHECK23-NEXT: [[CONV12:%.*]] = fptrunc double [[ADD11]] to float // CHECK23-NEXT: store float [[CONV12]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], i32 0, i32 1 -// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [5 x [10 x double]], ptr [[TMP3]], inrange i32 0, i32 1 +// CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x double], ptr [[ARRAYIDX13]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP19:%.*]] = load double, ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[ADD15:%.*]] = fadd double [[TMP19]], 1.000000e+00 // CHECK23-NEXT: store double [[ADD15]], ptr [[ARRAYIDX14]], align 8, !llvm.access.group [[ACC_GRP25]] @@ -12796,7 +12796,7 @@ // CHECK23-NEXT: [[ADD14:%.*]] = add nsw i32 [[CONV13]], 1 // CHECK23-NEXT: [[CONV15:%.*]] = trunc i32 [[ADD14]] to i8 // CHECK23-NEXT: store i8 [[CONV15]], ptr [[AAA_ADDR]], align 1, !llvm.access.group [[ACC_GRP28]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[ADD16:%.*]] = add nsw i32 [[TMP23]], 1 // CHECK23-NEXT: store i32 [[ADD16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] @@ -13089,7 +13089,7 @@ // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], 1 // CHECK23-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 // CHECK23-NEXT: store i16 [[CONV4]], ptr [[AA_ADDR]], align 2, !llvm.access.group [[ACC_GRP36]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 2 +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 2 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 // CHECK23-NEXT: store i32 [[ADD5]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] Index: clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_simd_collapse_codegen.cpp @@ -157,8 +157,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -235,10 +235,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -333,8 +333,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -410,9 +410,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -492,10 +492,10 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -509,8 +509,8 @@ // CHECK5-NEXT: store i32 123, ptr [[I]], align 4 // CHECK5-NEXT: store i32 456, ptr [[J]], align 4 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], inrange i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 // CHECK5-NEXT: ret i32 [[TMP9]] // @@ -562,9 +562,9 @@ // CHECK7-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -578,8 +578,8 @@ // CHECK7-NEXT: store i32 123, ptr [[I]], align 4 // CHECK7-NEXT: store i32 456, ptr [[J]], align 4 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], inrange i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 // CHECK7-NEXT: ret i32 [[TMP9]] // @@ -1044,10 +1044,10 @@ // CHECK9-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1535,9 +1535,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1753,10 +1753,10 @@ // CHECK13-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] +// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM6]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1951,9 +1951,9 @@ // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] // CHECK15-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_simd_dist_schedule_codegen.cpp @@ -278,7 +278,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -344,7 +344,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -429,7 +429,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -521,7 +521,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -718,7 +718,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -783,7 +783,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -867,7 +867,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -958,7 +958,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1046,7 +1046,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1076,7 +1076,7 @@ // CHECK5-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i64 0, i64 [[IDXPROM14]] +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i64 0, i64 [[IDXPROM14]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX15]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] // CHECK5: omp.body.continue16: @@ -1106,7 +1106,7 @@ // CHECK5-NEXT: [[A30:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], i64 0, i64 [[IDXPROM31]] +// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], inrange i64 0, i64 [[IDXPROM31]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK5: omp.body.continue33: @@ -1119,7 +1119,7 @@ // CHECK5: omp.inner.for.end36: // CHECK5-NEXT: store i32 123, ptr [[I24]], align 4 // CHECK5-NEXT: [[A37:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX38]], align 4 // CHECK5-NEXT: ret i32 [[TMP18]] // @@ -1170,7 +1170,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1199,7 +1199,7 @@ // CHECK7-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK7: omp.body.continue15: @@ -1228,7 +1228,7 @@ // CHECK7-NEXT: store i32 [[ADD28]], ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], inrange i32 0, i32 [[TMP16]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX30]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE31:%.*]] // CHECK7: omp.body.continue31: @@ -1241,7 +1241,7 @@ // CHECK7: omp.inner.for.end34: // CHECK7-NEXT: store i32 123, ptr [[I23]], align 4 // CHECK7-NEXT: [[A35:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX36]], align 4 // CHECK7-NEXT: ret i32 [[TMP18]] // @@ -2135,7 +2135,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2219,7 +2219,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2310,7 +2310,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3238,7 +3238,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3321,7 +3321,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3411,7 +3411,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3692,7 +3692,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3721,7 +3721,7 @@ // CHECK13-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM12]] +// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM12]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK13: omp.body.continue14: @@ -3750,7 +3750,7 @@ // CHECK13-NEXT: store i32 [[ADD27]], ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM28]] +// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM28]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX29]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE30:%.*]] // CHECK13: omp.body.continue30: @@ -4000,7 +4000,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -4028,7 +4028,7 @@ // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK15-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK15: omp.body.continue13: @@ -4056,7 +4056,7 @@ // CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] // CHECK15-NEXT: store i32 [[ADD26]], ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX27]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] // CHECK15: omp.body.continue28: Index: clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_simd_firstprivate_codegen.cpp @@ -454,11 +454,11 @@ // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] @@ -821,12 +821,12 @@ // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1276,10 +1276,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] @@ -1641,11 +1641,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1883,11 +1883,11 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -1952,12 +1952,12 @@ // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2204,10 +2204,10 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -2271,11 +2271,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP8]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP8]] // CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_simd_lastprivate_codegen.cpp @@ -773,12 +773,12 @@ // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1119,12 +1119,12 @@ // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1494,11 +1494,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1838,11 +1838,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP14:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP14]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2025,12 +2025,12 @@ // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2188,12 +2188,12 @@ // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK13-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2421,11 +2421,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2582,11 +2582,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp =================================================================== --- clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp +++ clang/test/OpenMP/target_teams_distribute_simd_private_codegen.cpp @@ -349,11 +349,11 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]] @@ -563,12 +563,12 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -897,10 +897,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]] @@ -1109,11 +1109,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1333,11 +1333,11 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -1429,12 +1429,12 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1710,10 +1710,10 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -1804,11 +1804,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/task_codegen.cpp =================================================================== --- clang/test/OpenMP/task_codegen.cpp +++ clang/test/OpenMP/task_codegen.cpp @@ -332,7 +332,7 @@ // CHECK1-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -370,7 +370,7 @@ // CHECK1-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -415,7 +415,7 @@ // CHECK1-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK1-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK1-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -579,7 +579,7 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK1-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK1-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK1-NEXT: ret i32 0 // @@ -1452,7 +1452,7 @@ // CHECK2-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK2-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -1490,7 +1490,7 @@ // CHECK2-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK2-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -1535,7 +1535,7 @@ // CHECK2-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK2-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK2-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK2-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK2-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -1699,7 +1699,7 @@ // CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK2-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK2-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK2-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK2-NEXT: ret i32 0 // @@ -2575,7 +2575,7 @@ // CHECK2-51-NEXT: [[TMP50:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK2-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP50]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR5]], i64 0, i64 0 -// CHECK2-51-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-51-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK2-51-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[ARRAYIDX6]] to i64 // CHECK2-51-NEXT: [[TMP54:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP52]], i64 0 // CHECK2-51-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP54]], i32 0, i32 0 @@ -2613,7 +2613,7 @@ // CHECK2-51-NEXT: [[TMP75:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[TMP0]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK2-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP75]], i32 0, i32 0 // CHECK2-51-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR13]], i64 0, i64 0 -// CHECK2-51-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK2-51-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK2-51-NEXT: [[TMP78:%.*]] = ptrtoint ptr [[ARRAYIDX14]] to i64 // CHECK2-51-NEXT: [[TMP79:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP77]], i64 0 // CHECK2-51-NEXT: [[TMP80:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP79]], i32 0, i32 0 @@ -2658,7 +2658,7 @@ // CHECK2-51-NEXT: store i64 4, ptr [[TMP105]], align 8 // CHECK2-51-NEXT: [[TMP106:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP103]], i32 0, i32 2 // CHECK2-51-NEXT: store i8 3, ptr [[TMP106]], align 8 -// CHECK2-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK2-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK2-51-NEXT: [[TMP107:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK2-51-NEXT: [[TMP108:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i64 1 // CHECK2-51-NEXT: [[TMP109:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP108]], i32 0, i32 0 @@ -2703,7 +2703,7 @@ // CHECK2-51-NEXT: store i64 4, ptr [[TMP133]], align 8 // CHECK2-51-NEXT: [[TMP134:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP131]], i32 0, i32 2 // CHECK2-51-NEXT: store i8 8, ptr [[TMP134]], align 8 -// CHECK2-51-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK2-51-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK2-51-NEXT: [[TMP135:%.*]] = ptrtoint ptr [[ARRAYIDX30]] to i64 // CHECK2-51-NEXT: [[TMP136:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i64 1 // CHECK2-51-NEXT: [[TMP137:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP136]], i32 0, i32 0 @@ -2867,7 +2867,7 @@ // CHECK2-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK2-51-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK2-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK2-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK2-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK2-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK2-51-NEXT: ret i32 0 // @@ -4189,7 +4189,7 @@ // CHECK3-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK3-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -4229,7 +4229,7 @@ // CHECK3-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK3-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK3-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -4276,7 +4276,7 @@ // CHECK3-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK3-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK3-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK3-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK3-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -4449,7 +4449,7 @@ // CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK3-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK3-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK3-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK3-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK3-NEXT: ret i32 0 // @@ -5205,7 +5205,7 @@ // CHECK4-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK4-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK4-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -5245,7 +5245,7 @@ // CHECK4-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 // CHECK4-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK4-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK4-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK4-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -5292,7 +5292,7 @@ // CHECK4-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK4-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK4-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK4-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK4-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK4-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK4-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -5465,7 +5465,7 @@ // CHECK4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK4-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK4-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK4-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK4-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK4-NEXT: ret i32 0 // @@ -6224,7 +6224,7 @@ // CHECK3-51-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK3-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK3-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK3-51-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK3-51-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK3-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -6264,7 +6264,7 @@ // CHECK3-51-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK3-51-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 // CHECK3-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK3-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK3-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK3-51-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK3-51-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK3-51-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -6311,7 +6311,7 @@ // CHECK3-51-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK3-51-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK3-51-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK3-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK3-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK3-51-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK3-51-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK3-51-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -6358,7 +6358,7 @@ // CHECK3-51-NEXT: store i64 4, ptr [[TMP132]], align 8 // CHECK3-51-NEXT: [[TMP133:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP130]], i32 0, i32 2 // CHECK3-51-NEXT: store i8 8, ptr [[TMP133]], align 8 -// CHECK3-51-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK3-51-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK3-51-NEXT: [[TMP134:%.*]] = ptrtoint ptr [[ARRAYIDX42]] to i64 // CHECK3-51-NEXT: [[TMP135:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP129]], i64 1 // CHECK3-51-NEXT: [[TMP136:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP135]], i32 0, i32 0 @@ -6531,7 +6531,7 @@ // CHECK3-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK3-51-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK3-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK3-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK3-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK3-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK3-51-NEXT: ret i32 0 // @@ -7739,7 +7739,7 @@ // CHECK4-51-NEXT: [[TMP49:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM10]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..6) // CHECK4-51-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_5:%.*]], ptr [[TMP49]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR11]], i64 0, i64 0 -// CHECK4-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-51-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK4-51-NEXT: [[TMP52:%.*]] = ptrtoint ptr [[ARRAYIDX12]] to i64 // CHECK4-51-NEXT: [[TMP53:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP51]], i64 0 // CHECK4-51-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP53]], i32 0, i32 0 @@ -7779,7 +7779,7 @@ // CHECK4-51-NEXT: [[TMP74:%.*]] = call ptr @__kmpc_omp_task_alloc(ptr @[[GLOB1]], i32 [[OMP_GLOBAL_THREAD_NUM20]], i32 0, i64 40, i64 1, ptr @.omp_task_entry..8) // CHECK4-51-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES_7:%.*]], ptr [[TMP74]], i32 0, i32 0 // CHECK4-51-NEXT: [[TMP76:%.*]] = getelementptr inbounds [2 x %struct.kmp_depend_info], ptr [[DOTDEP_ARR_ADDR21]], i64 0, i64 0 -// CHECK4-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 0 +// CHECK4-51-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 0 // CHECK4-51-NEXT: [[TMP77:%.*]] = ptrtoint ptr [[ARRAYIDX22]] to i64 // CHECK4-51-NEXT: [[TMP78:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP76]], i64 0 // CHECK4-51-NEXT: [[TMP79:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP78]], i32 0, i32 0 @@ -7826,7 +7826,7 @@ // CHECK4-51-NEXT: store i64 4, ptr [[TMP104]], align 8 // CHECK4-51-NEXT: [[TMP105:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP102]], i32 0, i32 2 // CHECK4-51-NEXT: store i8 3, ptr [[TMP105]], align 8 -// CHECK4-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], i64 0, i64 1 +// CHECK4-51-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S]], inrange i64 0, i64 1 // CHECK4-51-NEXT: [[TMP106:%.*]] = ptrtoint ptr [[ARRAYIDX32]] to i64 // CHECK4-51-NEXT: [[TMP107:%.*]] = getelementptr [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP101]], i64 1 // CHECK4-51-NEXT: [[TMP108:%.*]] = getelementptr inbounds [[STRUCT_KMP_DEPEND_INFO]], ptr [[TMP107]], i32 0, i32 0 @@ -7999,7 +7999,7 @@ // CHECK4-51-NEXT: [[TMP8:%.*]] = load ptr, ptr [[__CONTEXT_ADDR_I]], align 8, !noalias !22 // CHECK4-51-NEXT: store i32 15, ptr @a, align 4, !noalias !22 // CHECK4-51-NEXT: [[TMP9:%.*]] = load ptr, ptr [[TMP8]], align 8 -// CHECK4-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], i64 0, i64 1 +// CHECK4-51-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[TMP9]], inrange i64 0, i64 1 // CHECK4-51-NEXT: store i32 10, ptr [[ARRAYIDX_I]], align 4 // CHECK4-51-NEXT: ret i32 0 // Index: clang/test/OpenMP/taskloop_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/taskloop_reduction_codegen.cpp +++ clang/test/OpenMP/taskloop_reduction_codegen.cpp @@ -83,9 +83,9 @@ // CHECK-DAG: store ptr @[[RED_COMB1:.+]], ptr [[TMP25]], // CHECK-DAG: [[TMP26:%.*]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK-DAG: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 4, i1 false) -// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 0 +// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 0 // CHECK-DAG: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, % -// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 [[LB_ADD_LEN]] +// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 [[LB_ADD_LEN]] // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], // CHECK-DAG: [[TMP28]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_4:%.+]], i32 0, i32 0 // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], Index: clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp =================================================================== --- clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp +++ clang/test/OpenMP/taskloop_simd_reduction_codegen.cpp @@ -80,9 +80,9 @@ // CHECK-DAG: store ptr @[[RED_COMB1:.+]], ptr [[TMP25]], // CHECK-DAG: [[TMP26:%.*]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_]], i32 0, i32 6 // CHECK-DAG: call void @llvm.memset.p0.i64(ptr align 8 [[TMP26]], i8 0, i64 4, i1 false) -// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 0 +// CHECK-DAG: [[ARRAYIDX5:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 0 // CHECK-DAG: [[LB_ADD_LEN:%.*]] = add nsw i64 -1, % -// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], i64 0, i64 [[LB_ADD_LEN]] +// CHECK-DAG: [[ARRAYIDX6:%.*]] = getelementptr inbounds [100 x %struct.S], ptr [[C]], inrange i64 0, i64 [[LB_ADD_LEN]] // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], // CHECK-DAG: [[TMP28]] = getelementptr inbounds %struct.kmp_taskred_input_t, ptr [[DOTRD_INPUT_GEP_4:%.+]], i32 0, i32 0 // CHECK-DAG: store ptr [[ARRAYIDX5]], ptr [[TMP28:%[^,]+]], Index: clang/test/OpenMP/teams_distribute_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_codegen.cpp +++ clang/test/OpenMP/teams_distribute_codegen.cpp @@ -441,7 +441,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -545,7 +545,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -838,7 +838,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -941,7 +941,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1464,7 +1464,7 @@ // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i64 0, i64 0 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i64 0, i64 0 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: ret i32 [[TMP20]] // @@ -1530,7 +1530,7 @@ // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -1616,7 +1616,7 @@ // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i32 0, i32 0 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i32 0, i32 0 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: ret i32 [[TMP20]] // @@ -1681,7 +1681,7 @@ // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -2074,7 +2074,7 @@ // CHECK25-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK25-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK25-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: @@ -2465,7 +2465,7 @@ // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK27-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_collapse_codegen.cpp +++ clang/test/OpenMP/teams_distribute_collapse_codegen.cpp @@ -160,8 +160,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -238,10 +238,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -328,8 +328,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -405,9 +405,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -867,10 +867,10 @@ // CHECK9-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1326,9 +1326,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp +++ clang/test/OpenMP/teams_distribute_dist_schedule_codegen.cpp @@ -287,7 +287,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -353,7 +353,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -431,7 +431,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -516,7 +516,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -706,7 +706,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -771,7 +771,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -848,7 +848,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -932,7 +932,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1798,7 +1798,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1875,7 +1875,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1959,7 +1959,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2823,7 +2823,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2899,7 +2899,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2982,7 +2982,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_firstprivate_codegen.cpp @@ -457,11 +457,11 @@ // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -819,12 +819,12 @@ // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1267,10 +1267,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1627,11 +1627,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_lastprivate_codegen.cpp @@ -713,12 +713,12 @@ // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1051,12 +1051,12 @@ // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 8 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1415,11 +1415,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1751,11 +1751,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP15]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_codegen.cpp @@ -537,7 +537,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 @@ -754,7 +754,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1139,7 +1139,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4 @@ -1351,7 +1351,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2072,7 +2072,7 @@ // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i64 0, i64 0 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i64 0, i64 0 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: ret i32 [[TMP20]] // @@ -2211,7 +2211,7 @@ // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -2297,7 +2297,7 @@ // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i32 0, i32 0 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i32 0, i32 0 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: ret i32 [[TMP20]] // @@ -2431,7 +2431,7 @@ // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -2996,7 +2996,7 @@ // CHECK25-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK25-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK25-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: @@ -3551,7 +3551,7 @@ // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK27-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK27-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_collapse_codegen.cpp @@ -165,8 +165,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -318,10 +318,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -408,8 +408,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -556,9 +556,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1213,10 +1213,10 @@ // CHECK9-NEXT: store i32 [[ADD7]], ptr [[J]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1867,9 +1867,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4 -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_copyin_codegen.cpp @@ -301,7 +301,7 @@ // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -524,7 +524,7 @@ // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -758,7 +758,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -976,7 +976,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1162,7 +1162,7 @@ // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP1]], align 4 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[CLASS_ANON_0]], ptr [[REF_TMP]], i32 0, i32 0 // CHECK9-NEXT: store ptr [[TMP0]], ptr [[TMP14]], align 8 Index: clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_dist_schedule_codegen.cpp @@ -299,7 +299,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -438,7 +438,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -589,7 +589,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -760,7 +760,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -940,7 +940,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -1074,7 +1074,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1220,7 +1220,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1386,7 +1386,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2657,7 +2657,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2807,7 +2807,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2995,7 +2995,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -4248,7 +4248,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4393,7 +4393,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4576,7 +4576,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_firstprivate_codegen.cpp @@ -656,11 +656,11 @@ // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false) // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -1128,12 +1128,12 @@ // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1722,10 +1722,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4 @@ -2188,11 +2188,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_lastprivate_codegen.cpp @@ -1109,12 +1109,12 @@ // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1589,12 +1589,12 @@ // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false) // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2097,11 +2097,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2571,11 +2571,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4 // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4 // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4 -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false) // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_private_codegen.cpp @@ -473,11 +473,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -784,12 +784,12 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1208,10 +1208,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1513,11 +1513,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_schedule_codegen.cpp @@ -458,7 +458,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK1: omp_offload.cont33: // CHECK1-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP100]] // @@ -597,7 +597,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -748,7 +748,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -910,7 +910,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1068,7 +1068,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1217,7 +1217,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1492,7 +1492,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK3: omp_offload.cont33: // CHECK3-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP100]] // @@ -1626,7 +1626,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1772,7 +1772,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1927,7 +1927,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2080,7 +2080,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2224,7 +2224,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2499,7 +2499,7 @@ // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK5: omp_offload.cont33: // CHECK5-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: ret i32 [[TMP100]] // @@ -2638,7 +2638,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2789,7 +2789,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2951,7 +2951,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3109,7 +3109,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3258,7 +3258,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3533,7 +3533,7 @@ // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK7: omp_offload.cont33: // CHECK7-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: ret i32 [[TMP100]] // @@ -3667,7 +3667,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -3813,7 +3813,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -3968,7 +3968,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4 -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4121,7 +4121,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -4265,7 +4265,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -6241,7 +6241,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6391,7 +6391,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6570,7 +6570,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6727,7 +6727,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -6893,7 +6893,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -8843,7 +8843,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -8988,7 +8988,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9160,7 +9160,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9312,7 +9312,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -9473,7 +9473,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK15-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -11449,7 +11449,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -11599,7 +11599,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -11778,7 +11778,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -11935,7 +11935,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -12101,7 +12101,7 @@ // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -14051,7 +14051,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14196,7 +14196,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14368,7 +14368,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14520,7 +14520,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -14681,7 +14681,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_codegen.cpp @@ -566,7 +566,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -811,7 +811,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I5]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[I5]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1237,7 +1237,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1477,7 +1477,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I4]], align 4 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[I4]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], i32 0, i32 [[TMP22]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], inrange i32 0, i32 [[TMP22]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1583,7 +1583,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1635,7 +1635,7 @@ // CHECK5-NEXT: store i32 [[ADD30]], ptr [[I24]], align 4 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I24]], align 4 // CHECK5-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i64 0, i64 [[IDXPROM31]] +// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i64 0, i64 [[IDXPROM31]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK5: omp.body.continue33: @@ -1717,7 +1717,7 @@ // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i32 0, i32 [[TMP9]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i32 0, i32 [[TMP9]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1768,7 +1768,7 @@ // CHECK7-NEXT: [[ADD30:%.*]] = add nsw i32 0, [[MUL29]] // CHECK7-NEXT: store i32 [[ADD30]], ptr [[I24]], align 4 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[I24]], align 4 -// CHECK7-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i32 0, i32 [[TMP21]] +// CHECK7-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i32 0, i32 [[TMP21]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX31]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] // CHECK7: omp.body.continue32: @@ -2775,7 +2775,7 @@ // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i64 0, i64 0 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i64 0, i64 0 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: ret i32 [[TMP25]] // @@ -2940,7 +2940,7 @@ // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP1]], i32 0, i32 0 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I2]], align 4 // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A5]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A5]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -3050,7 +3050,7 @@ // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i32 0, i32 0 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i32 0, i32 0 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: ret i32 [[TMP25]] // @@ -3210,7 +3210,7 @@ // CHECK19-NEXT: store i32 [[ADD]], ptr [[I1]], align 4 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP1]], i32 0, i32 0 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I1]], align 4 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A4]], i32 0, i32 [[TMP13]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A4]], inrange i32 0, i32 [[TMP13]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -3292,7 +3292,7 @@ // CHECK21-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, ptr [[I2]], align 4 // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A4]], i64 0, i64 [[IDXPROM]] +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A4]], inrange i64 0, i64 [[IDXPROM]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: @@ -3305,7 +3305,7 @@ // CHECK21: omp.inner.for.end: // CHECK21-NEXT: store i32 123, ptr [[I]], align 4 // CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], ptr [[A6]], i64 0, i64 0 +// CHECK21-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], ptr [[A6]], inrange i64 0, i64 0 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4 // CHECK21-NEXT: ret i32 [[TMP7]] // @@ -3354,7 +3354,7 @@ // CHECK23-NEXT: store i32 [[ADD]], ptr [[I2]], align 4 // CHECK23-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, ptr [[I2]], align 4 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A4]], i32 0, i32 [[TMP5]] +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A4]], inrange i32 0, i32 [[TMP5]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: @@ -3367,7 +3367,7 @@ // CHECK23: omp.inner.for.end: // CHECK23-NEXT: store i32 123, ptr [[I]], align 4 // CHECK23-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], ptr [[A6]], i32 0, i32 0 +// CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [123 x i32], ptr [[A6]], inrange i32 0, i32 0 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX7]], align 4 // CHECK23-NEXT: ret i32 [[TMP7]] // @@ -3978,7 +3978,7 @@ // CHECK25-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK25-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK25-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: @@ -4605,7 +4605,7 @@ // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK27-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK27-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK27-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: @@ -4759,7 +4759,7 @@ // CHECK29-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK29-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK29-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK29: omp.body.continue: @@ -4894,7 +4894,7 @@ // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK31-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK31-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK31-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK31: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_collapse_codegen.cpp @@ -170,8 +170,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -331,10 +331,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -429,8 +429,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -585,9 +585,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -667,10 +667,10 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -684,8 +684,8 @@ // CHECK5-NEXT: store i32 123, ptr [[I]], align 4 // CHECK5-NEXT: store i32 456, ptr [[J]], align 4 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], inrange i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 // CHECK5-NEXT: ret i32 [[TMP9]] // @@ -737,9 +737,9 @@ // CHECK7-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -753,8 +753,8 @@ // CHECK7-NEXT: store i32 123, ptr [[I]], align 4 // CHECK7-NEXT: store i32 456, ptr [[J]], align 4 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], inrange i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 // CHECK7-NEXT: ret i32 [[TMP9]] // @@ -1434,10 +1434,10 @@ // CHECK9-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2140,9 +2140,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2358,10 +2358,10 @@ // CHECK13-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] +// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM6]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2556,9 +2556,9 @@ // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] // CHECK15-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_dist_schedule_codegen.cpp @@ -302,7 +302,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -448,7 +448,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -613,7 +613,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -798,7 +798,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -985,7 +985,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -1126,7 +1126,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1286,7 +1286,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1466,7 +1466,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1544,7 +1544,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1574,7 +1574,7 @@ // CHECK5-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i64 0, i64 [[IDXPROM14]] +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i64 0, i64 [[IDXPROM14]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX15]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] // CHECK5: omp.body.continue16: @@ -1604,7 +1604,7 @@ // CHECK5-NEXT: [[A30:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], i64 0, i64 [[IDXPROM31]] +// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], inrange i64 0, i64 [[IDXPROM31]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK5: omp.body.continue33: @@ -1617,7 +1617,7 @@ // CHECK5: omp.inner.for.end36: // CHECK5-NEXT: store i32 123, ptr [[I24]], align 4 // CHECK5-NEXT: [[A37:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX38]], align 4 // CHECK5-NEXT: ret i32 [[TMP18]] // @@ -1668,7 +1668,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1697,7 +1697,7 @@ // CHECK7-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK7: omp.body.continue15: @@ -1726,7 +1726,7 @@ // CHECK7-NEXT: store i32 [[ADD28]], ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], inrange i32 0, i32 [[TMP16]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX30]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE31:%.*]] // CHECK7: omp.body.continue31: @@ -1739,7 +1739,7 @@ // CHECK7: omp.inner.for.end34: // CHECK7-NEXT: store i32 123, ptr [[I23]], align 4 // CHECK7-NEXT: [[A35:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX36]], align 4 // CHECK7-NEXT: ret i32 [[TMP18]] // @@ -3070,7 +3070,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3234,7 +3234,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3436,7 +3436,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -4775,7 +4775,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP34]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP34]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4934,7 +4934,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP40]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP40]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -5131,7 +5131,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP46]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP46]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -5407,7 +5407,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -5436,7 +5436,7 @@ // CHECK13-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM12]] +// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM12]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK13: omp.body.continue14: @@ -5467,7 +5467,7 @@ // CHECK13-NEXT: store i32 [[ADD27]], ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP17:%.*]] = load i32, ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM28]] +// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM28]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX29]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE30:%.*]] // CHECK13: omp.body.continue30: @@ -5722,7 +5722,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -5750,7 +5750,7 @@ // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK15-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK15: omp.body.continue13: @@ -5780,7 +5780,7 @@ // CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] // CHECK15-NEXT: store i32 [[ADD26]], ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP17:%.*]] = load i32, ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP17]] +// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP17]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX27]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] // CHECK15: omp.body.continue28: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_firstprivate_codegen.cpp @@ -666,11 +666,11 @@ // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM8]] +// CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM8]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[VAR5]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP9]] @@ -1152,12 +1152,12 @@ // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP8]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM10]] +// CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM10]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1760,10 +1760,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP15]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP15]] // CHECK3-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -2240,11 +2240,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP18]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP18]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -2467,11 +2467,11 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -2539,12 +2539,12 @@ // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2791,10 +2791,10 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -2861,11 +2861,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK7-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP1]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_lastprivate_codegen.cpp @@ -1189,12 +1189,12 @@ // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i32 [[TMP19]] to i64 -// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM10]] +// CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM10]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX11]], ptr align 4 [[TMP18]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1683,12 +1683,12 @@ // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP17]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2205,11 +2205,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP18:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[TMP19:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP19]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP19]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP18]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2693,11 +2693,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP17:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: [[TMP18:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP18]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP18]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP17]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2883,12 +2883,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3049,12 +3049,12 @@ // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP11]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3285,11 +3285,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3449,11 +3449,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 [[TMP9]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP12]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP12]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP11]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_private_codegen.cpp @@ -482,11 +482,11 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP9]] @@ -807,12 +807,12 @@ // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP3]], align 8, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM5]] +// CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM5]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[TMP12]], i64 4, i1 false), !llvm.access.group [[ACC_GRP17]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1245,10 +1245,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP10]] @@ -1564,11 +1564,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 [[TMP10]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP12:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP12]], i32 4, i1 false), !llvm.access.group [[ACC_GRP18]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1788,11 +1788,11 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -1884,12 +1884,12 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2165,10 +2165,10 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -2259,11 +2259,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp +++ clang/test/OpenMP/teams_distribute_parallel_for_simd_schedule_codegen.cpp @@ -468,7 +468,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK1: omp_offload.cont33: // CHECK1-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP100]] // @@ -614,7 +614,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -779,7 +779,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -955,7 +955,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1127,7 +1127,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1290,7 +1290,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1572,7 +1572,7 @@ // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK2: omp_offload.cont33: // CHECK2-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i64 0, i64 0 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i64 0, i64 0 // CHECK2-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK2-NEXT: ret i32 [[TMP100]] // @@ -1718,7 +1718,7 @@ // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -1883,7 +1883,7 @@ // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP20]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -2059,7 +2059,7 @@ // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -2231,7 +2231,7 @@ // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -2394,7 +2394,7 @@ // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK2-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP38]] // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK2: omp.body.continue: @@ -2676,7 +2676,7 @@ // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK5: omp_offload.cont33: // CHECK5-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK5-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK5-NEXT: ret i32 [[TMP100]] // @@ -2817,7 +2817,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2977,7 +2977,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3146,7 +3146,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3313,7 +3313,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3471,7 +3471,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -3753,7 +3753,7 @@ // CHECK6-NEXT: br label [[OMP_OFFLOAD_CONT33]] // CHECK6: omp_offload.cont33: // CHECK6-NEXT: [[A34:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], i32 0, i32 0 +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A34]], inrange i32 0, i32 0 // CHECK6-NEXT: [[TMP100:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK6-NEXT: ret i32 [[TMP100]] // @@ -3894,7 +3894,7 @@ // CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK6-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: @@ -4054,7 +4054,7 @@ // CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK6-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: @@ -4223,7 +4223,7 @@ // CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP15]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP15]] // CHECK6-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: @@ -4390,7 +4390,7 @@ // CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP33]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK6-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: @@ -4548,7 +4548,7 @@ // CHECK6-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP39]] -// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP12]] +// CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP12]] // CHECK6-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP39]] // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK6: omp.body.continue: @@ -4637,7 +4637,7 @@ // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -4667,7 +4667,7 @@ // CHECK9-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i64 0, i64 [[IDXPROM14]] +// CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i64 0, i64 [[IDXPROM14]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX15]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] // CHECK9: omp.body.continue16: @@ -4697,7 +4697,7 @@ // CHECK9-NEXT: [[A30:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], i64 0, i64 [[IDXPROM31]] +// CHECK9-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], inrange i64 0, i64 [[IDXPROM31]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK9: omp.body.continue33: @@ -4727,7 +4727,7 @@ // CHECK9-NEXT: [[A47:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, ptr [[I41]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK9-NEXT: [[IDXPROM48:%.*]] = sext i32 [[TMP22]] to i64 -// CHECK9-NEXT: [[ARRAYIDX49:%.*]] = getelementptr inbounds [123 x i32], ptr [[A47]], i64 0, i64 [[IDXPROM48]] +// CHECK9-NEXT: [[ARRAYIDX49:%.*]] = getelementptr inbounds [123 x i32], ptr [[A47]], inrange i64 0, i64 [[IDXPROM48]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX49]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE50:%.*]] // CHECK9: omp.body.continue50: @@ -4757,7 +4757,7 @@ // CHECK9-NEXT: [[A64:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK9-NEXT: [[TMP28:%.*]] = load i32, ptr [[I58]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: [[IDXPROM65:%.*]] = sext i32 [[TMP28]] to i64 -// CHECK9-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds [123 x i32], ptr [[A64]], i64 0, i64 [[IDXPROM65]] +// CHECK9-NEXT: [[ARRAYIDX66:%.*]] = getelementptr inbounds [123 x i32], ptr [[A64]], inrange i64 0, i64 [[IDXPROM65]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX66]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE67:%.*]] // CHECK9: omp.body.continue67: @@ -4770,7 +4770,7 @@ // CHECK9: omp.inner.for.end70: // CHECK9-NEXT: store i32 123, ptr [[I58]], align 4 // CHECK9-NEXT: [[A71:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [123 x i32], ptr [[A71]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX72:%.*]] = getelementptr inbounds [123 x i32], ptr [[A71]], inrange i64 0, i64 0 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX72]], align 4 // CHECK9-NEXT: ret i32 [[TMP30]] // @@ -4831,7 +4831,7 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -4860,7 +4860,7 @@ // CHECK11-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i32 0, i32 [[TMP10]] +// CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i32 0, i32 [[TMP10]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK11: omp.body.continue15: @@ -4889,7 +4889,7 @@ // CHECK11-NEXT: store i32 [[ADD28]], ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK11-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX30]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE31:%.*]] // CHECK11: omp.body.continue31: @@ -4918,7 +4918,7 @@ // CHECK11-NEXT: store i32 [[ADD44]], ptr [[I39]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK11-NEXT: [[A45:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP22:%.*]] = load i32, ptr [[I39]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK11-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds [123 x i32], ptr [[A45]], i32 0, i32 [[TMP22]] +// CHECK11-NEXT: [[ARRAYIDX46:%.*]] = getelementptr inbounds [123 x i32], ptr [[A45]], inrange i32 0, i32 [[TMP22]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX46]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE47:%.*]] // CHECK11: omp.body.continue47: @@ -4947,7 +4947,7 @@ // CHECK11-NEXT: store i32 [[ADD60]], ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: [[A61:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK11-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [123 x i32], ptr [[A61]], i32 0, i32 [[TMP28]] +// CHECK11-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [123 x i32], ptr [[A61]], inrange i32 0, i32 [[TMP28]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX62]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE63:%.*]] // CHECK11: omp.body.continue63: @@ -4960,7 +4960,7 @@ // CHECK11: omp.inner.for.end66: // CHECK11-NEXT: store i32 123, ptr [[I55]], align 4 // CHECK11-NEXT: [[A67:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK11-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds [123 x i32], ptr [[A67]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX68:%.*]] = getelementptr inbounds [123 x i32], ptr [[A67]], inrange i32 0, i32 0 // CHECK11-NEXT: [[TMP30:%.*]] = load i32, ptr [[ARRAYIDX68]], align 4 // CHECK11-NEXT: ret i32 [[TMP30]] // @@ -7043,7 +7043,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7207,7 +7207,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7400,7 +7400,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7571,7 +7571,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK13-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -7751,7 +7751,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK13-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -9861,7 +9861,7 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK14-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP49]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -10025,7 +10025,7 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK14-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP55]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -10218,7 +10218,7 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK14-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP61]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -10389,7 +10389,7 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK14-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP67]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -10569,7 +10569,7 @@ // CHECK14-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK14-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK14-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK14-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK14-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP73]] // CHECK14-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK14: omp.body.continue: @@ -12653,7 +12653,7 @@ // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -12812,7 +12812,7 @@ // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK17-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -12998,7 +12998,7 @@ // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK17-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -13164,7 +13164,7 @@ // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK17-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -13339,7 +13339,7 @@ // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK17-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK17-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK17-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -15423,7 +15423,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP50]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP50]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -15582,7 +15582,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK19-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP56]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP56]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -15768,7 +15768,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK19-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP62]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP16]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP62]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -15934,7 +15934,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK19-NEXT: [[TMP12:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP68]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP12]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP12]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP68]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -16109,7 +16109,7 @@ // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK19-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK19-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP74]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP13]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP13]] // CHECK19-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP74]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -16514,7 +16514,7 @@ // CHECK21-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: @@ -16543,7 +16543,7 @@ // CHECK21-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM12]] +// CHECK21-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM12]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK21: omp.body.continue14: @@ -16574,7 +16574,7 @@ // CHECK21-NEXT: store i32 [[ADD27]], ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK21-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM28]] +// CHECK21-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM28]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX29]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE30:%.*]] // CHECK21: omp.body.continue30: @@ -16603,7 +16603,7 @@ // CHECK21-NEXT: store i32 [[ADD43]], ptr [[I38]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[TMP23:%.*]] = load i32, ptr [[I38]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: [[IDXPROM44:%.*]] = sext i32 [[TMP23]] to i64 -// CHECK21-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM44]] +// CHECK21-NEXT: [[ARRAYIDX45:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM44]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX45]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE46:%.*]] // CHECK21: omp.body.continue46: @@ -16634,7 +16634,7 @@ // CHECK21-NEXT: store i32 [[ADD60]], ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[TMP30:%.*]] = load i32, ptr [[I55]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: [[IDXPROM61:%.*]] = sext i32 [[TMP30]] to i64 -// CHECK21-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM61]] +// CHECK21-NEXT: [[ARRAYIDX62:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM61]] // CHECK21-NEXT: store i32 0, ptr [[ARRAYIDX62]], align 4, !llvm.access.group [[ACC_GRP30]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE63:%.*]] // CHECK21: omp.body.continue63: @@ -17015,7 +17015,7 @@ // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK23-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: @@ -17043,7 +17043,7 @@ // CHECK23-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK23-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK23-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK23-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK23: omp.body.continue13: @@ -17073,7 +17073,7 @@ // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] // CHECK23-NEXT: store i32 [[ADD26]], ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK23-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP17]] +// CHECK23-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP17]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX27]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] // CHECK23: omp.body.continue28: @@ -17101,7 +17101,7 @@ // CHECK23-NEXT: [[ADD41:%.*]] = add nsw i32 0, [[MUL40]] // CHECK23-NEXT: store i32 [[ADD41]], ptr [[I36]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: [[TMP23:%.*]] = load i32, ptr [[I36]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK23-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP23]] +// CHECK23-NEXT: [[ARRAYIDX42:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP23]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX42]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE43:%.*]] // CHECK23: omp.body.continue43: @@ -17131,7 +17131,7 @@ // CHECK23-NEXT: [[ADD57:%.*]] = add nsw i32 0, [[MUL56]] // CHECK23-NEXT: store i32 [[ADD57]], ptr [[I52]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: [[TMP30:%.*]] = load i32, ptr [[I52]], align 4, !llvm.access.group [[ACC_GRP31]] -// CHECK23-NEXT: [[ARRAYIDX58:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP30]] +// CHECK23-NEXT: [[ARRAYIDX58:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP30]] // CHECK23-NEXT: store i32 0, ptr [[ARRAYIDX58]], align 4, !llvm.access.group [[ACC_GRP31]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE59:%.*]] // CHECK23: omp.body.continue59: Index: clang/test/OpenMP/teams_distribute_private_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_private_codegen.cpp +++ clang/test/OpenMP/teams_distribute_private_codegen.cpp @@ -352,11 +352,11 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -559,12 +559,12 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false) // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -886,10 +886,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4 @@ -1091,11 +1091,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false) // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_simd_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_simd_codegen.cpp +++ clang/test/OpenMP/teams_distribute_simd_codegen.cpp @@ -493,7 +493,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -609,7 +609,7 @@ // CHECK1-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -930,7 +930,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], i32 0, i32 [[TMP17]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP2]], inrange i32 0, i32 [[TMP17]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1045,7 +1045,7 @@ // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr [[TMP1]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1148,7 +1148,7 @@ // CHECK5-NEXT: store i32 [[ADD]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1197,7 +1197,7 @@ // CHECK5-NEXT: store i32 [[ADD30]], ptr [[I25]], align 4 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, ptr [[I25]], align 4 // CHECK5-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP21]] to i64 -// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i64 0, i64 [[IDXPROM31]] +// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i64 0, i64 [[IDXPROM31]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK5: omp.body.continue33: @@ -1282,7 +1282,7 @@ // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK7-NEXT: store i32 [[ADD]], ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I5]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1330,7 +1330,7 @@ // CHECK7-NEXT: [[ADD30:%.*]] = add nsw i32 0, [[MUL29]] // CHECK7-NEXT: store i32 [[ADD30]], ptr [[I25]], align 4 // CHECK7-NEXT: [[TMP21:%.*]] = load i32, ptr [[I25]], align 4 -// CHECK7-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [100 x i32], ptr @a, i32 0, i32 [[TMP21]] +// CHECK7-NEXT: [[ARRAYIDX31:%.*]] = getelementptr inbounds [100 x i32], ptr @a, inrange i32 0, i32 [[TMP21]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX31]], align 4 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE32:%.*]] // CHECK7: omp.body.continue32: @@ -2047,7 +2047,7 @@ // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK17: omp_offload.cont: // CHECK17-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i64 0, i64 0 +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i64 0, i64 0 // CHECK17-NEXT: [[TMP33:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK17-NEXT: ret i32 [[TMP33]] // @@ -2116,7 +2116,7 @@ // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK17-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK17: omp.body.continue: @@ -2232,7 +2232,7 @@ // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK19: omp_offload.cont: // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i32 0, i32 0 +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i32 0, i32 0 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK19-NEXT: ret i32 [[TMP33]] // @@ -2300,7 +2300,7 @@ // CHECK19-NEXT: [[CONV:%.*]] = fptosi float [[TMP9]] to i32 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK19-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK19: omp.body.continue: @@ -2416,7 +2416,7 @@ // CHECK21-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK21: omp_offload.cont: // CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i64 0, i64 0 +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i64 0, i64 0 // CHECK21-NEXT: [[TMP33:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK21-NEXT: ret i32 [[TMP33]] // @@ -2503,7 +2503,7 @@ // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK21-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK21: omp.body.continue: @@ -2533,7 +2533,7 @@ // CHECK21-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 // CHECK21-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [123 x i32], ptr [[A10]], i64 0, i64 [[IDXPROM11]] +// CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [123 x i32], ptr [[A10]], inrange i64 0, i64 [[IDXPROM11]] // CHECK21-NEXT: store i32 [[CONV9]], ptr [[ARRAYIDX12]], align 4 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK21: omp.body.continue13: @@ -2651,7 +2651,7 @@ // CHECK23-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK23: omp_offload.cont: // CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], i32 0, i32 0 +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A2]], inrange i32 0, i32 0 // CHECK23-NEXT: [[TMP33:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK23-NEXT: ret i32 [[TMP33]] // @@ -2737,7 +2737,7 @@ // CHECK23-NEXT: [[CONV:%.*]] = fptosi float [[TMP10]] to i32 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK23-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK23: omp.body.continue: @@ -2766,7 +2766,7 @@ // CHECK23-NEXT: [[CONV9:%.*]] = fptosi float [[TMP16]] to i32 // CHECK23-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[TMP0]], i32 0, i32 0 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4 -// CHECK23-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x i32], ptr [[A10]], i32 0, i32 [[TMP17]] +// CHECK23-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x i32], ptr [[A10]], inrange i32 0, i32 [[TMP17]] // CHECK23-NEXT: store i32 [[CONV9]], ptr [[ARRAYIDX11]], align 4 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE12:%.*]] // CHECK23: omp.body.continue12: @@ -2839,7 +2839,7 @@ // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK25-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK25-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK25-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK25-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK25: omp.body.continue: @@ -2852,7 +2852,7 @@ // CHECK25: omp.inner.for.end: // CHECK25-NEXT: store i32 123, ptr [[I]], align 4 // CHECK25-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK25-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [123 x i32], ptr [[A3]], i64 0, i64 0 +// CHECK25-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [123 x i32], ptr [[A3]], inrange i64 0, i64 0 // CHECK25-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK25-NEXT: ret i32 [[TMP7]] // @@ -2896,7 +2896,7 @@ // CHECK27-NEXT: [[CONV:%.*]] = fptosi float [[TMP4]] to i32 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP5]] +// CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP5]] // CHECK27-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK27-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK27: omp.body.continue: @@ -2909,7 +2909,7 @@ // CHECK27: omp.inner.for.end: // CHECK27-NEXT: store i32 123, ptr [[I]], align 4 // CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK27-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [123 x i32], ptr [[A3]], i32 0, i32 0 +// CHECK27-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [123 x i32], ptr [[A3]], inrange i32 0, i32 0 // CHECK27-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK27-NEXT: ret i32 [[TMP7]] // @@ -2964,7 +2964,7 @@ // CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK29-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK29-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK29-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK29: omp.body.continue: @@ -2994,7 +2994,7 @@ // CHECK29-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK29-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 // CHECK29-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK29-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A12]], i64 0, i64 [[IDXPROM13]] +// CHECK29-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A12]], inrange i64 0, i64 [[IDXPROM13]] // CHECK29-NEXT: store i32 [[CONV11]], ptr [[ARRAYIDX14]], align 4 // CHECK29-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK29: omp.body.continue15: @@ -3009,7 +3009,7 @@ // CHECK29: omp_if.end: // CHECK29-NEXT: store i32 123, ptr [[I]], align 4 // CHECK29-NEXT: [[A19:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [123 x i32], ptr [[A19]], i64 0, i64 0 +// CHECK29-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [123 x i32], ptr [[A19]], inrange i64 0, i64 0 // CHECK29-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX20]], align 4 // CHECK29-NEXT: ret i32 [[TMP15]] // @@ -3063,7 +3063,7 @@ // CHECK31-NEXT: [[CONV:%.*]] = fptosi float [[TMP6]] to i32 // CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK31-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP7]] +// CHECK31-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP7]] // CHECK31-NEXT: store i32 [[CONV]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK31: omp.body.continue: @@ -3092,7 +3092,7 @@ // CHECK31-NEXT: [[CONV11:%.*]] = fptosi float [[TMP12]] to i32 // CHECK31-NEXT: [[A12:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK31-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4 -// CHECK31-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [123 x i32], ptr [[A12]], i32 0, i32 [[TMP13]] +// CHECK31-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [123 x i32], ptr [[A12]], inrange i32 0, i32 [[TMP13]] // CHECK31-NEXT: store i32 [[CONV11]], ptr [[ARRAYIDX13]], align 4 // CHECK31-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK31: omp.body.continue14: @@ -3107,7 +3107,7 @@ // CHECK31: omp_if.end: // CHECK31-NEXT: store i32 123, ptr [[I]], align 4 // CHECK31-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK31-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK31-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK31-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX19]], align 4 // CHECK31-NEXT: ret i32 [[TMP15]] // @@ -3491,7 +3491,7 @@ // CHECK33-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK33-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK33-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK33-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK33-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK33: omp.body.continue: @@ -3899,7 +3899,7 @@ // CHECK35-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK35-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK35-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK35-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK35-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK35-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK35: omp.body.continue: @@ -4366,7 +4366,7 @@ // CHECK37-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK37-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK37-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK37-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK37-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK37: omp.body.continue: @@ -4830,7 +4830,7 @@ // CHECK39-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK39-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP14]] -// CHECK39-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK39-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK39-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP14]] // CHECK39-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK39: omp.body.continue: @@ -4978,7 +4978,7 @@ // CHECK41-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK41-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK41-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK41-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK41-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK41-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK41-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK41: omp.body.continue: @@ -5107,7 +5107,7 @@ // CHECK43-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK43-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK43-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK43-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK43-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK43-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK43-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK43: omp.body.continue: @@ -5276,7 +5276,7 @@ // CHECK45-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK45-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK45-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK45-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK45-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK45-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP8]] // CHECK45-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK45: omp.body.continue: @@ -5441,7 +5441,7 @@ // CHECK47-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK47-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK47-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP9]] -// CHECK47-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK47-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK47-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK47-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK47: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp +++ clang/test/OpenMP/teams_distribute_simd_collapse_codegen.cpp @@ -161,8 +161,8 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK1: omp_offload.cont: // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i64 0, i64 0 -// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK1-NEXT: ret i32 [[TMP20]] // @@ -239,10 +239,10 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP4]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -337,8 +337,8 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] // CHECK3: omp_offload.cont: // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A3]], inrange i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 // CHECK3-NEXT: ret i32 [[TMP20]] // @@ -414,9 +414,9 @@ // CHECK3-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP5]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -496,10 +496,10 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -513,8 +513,8 @@ // CHECK5-NEXT: store i32 123, ptr [[I]], align 4 // CHECK5-NEXT: store i32 456, ptr [[J]], align 4 // CHECK5-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], i64 0, i64 0 -// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A10]], inrange i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX11]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4 // CHECK5-NEXT: ret i32 [[TMP9]] // @@ -566,9 +566,9 @@ // CHECK7-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -582,8 +582,8 @@ // CHECK7-NEXT: store i32 123, ptr [[I]], align 4 // CHECK7-NEXT: store i32 456, ptr [[J]], align 4 // CHECK7-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [123 x [456 x i32]], ptr [[A9]], inrange i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [456 x i32], ptr [[ARRAYIDX10]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, ptr [[ARRAYIDX11]], align 4 // CHECK7-NEXT: ret i32 [[TMP9]] // @@ -1042,10 +1042,10 @@ // CHECK9-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP12]] to i64 -// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM7]] +// CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM7]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX8]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1527,9 +1527,9 @@ // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]] // CHECK11-NEXT: store i32 [[ADD6]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP12]] +// CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP12]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1745,10 +1745,10 @@ // CHECK13-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM6]] +// CHECK13-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i64 0, i64 [[IDXPROM6]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -1943,9 +1943,9 @@ // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]] // CHECK15-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], i32 0, i32 [[TMP6]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [2 x i32]], ptr [[A]], inrange i32 0, i32 [[TMP6]] // CHECK15-NEXT: [[TMP7:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP7]] +// CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x i32], ptr [[ARRAYIDX]], inrange i32 0, i32 [[TMP7]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp +++ clang/test/OpenMP/teams_distribute_simd_dist_schedule_codegen.cpp @@ -287,7 +287,7 @@ // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK1: omp_offload.cont17: // CHECK1-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i64 0, i64 0 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i64 0, i64 0 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK1-NEXT: ret i32 [[TMP60]] // @@ -353,7 +353,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -438,7 +438,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -530,7 +530,7 @@ // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -727,7 +727,7 @@ // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] // CHECK3: omp_offload.cont17: // CHECK3-NEXT: [[A18:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], i32 0, i32 0 +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A18]], inrange i32 0, i32 0 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 // CHECK3-NEXT: ret i32 [[TMP60]] // @@ -792,7 +792,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -876,7 +876,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -967,7 +967,7 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[TMP0]], i32 0, i32 0 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1055,7 +1055,7 @@ // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1085,7 +1085,7 @@ // CHECK5-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i64 0, i64 [[IDXPROM14]] +// CHECK5-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i64 0, i64 [[IDXPROM14]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX15]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] // CHECK5: omp.body.continue16: @@ -1115,7 +1115,7 @@ // CHECK5-NEXT: [[A30:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, ptr [[I24]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: [[IDXPROM31:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], i64 0, i64 [[IDXPROM31]] +// CHECK5-NEXT: [[ARRAYIDX32:%.*]] = getelementptr inbounds [123 x i32], ptr [[A30]], inrange i64 0, i64 [[IDXPROM31]] // CHECK5-NEXT: store i32 0, ptr [[ARRAYIDX32]], align 4, !llvm.access.group [[ACC_GRP9]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE33:%.*]] // CHECK5: omp.body.continue33: @@ -1128,7 +1128,7 @@ // CHECK5: omp.inner.for.end36: // CHECK5-NEXT: store i32 123, ptr [[I24]], align 4 // CHECK5-NEXT: [[A37:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], i64 0, i64 0 +// CHECK5-NEXT: [[ARRAYIDX38:%.*]] = getelementptr inbounds [123 x i32], ptr [[A37]], inrange i64 0, i64 0 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX38]], align 4 // CHECK5-NEXT: ret i32 [[TMP18]] // @@ -1179,7 +1179,7 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SS:%.*]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [123 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: @@ -1208,7 +1208,7 @@ // CHECK7-NEXT: store i32 [[ADD12]], ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [123 x i32], ptr [[A13]], inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX14]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE15:%.*]] // CHECK7: omp.body.continue15: @@ -1237,7 +1237,7 @@ // CHECK7-NEXT: store i32 [[ADD28]], ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: [[A29:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, ptr [[I23]], align 4, !llvm.access.group [[ACC_GRP10]] -// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], i32 0, i32 [[TMP16]] +// CHECK7-NEXT: [[ARRAYIDX30:%.*]] = getelementptr inbounds [123 x i32], ptr [[A29]], inrange i32 0, i32 [[TMP16]] // CHECK7-NEXT: store i32 0, ptr [[ARRAYIDX30]], align 4, !llvm.access.group [[ACC_GRP10]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE31:%.*]] // CHECK7: omp.body.continue31: @@ -1250,7 +1250,7 @@ // CHECK7: omp.inner.for.end34: // CHECK7-NEXT: store i32 123, ptr [[I23]], align 4 // CHECK7-NEXT: [[A35:%.*]] = getelementptr inbounds [[STRUCT_SS]], ptr [[THIS1]], i32 0, i32 0 -// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], i32 0, i32 0 +// CHECK7-NEXT: [[ARRAYIDX36:%.*]] = getelementptr inbounds [123 x i32], ptr [[A35]], inrange i32 0, i32 0 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, ptr [[ARRAYIDX36]], align 4 // CHECK7-NEXT: ret i32 [[TMP18]] // @@ -2123,7 +2123,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2207,7 +2207,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -2298,7 +2298,7 @@ // CHECK9-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK9-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP27]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -3205,7 +3205,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP22]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3288,7 +3288,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK11-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP25]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP9]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3378,7 +3378,7 @@ // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK11-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP28]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP11]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], inrange i32 0, i32 [[TMP11]] // CHECK11-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP28]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -3659,7 +3659,7 @@ // CHECK13-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -3688,7 +3688,7 @@ // CHECK13-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM12]] +// CHECK13-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM12]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX13]], align 4, !llvm.access.group [[ACC_GRP15]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE14:%.*]] // CHECK13: omp.body.continue14: @@ -3717,7 +3717,7 @@ // CHECK13-NEXT: store i32 [[ADD27]], ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[TMP16:%.*]] = load i32, ptr [[I22]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: [[IDXPROM28:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i64 0, i64 [[IDXPROM28]] +// CHECK13-NEXT: [[ARRAYIDX29:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i64 0, i64 [[IDXPROM28]] // CHECK13-NEXT: store i32 0, ptr [[ARRAYIDX29]], align 4, !llvm.access.group [[ACC_GRP18]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE30:%.*]] // CHECK13: omp.body.continue30: @@ -3967,7 +3967,7 @@ // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: [[TMP4:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP13]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP4]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP4]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP13]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -3995,7 +3995,7 @@ // CHECK15-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]] // CHECK15-NEXT: store i32 [[ADD11]], ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: [[TMP10:%.*]] = load i32, ptr [[I6]], align 4, !llvm.access.group [[ACC_GRP16]] -// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP10]] +// CHECK15-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP10]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP16]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE13:%.*]] // CHECK15: omp.body.continue13: @@ -4023,7 +4023,7 @@ // CHECK15-NEXT: [[ADD26:%.*]] = add nsw i32 0, [[MUL25]] // CHECK15-NEXT: store i32 [[ADD26]], ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: [[TMP16:%.*]] = load i32, ptr [[I21]], align 4, !llvm.access.group [[ACC_GRP19]] -// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], i32 0, i32 [[TMP16]] +// CHECK15-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds [10 x i32], ptr [[A]], inrange i32 0, i32 [[TMP16]] // CHECK15-NEXT: store i32 0, ptr [[ARRAYIDX27]], align 4, !llvm.access.group [[ACC_GRP19]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] // CHECK15: omp.body.continue28: Index: clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_simd_firstprivate_codegen.cpp @@ -457,11 +457,11 @@ // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 [[IDXPROM7]] +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i64 0, i64 [[IDXPROM7]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[VAR4]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP5]] @@ -826,12 +826,12 @@ // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i64 0, i64 [[IDXPROM9]] +// CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i64 0, i64 [[IDXPROM9]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -1281,10 +1281,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 [[TMP13]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 [[TMP13]] // CHECK3-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[VAR4]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[SIVAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP6]] @@ -1648,11 +1648,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], i32 0, i32 [[TMP14]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC2]], inrange i32 0, i32 [[TMP14]] // CHECK3-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], i32 0, i32 [[TMP16]] +// CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR3]], inrange i32 0, i32 [[TMP16]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1890,11 +1890,11 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 @var, i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP2]] @@ -1961,12 +1961,12 @@ // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM3]] +// CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM3]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP9]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -2213,10 +2213,10 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr @t_var, align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr @vec, inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr @s_arr, inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 @var, i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr @_ZZ4mainE5sivar, align 4, !llvm.access.group [[ACC_GRP3]] @@ -2282,11 +2282,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP8]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP8]] // CHECK7-NEXT: store i32 [[TMP7]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP9:%.*]] = load ptr, ptr [[_TMP1]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK7-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP10]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[TMP9]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp +++ clang/test/OpenMP/teams_distribute_simd_lastprivate_codegen.cpp @@ -763,12 +763,12 @@ // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP17]] to i64 -// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM9]] +// CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM9]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX10]], ptr align 4 [[TMP16]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1108,12 +1108,12 @@ // CHECK9-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK9-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP16]] to i64 -// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM8]] +// CHECK9-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM8]] // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP15]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK9: omp.body.continue: @@ -1479,11 +1479,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP15]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP15]] // CHECK11-NEXT: store i32 [[TMP14]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP16:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: [[TMP17:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], i32 0, i32 [[TMP17]] +// CHECK11-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP17]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP16]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -1822,11 +1822,11 @@ // CHECK11-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP13:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP14:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP14]] +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP14]] // CHECK11-NEXT: store i32 [[TMP13]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP15:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: [[TMP16:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP16]] +// CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP16]] // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP15]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK11: omp.body.continue: @@ -2011,12 +2011,12 @@ // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2176,12 +2176,12 @@ // CHECK13-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i64 0, i64 [[IDXPROM]] +// CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i64 0, i64 [[IDXPROM]] // CHECK13-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i64 0, i64 [[IDXPROM8]] +// CHECK13-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i64 0, i64 [[IDXPROM8]] // CHECK13-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX9]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK13: omp.body.continue: @@ -2411,11 +2411,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: @@ -2574,11 +2574,11 @@ // CHECK15-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR3]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], i32 0, i32 [[TMP9]] +// CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC4]], inrange i32 0, i32 [[TMP9]] // CHECK15-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP7]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], i32 0, i32 [[TMP11]] +// CHECK15-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR5]], inrange i32 0, i32 [[TMP11]] // CHECK15-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK15: omp.body.continue: Index: clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp +++ clang/test/OpenMP/teams_distribute_simd_private_codegen.cpp @@ -353,11 +353,11 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP10]] to i64 -// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM2]] +// CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM2]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX3]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP5]] // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP5]] @@ -567,12 +567,12 @@ // CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64 -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK1-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 8, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP11]] to i64 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 [[IDXPROM4]] +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM4]] // CHECK1-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX5]], ptr align 4 [[TMP10]], i64 4, i1 false), !llvm.access.group [[ACC_GRP11]] // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK1: omp.body.continue: @@ -901,10 +901,10 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] -// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP10]] +// CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP10]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP6]] @@ -1113,11 +1113,11 @@ // CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP9]] +// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP9]] // CHECK3-NEXT: store i32 [[TMP8]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[_TMP2]], align 4, !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP12]] -// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 [[TMP11]] +// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 [[TMP11]] // CHECK3-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX4]], ptr align 4 [[TMP10]], i32 4, i1 false), !llvm.access.group [[ACC_GRP12]] // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK3: omp.body.continue: @@ -1337,11 +1337,11 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP6]] to i64 -// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 [[IDXPROM1]] +// CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 [[IDXPROM1]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX2]], ptr align 4 [[VAR]], i64 4, i1 false), !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP2]] // CHECK5-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP2]] @@ -1433,12 +1433,12 @@ // CHECK5-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64 -// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i64 0, i64 [[IDXPROM]] +// CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i64 0, i64 [[IDXPROM]] // CHECK5-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 8, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP7]] to i64 -// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i64 0, i64 [[IDXPROM7]] +// CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i64 0, i64 [[IDXPROM7]] // CHECK5-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX8]], ptr align 4 [[TMP6]], i64 4, i1 false), !llvm.access.group [[ACC_GRP6]] // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK5: omp.body.continue: @@ -1714,10 +1714,10 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP6:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] -// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 [[TMP6]] +// CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 [[TMP6]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false), !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP3]] // CHECK7-NEXT: [[TMP8:%.*]] = load i32, ptr [[SIVAR]], align 4, !llvm.access.group [[ACC_GRP3]] @@ -1808,11 +1808,11 @@ // CHECK7-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR2]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP5:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], i32 0, i32 [[TMP5]] +// CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC3]], inrange i32 0, i32 [[TMP5]] // CHECK7-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP6:%.*]] = load ptr, ptr [[_TMP6]], align 4, !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: [[TMP7:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP7]] -// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], i32 0, i32 [[TMP7]] +// CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR4]], inrange i32 0, i32 [[TMP7]] // CHECK7-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX7]], ptr align 4 [[TMP6]], i32 4, i1 false), !llvm.access.group [[ACC_GRP7]] // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // CHECK7: omp.body.continue: Index: clang/test/OpenMP/teams_firstprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_firstprivate_codegen.cpp +++ clang/test/OpenMP/teams_firstprivate_codegen.cpp @@ -531,9 +531,9 @@ // CHECK9-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i64 4, i1 false) // CHECK9-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] @@ -941,9 +941,9 @@ // CHECK9-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK9-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK9-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], inrange i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i64 4, i1 false) // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 @@ -1332,9 +1332,9 @@ // CHECK11-NEXT: call void @_ZN1SIfEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR2]], inrange i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX6]], ptr align 4 [[VAR4]], i32 4, i1 false) // CHECK11-NEXT: store i32 2, ptr [[SIVAR_ADDR]], align 4 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] @@ -1742,9 +1742,9 @@ // CHECK11-NEXT: call void @_ZN1SIiEC1ERKS0_2St(ptr nonnull align 4 dereferenceable(4) [[VAR4]], ptr nonnull align 4 dereferenceable(4) [[TMP2]], ptr [[AGG_TMP5]]) // CHECK11-NEXT: call void @_ZN2StD1Ev(ptr nonnull align 4 dereferenceable(8) [[AGG_TMP5]]) #[[ATTR4]] // CHECK11-NEXT: [[TMP4:%.*]] = load i32, ptr [[T_VAR_ADDR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC1]], inrange i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX]], align 128 -// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], inrange i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX6]], ptr align 128 [[VAR4]], i32 4, i1 false) // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr nonnull align 4 dereferenceable(4) [[VAR4]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN7:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR2]], i32 0, i32 0 Index: clang/test/OpenMP/teams_private_codegen.cpp =================================================================== --- clang/test/OpenMP/teams_private_codegen.cpp +++ clang/test/OpenMP/teams_private_codegen.cpp @@ -688,9 +688,9 @@ // CHECK9: arrayctor.cont: // CHECK9-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i64 4, i1 false) // CHECK9-NEXT: store i32 3, ptr [[SIVAR]], align 4 // CHECK9-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] @@ -991,9 +991,9 @@ // CHECK9: arrayctor.cont: // CHECK9-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK9-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 -// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i64 0, i64 0 // CHECK9-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 -// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i64 0, i64 0 +// CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i64 0, i64 0 // CHECK9-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i64 4, i1 false) // CHECK9-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK9-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 @@ -1285,9 +1285,9 @@ // CHECK11: arrayctor.cont: // CHECK11-NEXT: call void @_ZN1SIfEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 4 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 4 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S], ptr [[S_ARR]], inrange i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 4 [[ARRAYIDX1]], ptr align 4 [[VAR]], i32 4, i1 false) // CHECK11-NEXT: store i32 3, ptr [[SIVAR]], align 4 // CHECK11-NEXT: call void @_ZN1SIfED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] @@ -1588,9 +1588,9 @@ // CHECK11: arrayctor.cont: // CHECK11-NEXT: call void @_ZN1SIiEC1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) // CHECK11-NEXT: [[TMP0:%.*]] = load i32, ptr [[T_VAR]], align 128 -// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], ptr [[VEC]], inrange i32 0, i32 0 // CHECK11-NEXT: store i32 [[TMP0]], ptr [[ARRAYIDX]], align 128 -// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 +// CHECK11-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], inrange i32 0, i32 0 // CHECK11-NEXT: call void @llvm.memcpy.p0.p0.i32(ptr align 128 [[ARRAYIDX1]], ptr align 128 [[VAR]], i32 4, i1 false) // CHECK11-NEXT: call void @_ZN1SIiED1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[VAR]]) #[[ATTR4]] // CHECK11-NEXT: [[ARRAY_BEGIN2:%.*]] = getelementptr inbounds [2 x %struct.S.0], ptr [[S_ARR]], i32 0, i32 0 Index: clang/test/OpenMP/threadprivate_codegen.cpp =================================================================== --- clang/test/OpenMP/threadprivate_codegen.cpp +++ clang/test/OpenMP/threadprivate_codegen.cpp @@ -1408,8 +1408,8 @@ // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] // CHECK1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 @@ -1550,8 +1550,8 @@ // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] // CHECK1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1 -// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], inrange i64 0, i64 1 +// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 @@ -2062,8 +2062,8 @@ // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]] // CHECK2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1 -// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], inrange i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4 @@ -2179,8 +2179,8 @@ // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]] // CHECK2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB1]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.) -// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1 -// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], inrange i64 0, i64 1 +// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4 @@ -2840,179 +2840,179 @@ // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG118:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG120:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG121:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG122:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] -// SIMD2-NEXT: ret void, !dbg [[DBG129:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] +// SIMD2-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG137:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] -// SIMD2-NEXT: ret void, !dbg [[DBG147:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG147]] +// SIMD2-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG152:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG153:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// SIMD2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG153:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG154:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] -// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] +// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]] +// SIMD2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]] // SIMD2: invoke.cont: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] // SIMD2: invoke.cont2: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]] // SIMD2: invoke.cont3: -// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]] // SIMD2: invoke.cont7: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] // SIMD2: invoke.cont8: -// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] +// SIMD2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] // SIMD2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]] // SIMD2: invoke.cont9: -// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG164]] +// SIMD2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG165]] // SIMD2: lpad: // SIMD2-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] -// SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG165]] -// SIMD2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG165]] -// SIMD2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG156]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] +// SIMD2-NEXT: cleanup, !dbg [[DBG166:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG166]] +// SIMD2-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG166]] +// SIMD2-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG157]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] // SIMD2: arraydestroy.body: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG156]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG157]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] // SIMD2: arraydestroy.done4: -// SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] +// SIMD2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG157]] // SIMD2: lpad6: // SIMD2-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG165]] -// SIMD2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG165]] -// SIMD2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG160]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] +// SIMD2-NEXT: cleanup, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG166]] +// SIMD2-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG166]] +// SIMD2-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG161]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]] // SIMD2: arraydestroy.body11: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG160]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG161]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]] // SIMD2: arraydestroy.done15: -// SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] +// SIMD2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG161]] // SIMD2: ehcleanup: -// SIMD2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG154]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] +// SIMD2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG155]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]] // SIMD2: arraydestroy.body17: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG154]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG155]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]] // SIMD2: arraydestroy.done21: -// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] +// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG155]] // SIMD2: eh.resume: -// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG154]] -// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] -// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG154]] -// SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] -// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] +// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG155]] +// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]] +// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG155]] +// SIMD2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]] +// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG155]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { +// SIMD2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] -// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]] +// SIMD2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG172]] // SIMD2: arraydestroy.body: -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG171]] -// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG171]] -// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG171]] -// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG171]] -// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG171]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG172]] +// SIMD2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG172]] +// SIMD2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG172]] +// SIMD2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG172]] +// SIMD2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG172]] // SIMD2: arraydestroy.done1: -// SIMD2-NEXT: ret void, !dbg [[DBG171]] +// SIMD2-NEXT: ret void, !dbg [[DBG172]] // // // SIMD2-LABEL: define {{[^@]+}}@main @@ -3023,302 +3023,302 @@ // SIMD2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG174:![0-9]+]] -// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG175:![0-9]+]] +// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]] // SIMD2: init.check: -// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] +// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]] // SIMD2: init: -// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG176:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG177:![0-9]+]] // SIMD2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) -// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] +// SIMD2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]] // SIMD2: invoke.cont: -// SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG174]] +// SIMD2-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG175]] // SIMD2: init.end: -// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG178:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG180:![0-9]+]] -// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] -// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG181]] -// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG182:![0-9]+]] -// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] -// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] -// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG183]] -// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG184:![0-9]+]] -// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] -// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG185]] -// SIMD2-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG186:![0-9]+]] -// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] -// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] -// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]] -// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG188:![0-9]+]] -// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]] -// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] -// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]] -// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] -// SIMD2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG191:![0-9]+]] -// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] -// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG191]] -// SIMD2-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] -// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] -// SIMD2-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG193:![0-9]+]] -// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] -// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG193]] -// SIMD2-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG194:![0-9]+]] -// SIMD2-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG195:![0-9]+]] -// SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] -// SIMD2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG195]] -// SIMD2-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] -// SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] +// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG179:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG181:![0-9]+]] +// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]] +// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]] +// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG182]] +// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG183:![0-9]+]] +// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]] +// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG184]] +// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG185:![0-9]+]] +// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]] +// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG186]] +// SIMD2-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG187:![0-9]+]] +// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG188:![0-9]+]] +// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]] +// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG188]] +// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG189:![0-9]+]] +// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG190:![0-9]+]] +// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]] +// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG190]] +// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]] +// SIMD2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG192:![0-9]+]] +// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]] +// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG192]] +// SIMD2-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]] +// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]] +// SIMD2-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG194:![0-9]+]] +// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]] +// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG194]] +// SIMD2-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG195:![0-9]+]] +// SIMD2-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] +// SIMD2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]] +// SIMD2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG196]] +// SIMD2-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG197:![0-9]+]] +// SIMD2-NEXT: ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]] // SIMD2: lpad: // SIMD2-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } -// SIMD2-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] -// SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG198]] -// SIMD2-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG198]] -// SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG198]] -// SIMD2-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] -// SIMD2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] +// SIMD2-NEXT: cleanup, !dbg [[DBG199:![0-9]+]] +// SIMD2-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG199]] +// SIMD2-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG199]] +// SIMD2-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG199]] +// SIMD2-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]] +// SIMD2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG175]] // SIMD2: eh.resume: -// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG174]] -// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] -// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG174]] -// SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] -// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] +// SIMD2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG175]] +// SIMD2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]] +// SIMD2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG175]] +// SIMD2-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]] +// SIMD2-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG175]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] -// SIMD2-NEXT: ret void, !dbg [[DBG206:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]] +// SIMD2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG206]] +// SIMD2-NEXT: ret void, !dbg [[DBG207:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG209:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG211:![0-9]+]] +// SIMD2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG212:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_Z6foobarv -// SIMD2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG212:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG213:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[RES:%.*]] = alloca i32, align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META213:![0-9]+]], metadata !DIExpression()), !dbg [[DBG214:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG215:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] -// SIMD2-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG217:![0-9]+]] -// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] -// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG218]] -// SIMD2-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] -// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] -// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG220]] -// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG221:![0-9]+]] -// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]] -// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] -// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]] -// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG223:![0-9]+]] -// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] -// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] -// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]] -// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] -// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] -// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG226]] -// SIMD2-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] -// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] -// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] -// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG228]] -// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG229:![0-9]+]] -// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] -// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG230]] -// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG216:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] +// SIMD2-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG218:![0-9]+]] +// SIMD2-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// SIMD2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]] +// SIMD2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG219]] +// SIMD2-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]] +// SIMD2-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// SIMD2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]] +// SIMD2-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG221]] +// SIMD2-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG222:![0-9]+]] +// SIMD2-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] +// SIMD2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]] +// SIMD2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG223]] +// SIMD2-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG224:![0-9]+]] +// SIMD2-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] +// SIMD2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]] +// SIMD2-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG225]] +// SIMD2-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]] +// SIMD2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// SIMD2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]] +// SIMD2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG227]] +// SIMD2-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]] +// SIMD2-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]] +// SIMD2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// SIMD2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]] +// SIMD2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG229]] +// SIMD2-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG230:![0-9]+]] +// SIMD2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// SIMD2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]] +// SIMD2-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG231]] +// SIMD2-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// SIMD2-NEXT: ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234:![0-9]+]] -// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] -// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235:![0-9]+]] +// SIMD2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]] +// SIMD2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]] // SIMD2: init.check: -// SIMD2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234]] -// SIMD2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] -// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] -// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG234]] +// SIMD2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235]] +// SIMD2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG236:![0-9]+]] +// SIMD2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG235]] +// SIMD2-NEXT: br label [[INIT_END]], !dbg [[DBG235]] // SIMD2: init.end: -// SIMD2-NEXT: ret void, !dbg [[DBG237:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG238:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG241:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] -// SIMD2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] -// SIMD2-NEXT: ret void, !dbg [[DBG245:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG245]] +// SIMD2-NEXT: ret void, !dbg [[DBG246:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META248:![0-9]+]], metadata !DIExpression()), !dbg [[DBG249:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG250:![0-9]+]] +// SIMD2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG251:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META252:![0-9]+]], metadata !DIExpression()), !dbg [[DBG253:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG255:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG256]] -// SIMD2-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG257]] +// SIMD2-NEXT: ret void, !dbg [[DBG259:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG262:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG264:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG265:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG265:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG266:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META267:![0-9]+]], metadata !DIExpression()), !dbg [[DBG268:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG269:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG271]] -// SIMD2-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG272]] +// SIMD2-NEXT: ret void, !dbg [[DBG274:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META275:![0-9]+]], metadata !DIExpression()), !dbg [[DBG276:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG279:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG280:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG280:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG281:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META282:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG286]] -// SIMD2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG287]] +// SIMD2-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META290:![0-9]+]], metadata !DIExpression()), !dbg [[DBG291:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG294:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG295:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG296:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // SIMD2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] -// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] -// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG301]] -// SIMD2-NEXT: ret void, !dbg [[DBG303:![0-9]+]] +// SIMD2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]] +// SIMD2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]] +// SIMD2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG302]] +// SIMD2-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { +// SIMD2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] { // SIMD2-NEXT: entry: // SIMD2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]] +// SIMD2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META306:![0-9]+]], metadata !DIExpression()), !dbg [[DBG307:![0-9]+]] // SIMD2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] -// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG309:![0-9]+]] -// SIMD2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// SIMD2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]] +// SIMD2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG310:![0-9]+]] +// SIMD2-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // SIMD2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { +// SIMD2-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] { // SIMD2-NEXT: entry: -// SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] -// SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] -// SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] +// SIMD2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]] +// SIMD2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG314]] +// SIMD2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG314]] // SIMD2-NEXT: ret void // // @@ -3588,8 +3588,8 @@ // CHECK-TLS1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] // CHECK-TLS1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK-TLS1-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1 -// CHECK-TLS1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], inrange i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK-TLS1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK-TLS1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4 // CHECK-TLS1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 @@ -3732,8 +3732,8 @@ // CHECK-TLS1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] // CHECK-TLS1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK-TLS1-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1 -// CHECK-TLS1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], inrange i64 0, i64 1 +// CHECK-TLS1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK-TLS1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK-TLS1-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4 // CHECK-TLS1-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 @@ -3890,8 +3890,8 @@ // CHECK-TLS2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]] // CHECK-TLS2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4 // CHECK-TLS2-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1 -// CHECK-TLS2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], inrange i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK-TLS2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0 // CHECK-TLS2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4 // CHECK-TLS2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4 @@ -4021,8 +4021,8 @@ // CHECK-TLS2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]] // CHECK-TLS2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4 // CHECK-TLS2-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x() -// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1 -// CHECK-TLS2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], inrange i64 0, i64 1 +// CHECK-TLS2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1 // CHECK-TLS2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0 // CHECK-TLS2-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4 // CHECK-TLS2-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4 @@ -4383,235 +4383,235 @@ // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK-TLS3-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG122:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG120:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG122:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG123:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG124:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG129:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG130:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG130:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG130]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG131:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG132:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META133:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG135:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG135:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG136:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG136:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG137:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META137:![0-9]+]], metadata !DIExpression()), !dbg [[DBG138:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG139:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META139:![0-9]+]], metadata !DIExpression()), !dbg [[DBG140:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG141:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG142:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG141]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG143:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG142:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG143:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG142]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG144:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG144:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG145:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META146:![0-9]+]], metadata !DIExpression()), !dbg [[DBG147:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG147:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG149:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG150:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG148:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG150:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG151:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG151:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG152:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG152:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG154:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG155:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG153:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG155:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG156:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG156:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG157:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG159:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META158:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META160:![0-9]+]], metadata !DIExpression()), !dbg [[DBG161:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG162:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG162]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG163:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG163:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG163]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG164:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG164:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG165:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META165:![0-9]+]], metadata !DIExpression()), !dbg [[DBG166:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META166:![0-9]+]], metadata !DIExpression()), !dbg [[DBG167:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG167:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG168:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG168:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG169:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG169:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG170:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG175:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG174]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG176:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG175:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG176:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG175]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG177:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG177:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG178:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG179:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG180:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG182:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG183:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG181:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG183:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG184:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK-TLS3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG184:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG185:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185:![0-9]+]] -// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188:![0-9]+]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG188:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG189:![0-9]+]] // CHECK-TLS3: invoke.cont: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG189:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]] // CHECK-TLS3: invoke.cont2: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG190:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG191:![0-9]+]] // CHECK-TLS3: invoke.cont3: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191:![0-9]+]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192:![0-9]+]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG192:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG193:![0-9]+]] // CHECK-TLS3: invoke.cont7: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG193:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]] // CHECK-TLS3: invoke.cont8: -// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] +// CHECK-TLS3-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]] // CHECK-TLS3-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// CHECK-TLS3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG194:![0-9]+]] +// CHECK-TLS3-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG195:![0-9]+]] // CHECK-TLS3: invoke.cont9: -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG195:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG195]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG196:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG196]] // CHECK-TLS3: lpad: // CHECK-TLS3-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG196:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG187]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG197:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG188]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG188]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG188]] // CHECK-TLS3: arraydestroy.body: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG187]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG187]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG187]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG188]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG188]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG188]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG188]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG188]] // CHECK-TLS3: arraydestroy.done4: -// CHECK-TLS3-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG187]] +// CHECK-TLS3-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG188]] // CHECK-TLS3: lpad6: // CHECK-TLS3-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG196]] -// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG191]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: cleanup, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG197]] +// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG192]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG192]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG192]] // CHECK-TLS3: arraydestroy.body11: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG191]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG191]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG191]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG191]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG192]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG192]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG192]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG192]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG192]] // CHECK-TLS3: arraydestroy.done15: -// CHECK-TLS3-NEXT: br label [[EHCLEANUP]], !dbg [[DBG191]] +// CHECK-TLS3-NEXT: br label [[EHCLEANUP]], !dbg [[DBG192]] // CHECK-TLS3: ehcleanup: -// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG185]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG186]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG186]] // CHECK-TLS3: arraydestroy.body17: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG186]] // CHECK-TLS3: arraydestroy.done21: -// CHECK-TLS3-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG186]] // CHECK-TLS3: eh.resume: -// CHECK-TLS3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG185]] -// CHECK-TLS3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG185]] +// CHECK-TLS3-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG186]] +// CHECK-TLS3-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG186]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG197:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG198:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]] -// CHECK-TLS3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG202]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META202:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] +// CHECK-TLS3-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG203]] // CHECK-TLS3: arraydestroy.body: -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG202]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG202]] -// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG202]] -// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG202]] -// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG202]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG203]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG203]] +// CHECK-TLS3-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG203]] +// CHECK-TLS3-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG203]] +// CHECK-TLS3-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG203]] // CHECK-TLS3: arraydestroy.done1: -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG202]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG203]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@main @@ -4620,72 +4620,72 @@ // CHECK-TLS3-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: [[RES:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205:![0-9]+]] -// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG205]] -// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG205]], !prof [[PROF206:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG206:![0-9]+]] +// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG206]] +// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG206]], !prof [[PROF207:![0-9]+]] // CHECK-TLS3: init.check: -// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG207:![0-9]+]] -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG208]] -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG209:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG205]] -// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG205]] -// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG205]] +// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG208:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG209:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG209]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]), !dbg [[DBG210:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG206]] +// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVZ4mainE2sm, align 1, !dbg [[DBG206]] +// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG206]] // CHECK-TLS3: init.end: -// CHECK-TLS3-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG210:![0-9]+]] -// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG211:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG211]] -// CHECK-TLS3-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG212:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG213:![0-9]+]] -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG214]] -// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG215:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG215]] -// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG215]] -// CHECK-TLS3-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG216:![0-9]+]] -// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG217:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG217]] -// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG218]] -// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG218]] -// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG220]] -// CHECK-TLS3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG220]] -// CHECK-TLS3-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG221:![0-9]+]] -// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG222:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG222]] -// CHECK-TLS3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG223]] -// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG223]] -// CHECK-TLS3-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG224:![0-9]+]] -// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG224]] -// CHECK-TLS3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG224]] -// CHECK-TLS3-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG225:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG225]] -// CHECK-TLS3-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG226]] -// CHECK-TLS3-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG226]] -// CHECK-TLS3-NEXT: [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG227:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG227]] -// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG228]] -// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG228]] -// CHECK-TLS3-NEXT: [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG229:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG229]] -// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG229]] -// CHECK-TLS3-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG230]] -// CHECK-TLS3-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG230]] -// CHECK-TLS3-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG231:![0-9]+]] -// CHECK-TLS3-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG232:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG232]] -// CHECK-TLS3-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG233:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG233]] -// CHECK-TLS3-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG233]] -// CHECK-TLS3-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG234:![0-9]+]] -// CHECK-TLS3-NEXT: ret i32 [[TMP29]], !dbg [[DBG235:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP4:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG211:![0-9]+]] +// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG212]] +// CHECK-TLS3-NEXT: store i32 [[TMP5]], ptr [[RES]], align 4, !dbg [[DBG213:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP6:%.*]] = call align 8 ptr @llvm.threadlocal.address.p0(ptr align 8 @_ZZ4mainE2sm), !dbg [[DBG214:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP6]], i32 0, i32 0, !dbg [[DBG215:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP7:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG215]] +// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG216]] +// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG216]] +// CHECK-TLS3-NEXT: [[TMP9:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG217:![0-9]+]] +// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG218:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP10:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG218]] +// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG219]] +// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG219]] +// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG221]] +// CHECK-TLS3-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG221]] +// CHECK-TLS3-NEXT: [[TMP14:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG222:![0-9]+]] +// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP14]], i32 0, i32 0, !dbg [[DBG223:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG223]] +// CHECK-TLS3-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG224]] +// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG224]] +// CHECK-TLS3-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG225:![0-9]+]] +// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], inrange i64 0, i64 1, !dbg [[DBG225]] +// CHECK-TLS3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG225]] +// CHECK-TLS3-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG226:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG226]] +// CHECK-TLS3-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG227]] +// CHECK-TLS3-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG227]] +// CHECK-TLS3-NEXT: [[TMP20:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG228:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4, !dbg [[DBG228]] +// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG229]] +// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG229]] +// CHECK-TLS3-NEXT: [[TMP23:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG230:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP24:%.*]] = load float, ptr [[TMP23]], align 4, !dbg [[DBG230]] +// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP24]] to i32, !dbg [[DBG230]] +// CHECK-TLS3-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP25]], [[CONV]], !dbg [[DBG231]] +// CHECK-TLS3-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG231]] +// CHECK-TLS3-NEXT: [[TMP26:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG232:![0-9]+]] +// CHECK-TLS3-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP26]], i32 0, i32 0, !dbg [[DBG233:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP27:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG233]] +// CHECK-TLS3-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG234:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP28]], [[TMP27]], !dbg [[DBG234]] +// CHECK-TLS3-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG234]] +// CHECK-TLS3-NEXT: [[TMP29:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG235:![0-9]+]] +// CHECK-TLS3-NEXT: ret i32 [[TMP29]], !dbg [[DBG236:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWL3gs1 @@ -4696,29 +4696,29 @@ // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG236:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG237:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META237:![0-9]+]], metadata !DIExpression()), !dbg [[DBG239:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG240:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG241:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META241:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG242:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG242]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG243:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG243:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG243]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG244:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG244:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG245:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META246:![0-9]+]], metadata !DIExpression()), !dbg [[DBG247:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG247:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG248:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG248:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZTWN6Static1sE @@ -4758,174 +4758,174 @@ // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG249:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG250:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META250:![0-9]+]], metadata !DIExpression()), !dbg [[DBG251:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META252:![0-9]+]], metadata !DIExpression()), !dbg [[DBG253:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG254:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG255:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG254]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG256:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG255:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG256:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG255]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG257:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG257:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG258:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META258:![0-9]+]], metadata !DIExpression()), !dbg [[DBG259:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META259:![0-9]+]], metadata !DIExpression()), !dbg [[DBG260:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG260:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG262:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG263:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG261:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG263:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG264:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_Z6foobarv -// CHECK-TLS3-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG264:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG265:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[RES:%.*]] = alloca i32, align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META265:![0-9]+]], metadata !DIExpression()), !dbg [[DBG266:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG267:![0-9]+]] -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG268:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG268]] -// CHECK-TLS3-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG269:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG270:![0-9]+]] -// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG271]] -// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG272:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG272]] -// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG272]] -// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG273:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG274:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG274]] -// CHECK-TLS3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG274]] -// CHECK-TLS3-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG275:![0-9]+]] -// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG276:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG276]] -// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG277:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG277]] -// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG277]] -// CHECK-TLS3-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG278:![0-9]+]] -// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG278]] -// CHECK-TLS3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG278]] -// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG279:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG279]] -// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG280:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG280]] -// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG280]] -// CHECK-TLS3-NEXT: [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG281:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG281]] -// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG282]] -// CHECK-TLS3-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG282]] -// CHECK-TLS3-NEXT: [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG283:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG283]] -// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG283]] -// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG284:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG284]] -// CHECK-TLS3-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG284]] -// CHECK-TLS3-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG285:![0-9]+]] -// CHECK-TLS3-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG286]] -// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG287:![0-9]+]] -// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG287]] -// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG287]] -// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG288:![0-9]+]] -// CHECK-TLS3-NEXT: ret i32 [[TMP22]], !dbg [[DBG289:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META266:![0-9]+]], metadata !DIExpression()), !dbg [[DBG267:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = call ptr @_ZTWN6Static1sE(), !dbg [[DBG268:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP0]], i32 0, i32 0, !dbg [[DBG269:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG269]] +// CHECK-TLS3-NEXT: store i32 [[TMP1]], ptr [[RES]], align 4, !dbg [[DBG270:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP2:%.*]] = call ptr @_ZTWL3gs1(), !dbg [[DBG271:![0-9]+]] +// CHECK-TLS3-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP2]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP3:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG272]] +// CHECK-TLS3-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG273:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG273]] +// CHECK-TLS3-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG273]] +// CHECK-TLS3-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG274:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG275:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG275]] +// CHECK-TLS3-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG275]] +// CHECK-TLS3-NEXT: [[TMP7:%.*]] = call ptr @_ZTW3gs3(), !dbg [[DBG276:![0-9]+]] +// CHECK-TLS3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP8:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG277]] +// CHECK-TLS3-NEXT: [[TMP9:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG278:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG278]] +// CHECK-TLS3-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG278]] +// CHECK-TLS3-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG279:![0-9]+]] +// CHECK-TLS3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], inrange i64 0, i64 1, !dbg [[DBG279]] +// CHECK-TLS3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG279]] +// CHECK-TLS3-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG280]] +// CHECK-TLS3-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG281:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG281]] +// CHECK-TLS3-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG281]] +// CHECK-TLS3-NEXT: [[TMP13:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIiE2stE), !dbg [[DBG282:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4, !dbg [[DBG282]] +// CHECK-TLS3-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG283:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP14]], !dbg [[DBG283]] +// CHECK-TLS3-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG283]] +// CHECK-TLS3-NEXT: [[TMP16:%.*]] = call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @_ZN2STIfE2stE), !dbg [[DBG284:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP16]], align 4, !dbg [[DBG284]] +// CHECK-TLS3-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG284]] +// CHECK-TLS3-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG285:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG285]] +// CHECK-TLS3-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG285]] +// CHECK-TLS3-NEXT: [[TMP19:%.*]] = call ptr @_ZTWN2STI2S4E2stE(), !dbg [[DBG286:![0-9]+]] +// CHECK-TLS3-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP19]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP20:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG287]] +// CHECK-TLS3-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG288:![0-9]+]] +// CHECK-TLS3-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP21]], [[TMP20]], !dbg [[DBG288]] +// CHECK-TLS3-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG288]] +// CHECK-TLS3-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG289:![0-9]+]] +// CHECK-TLS3-NEXT: ret i32 [[TMP22]], !dbg [[DBG290:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG290:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG291:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291:![0-9]+]] -// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG291]] -// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG291]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292:![0-9]+]] +// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG292]] +// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG292]] // CHECK-TLS3: init.check: -// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291]] -// CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG292:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG291]] -// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG291]] +// CHECK-TLS3-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292]] +// CHECK-TLS3-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG293:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG292]] +// CHECK-TLS3-NEXT: br label [[INIT_END]], !dbg [[DBG292]] // CHECK-TLS3: init.end: -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG294:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG295:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG295:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG296:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META296:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] -// CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG302]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG303:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG303:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META304:![0-9]+]], metadata !DIExpression()), !dbg [[DBG305:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG306:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG307:![0-9]+]] +// CHECK-TLS3-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG307:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG308:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG308:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG309:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META309:![0-9]+]], metadata !DIExpression()), !dbg [[DBG310:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311:![0-9]+]] // CHECK-TLS3-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META311:![0-9]+]], metadata !DIExpression()), !dbg [[DBG312:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG313:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG313:![0-9]+]] -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG314:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG313]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG314]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG316:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG316:![0-9]+]] { +// CHECK-TLS3-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG317:![0-9]+]] { // CHECK-TLS3-NEXT: entry: // CHECK-TLS3-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS3-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META317:![0-9]+]], metadata !DIExpression()), !dbg [[DBG318:![0-9]+]] +// CHECK-TLS3-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META318:![0-9]+]], metadata !DIExpression()), !dbg [[DBG319:![0-9]+]] // CHECK-TLS3-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] -// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG321:![0-9]+]] -// CHECK-TLS3-NEXT: ret void, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]] +// CHECK-TLS3-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS3-NEXT: ret void, !dbg [[DBG323:![0-9]+]] // // // CHECK-TLS3-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG323:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG324:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG325:![0-9]+]] +// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG326:![0-9]+]] // CHECK-TLS3-NEXT: ret void // // // CHECK-TLS3-LABEL: define {{[^@]+}}@__tls_init -// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG326:![0-9]+]] { +// CHECK-TLS3-SAME: () #[[ATTR0]] !dbg [[DBG327:![0-9]+]] { // CHECK-TLS3-NEXT: entry: -// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG327:![0-9]+]] -// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG327]] -// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG327]], !prof [[PROF206]] +// CHECK-TLS3-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG328:![0-9]+]] +// CHECK-TLS3-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG328]] +// CHECK-TLS3-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG328]], !prof [[PROF207]] // CHECK-TLS3: init: -// CHECK-TLS3-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG327]] -// CHECK-TLS3-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG327]] -// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG327]] -// CHECK-TLS3-NEXT: br label [[EXIT]], !dbg [[DBG327]] +// CHECK-TLS3-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG328]] +// CHECK-TLS3-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG328]] +// CHECK-TLS3-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG328]] +// CHECK-TLS3-NEXT: br label [[EXIT]], !dbg [[DBG328]] // CHECK-TLS3: exit: // CHECK-TLS3-NEXT: ret void // @@ -4976,8 +4976,8 @@ // CHECK-TLS4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG136]] // CHECK-TLS4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG136]] // CHECK-TLS4-NEXT: [[TMP17:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG137:![0-9]+]] -// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], i64 0, i64 1, !dbg [[DBG137]] -// CHECK-TLS4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG137]] +// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP17]], inrange i64 0, i64 1, !dbg [[DBG137]] +// CHECK-TLS4-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG137]] // CHECK-TLS4-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG138:![0-9]+]] // CHECK-TLS4-NEXT: [[TMP18:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG138]] // CHECK-TLS4-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG139:![0-9]+]] @@ -5111,8 +5111,8 @@ // CHECK-TLS4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP8]], !dbg [[DBG175]] // CHECK-TLS4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG175]] // CHECK-TLS4-NEXT: [[TMP10:%.*]] = call ptr @_ZTW5arr_x(), !dbg [[DBG176:![0-9]+]] -// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], i64 0, i64 1, !dbg [[DBG176]] -// CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG176]] +// CHECK-TLS4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP10]], inrange i64 0, i64 1, !dbg [[DBG176]] +// CHECK-TLS4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG176]] // CHECK-TLS4-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG177:![0-9]+]] // CHECK-TLS4-NEXT: [[TMP11:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG177]] // CHECK-TLS4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG178:![0-9]+]] @@ -5142,352 +5142,352 @@ // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init // CHECK-TLS4-SAME: () #[[ATTR7:[0-9]+]] !dbg [[DBG188:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG191:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG193:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG194:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG192:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG194:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG195:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG195:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG196:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META196:![0-9]+]], metadata !DIExpression()), !dbg [[DBG198:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG199:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG200:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG201:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG201:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG201]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG202:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG202:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG202]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG203:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG203:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG204:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META205:![0-9]+]], metadata !DIExpression()), !dbg [[DBG206:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]], !dbg [[DBG206:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG207:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR5]], !dbg [[DBG207:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG208:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG208:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG209:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG211:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META211:![0-9]+]], metadata !DIExpression()), !dbg [[DBG212:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META212:![0-9]+]], metadata !DIExpression()), !dbg [[DBG213:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG213:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG214:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG213]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG215:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG215:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG214]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG216:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG216:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG217:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG218:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META218:![0-9]+]], metadata !DIExpression()), !dbg [[DBG219:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG219:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG221:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG222:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG220:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG222:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG223:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG223:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG224:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG224:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG226:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG227:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG225:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG227:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG228:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG228:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG229:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META229:![0-9]+]], metadata !DIExpression()), !dbg [[DBG231:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG232:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG233:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META233:![0-9]+]], metadata !DIExpression()), !dbg [[DBG234:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG234:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG234]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG235:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG235:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG235]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG236:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG236:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG237:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META237:![0-9]+]], metadata !DIExpression()), !dbg [[DBG238:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG239:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR5]], !dbg [[DBG239:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG240:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR5]], !dbg [[DBG240:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG241:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG241:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG242:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META244:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG246:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG246]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG248:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG247:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG248:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG247]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG249:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG250:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META250:![0-9]+]], metadata !DIExpression()), !dbg [[DBG251:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG252:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG254:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG255:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG253:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG255:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG256:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// CHECK-TLS4-SAME: () #[[ATTR7]] personality ptr @__gxx_personality_v0 !dbg [[DBG256:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR7]] personality ptr @__gxx_personality_v0 !dbg [[DBG257:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257:![0-9]+]] -// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260:![0-9]+]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG260:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG261:![0-9]+]] // CHECK-TLS4: invoke.cont: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG261:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG262:![0-9]+]] // CHECK-TLS4: invoke.cont2: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG262:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG263:![0-9]+]] // CHECK-TLS4: invoke.cont3: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263:![0-9]+]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264:![0-9]+]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG264:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG265:![0-9]+]] // CHECK-TLS4: invoke.cont7: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG265:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG266:![0-9]+]] // CHECK-TLS4: invoke.cont8: -// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] +// CHECK-TLS4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]] // CHECK-TLS4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// CHECK-TLS4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG266:![0-9]+]] +// CHECK-TLS4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG267:![0-9]+]] // CHECK-TLS4: invoke.cont9: -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG267:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG267]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_thread_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG268:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG268]] // CHECK-TLS4: lpad: // CHECK-TLS4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG268:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG259]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG259]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG259]] +// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG269:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG260]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG260]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG260]] // CHECK-TLS4: arraydestroy.body: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG259]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG259]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG259]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG259]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG259]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG260]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG260]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG260]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG260]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG260]] // CHECK-TLS4: arraydestroy.done4: -// CHECK-TLS4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG259]] +// CHECK-TLS4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG260]] // CHECK-TLS4: lpad6: // CHECK-TLS4-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] -// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG263]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG263]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG263]] +// CHECK-TLS4-NEXT: cleanup, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG269]] +// CHECK-TLS4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG264]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG264]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG264]] // CHECK-TLS4: arraydestroy.body11: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG263]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG263]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR5]], !dbg [[DBG263]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG263]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG263]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG264]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG264]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR5]], !dbg [[DBG264]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG264]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG264]] // CHECK-TLS4: arraydestroy.done15: -// CHECK-TLS4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG263]] +// CHECK-TLS4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG264]] // CHECK-TLS4: ehcleanup: -// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG257]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG258]] // CHECK-TLS4: arraydestroy.body17: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR5]], !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR5]], !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG258]] // CHECK-TLS4: arraydestroy.done21: -// CHECK-TLS4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG258]] // CHECK-TLS4: eh.resume: -// CHECK-TLS4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG257]] -// CHECK-TLS4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG257]] +// CHECK-TLS4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG258]] +// CHECK-TLS4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG258]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// CHECK-TLS4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7]] !dbg [[DBG269:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR7]] !dbg [[DBG270:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META273:![0-9]+]], metadata !DIExpression()), !dbg [[DBG274:![0-9]+]] -// CHECK-TLS4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG274]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META274:![0-9]+]], metadata !DIExpression()), !dbg [[DBG275:![0-9]+]] +// CHECK-TLS4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG275]] // CHECK-TLS4: arraydestroy.body: -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG274]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG274]] -// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG274]] -// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG274]] -// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG274]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG275]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG275]] +// CHECK-TLS4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR5]], !dbg [[DBG275]] +// CHECK-TLS4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG275]] +// CHECK-TLS4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG275]] // CHECK-TLS4: arraydestroy.done1: -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG274]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG275]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG275:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG276:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META277:![0-9]+]], metadata !DIExpression()), !dbg [[DBG278:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META278:![0-9]+]], metadata !DIExpression()), !dbg [[DBG279:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META279:![0-9]+]], metadata !DIExpression()), !dbg [[DBG280:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG280]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG282:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG281:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG282:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG281]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG283:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG283:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] align 2 !dbg [[DBG284:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG288:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG289:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG289:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG290:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG290:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG291:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291:![0-9]+]] -// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG291]] -// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG291]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292:![0-9]+]] +// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG292]] +// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG292]] // CHECK-TLS4: init.check: -// CHECK-TLS4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG291]] -// CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG292:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG291]] -// CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG291]] +// CHECK-TLS4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG292]] +// CHECK-TLS4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG293:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR5]], !dbg [[DBG292]] +// CHECK-TLS4-NEXT: br label [[INIT_END]], !dbg [[DBG292]] // CHECK-TLS4: init.end: -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG294:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG295:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG295:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG296:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META296:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] -// CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG302]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG303:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG303:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG304:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META304:![0-9]+]], metadata !DIExpression()), !dbg [[DBG305:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]], !dbg [[DBG306:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG307:![0-9]+]] +// CHECK-TLS4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR5]], !dbg [[DBG307:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG308:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG308:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG309:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META309:![0-9]+]], metadata !DIExpression()), !dbg [[DBG310:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG311:![0-9]+]] // CHECK-TLS4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META311:![0-9]+]], metadata !DIExpression()), !dbg [[DBG312:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG313:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG313:![0-9]+]] -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG314:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG313]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG315:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG314]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG316:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG316:![0-9]+]] { +// CHECK-TLS4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR4]] comdat align 2 !dbg [[DBG317:![0-9]+]] { // CHECK-TLS4-NEXT: entry: // CHECK-TLS4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // CHECK-TLS4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META317:![0-9]+]], metadata !DIExpression()), !dbg [[DBG318:![0-9]+]] +// CHECK-TLS4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META318:![0-9]+]], metadata !DIExpression()), !dbg [[DBG319:![0-9]+]] // CHECK-TLS4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] -// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG321:![0-9]+]] -// CHECK-TLS4-NEXT: ret void, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]] +// CHECK-TLS4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG322:![0-9]+]] +// CHECK-TLS4-NEXT: ret void, !dbg [[DBG323:![0-9]+]] // // // CHECK-TLS4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG323:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG324:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG325:![0-9]+]] +// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG326:![0-9]+]] // CHECK-TLS4-NEXT: ret void // // // CHECK-TLS4-LABEL: define {{[^@]+}}@__tls_init -// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG326:![0-9]+]] { +// CHECK-TLS4-SAME: () #[[ATTR7]] !dbg [[DBG327:![0-9]+]] { // CHECK-TLS4-NEXT: entry: -// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG327:![0-9]+]] -// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG327]] -// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG327]], !prof [[PROF119]] +// CHECK-TLS4-NEXT: [[TMP0:%.*]] = load i8, ptr @__tls_guard, align 1, !dbg [[DBG328:![0-9]+]] +// CHECK-TLS4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG328]] +// CHECK-TLS4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !dbg [[DBG328]], !prof [[PROF119]] // CHECK-TLS4: init: -// CHECK-TLS4-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG327]] -// CHECK-TLS4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG327]] -// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG327]] -// CHECK-TLS4-NEXT: br label [[EXIT]], !dbg [[DBG327]] +// CHECK-TLS4-NEXT: store i8 1, ptr @__tls_guard, align 1, !dbg [[DBG328]] +// CHECK-TLS4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG328]] +// CHECK-TLS4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG328]] +// CHECK-TLS4-NEXT: br label [[EXIT]], !dbg [[DBG328]] // CHECK-TLS4: exit: // CHECK-TLS4-NEXT: ret void // @@ -5953,179 +5953,179 @@ // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init // SIMD4-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG115:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG118:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG120:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG121:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG119:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR3:[0-9]+]], !dbg [[DBG121:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG122:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG122:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 !dbg [[DBG123:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META123:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG126:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG128:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG128]] -// SIMD4-NEXT: ret void, !dbg [[DBG129:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG129:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG129]] +// SIMD4-NEXT: ret void, !dbg [[DBG130:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG132:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG133:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG134:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]], !dbg [[DBG134:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG135:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG135:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG136:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG136:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG138:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG139:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG137:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG139:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG140:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG140:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG141:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META141:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META145:![0-9]+]], metadata !DIExpression()), !dbg [[DBG146:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG146:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG146]] -// SIMD4-NEXT: ret void, !dbg [[DBG147:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG147:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG147]] +// SIMD4-NEXT: ret void, !dbg [[DBG148:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG148:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG149:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META149:![0-9]+]], metadata !DIExpression()), !dbg [[DBG150:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META150:![0-9]+]], metadata !DIExpression()), !dbg [[DBG151:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG151:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG152:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR3]], !dbg [[DBG152:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG153:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// SIMD4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG153:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG154:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD4-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154:![0-9]+]] -// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156:![0-9]+]] +// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155:![0-9]+]] +// SIMD4-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157:![0-9]+]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG157:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG158:![0-9]+]] // SIMD4: invoke.cont: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG158:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] // SIMD4: invoke.cont2: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG159:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG160:![0-9]+]] // SIMD4: invoke.cont3: -// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160:![0-9]+]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161:![0-9]+]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG161:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG162:![0-9]+]] // SIMD4: invoke.cont7: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG162:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] // SIMD4: invoke.cont8: -// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] +// SIMD4-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] // SIMD4-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG163:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG164:![0-9]+]] // SIMD4: invoke.cont9: -// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG164:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG164]] +// SIMD4-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG165:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG165]] // SIMD4: lpad: // SIMD4-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG165:![0-9]+]] -// SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG165]] -// SIMD4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG165]] -// SIMD4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG156]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG156]] +// SIMD4-NEXT: cleanup, !dbg [[DBG166:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG166]] +// SIMD4-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG166]] +// SIMD4-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG157]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG157]] // SIMD4: arraydestroy.body: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG156]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG156]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG156]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG156]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG157]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG157]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG157]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG157]] // SIMD4: arraydestroy.done4: -// SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG156]] +// SIMD4-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG157]] // SIMD4: lpad6: // SIMD4-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG165]] -// SIMD4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG165]] -// SIMD4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG165]] -// SIMD4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG160]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG160]] +// SIMD4-NEXT: cleanup, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG166]] +// SIMD4-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG166]] +// SIMD4-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG166]] +// SIMD4-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG161]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG161]] // SIMD4: arraydestroy.body11: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG160]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG160]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG160]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG160]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG161]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR3]], !dbg [[DBG161]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG161]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG161]] // SIMD4: arraydestroy.done15: -// SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG160]] +// SIMD4-NEXT: br label [[EHCLEANUP]], !dbg [[DBG161]] // SIMD4: ehcleanup: -// SIMD4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG154]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG154]] +// SIMD4-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG155]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG155]] // SIMD4: arraydestroy.body17: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG154]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG154]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG154]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG154]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG155]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR3]], !dbg [[DBG155]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG155]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG155]] // SIMD4: arraydestroy.done21: -// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG154]] +// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG155]] // SIMD4: eh.resume: -// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG154]] -// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG154]] -// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG154]] -// SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG154]] -// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG154]] +// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG155]] +// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG155]] +// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG155]] +// SIMD4-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG155]] +// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG155]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// SIMD4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG166:![0-9]+]] { +// SIMD4-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG167:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] -// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG171]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]] +// SIMD4-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG172]] // SIMD4: arraydestroy.body: -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG171]] -// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG171]] -// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG171]] -// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG171]] -// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG171]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG172]] +// SIMD4-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG172]] +// SIMD4-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]], !dbg [[DBG172]] +// SIMD4-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG172]] +// SIMD4-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG172]] // SIMD4: arraydestroy.done1: -// SIMD4-NEXT: ret void, !dbg [[DBG171]] +// SIMD4-NEXT: ret void, !dbg [[DBG172]] // // // SIMD4-LABEL: define {{[^@]+}}@main @@ -6136,302 +6136,302 @@ // SIMD4-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG174:![0-9]+]] -// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG174]], !prof [[PROF175:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG174:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG175:![0-9]+]] +// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG175]], !prof [[PROF176:![0-9]+]] // SIMD4: init.check: -// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG174]] +// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG175]] // SIMD4: init: -// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG176:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG177:![0-9]+]] // SIMD4-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP2]]) -// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG177:![0-9]+]] +// SIMD4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG178:![0-9]+]] // SIMD4: invoke.cont: -// SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG174]] +// SIMD4-NEXT: [[TMP3:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG175]] // SIMD4: init.end: -// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG178:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG179:![0-9]+]] -// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG180:![0-9]+]] -// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG181:![0-9]+]] -// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG181]] -// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG181]] -// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG182:![0-9]+]] -// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG183:![0-9]+]] -// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG183]] -// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG183]] -// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG184:![0-9]+]] -// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG185:![0-9]+]] -// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG185]] -// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG185]] -// SIMD4-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG186:![0-9]+]] -// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG187:![0-9]+]] -// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG187]] -// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG187]] -// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG188:![0-9]+]] -// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG189:![0-9]+]] -// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG189]] -// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG189]] -// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG190:![0-9]+]] -// SIMD4-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG191:![0-9]+]] -// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG191]] -// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG191]] -// SIMD4-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG192:![0-9]+]] -// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG192]] -// SIMD4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG193:![0-9]+]] -// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG193]] -// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG193]] -// SIMD4-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG194:![0-9]+]] -// SIMD4-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG195:![0-9]+]] -// SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG195]] -// SIMD4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG195]] -// SIMD4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] -// SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG197:![0-9]+]] +// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG179:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP4]], ptr [[RES]], align 4, !dbg [[DBG180:![0-9]+]] +// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @_ZZ4mainE2sm, align 8, !dbg [[DBG181:![0-9]+]] +// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG182:![0-9]+]] +// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG182]] +// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG182]] +// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG183:![0-9]+]] +// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG184:![0-9]+]] +// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG184]] +// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG184]] +// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG185:![0-9]+]] +// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG186:![0-9]+]] +// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG186]] +// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG186]] +// SIMD4-NEXT: [[TMP11:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG187:![0-9]+]] +// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG188:![0-9]+]] +// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP12]], [[TMP11]], !dbg [[DBG188]] +// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG188]] +// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG189:![0-9]+]] +// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG190:![0-9]+]] +// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG190]] +// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG190]] +// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG191:![0-9]+]] +// SIMD4-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG192:![0-9]+]] +// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG192]] +// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG192]] +// SIMD4-NEXT: [[TMP17:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG193:![0-9]+]] +// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP17]] to i32, !dbg [[DBG193]] +// SIMD4-NEXT: [[TMP18:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG194:![0-9]+]] +// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP18]], [[CONV]], !dbg [[DBG194]] +// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG194]] +// SIMD4-NEXT: [[TMP19:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG195:![0-9]+]] +// SIMD4-NEXT: [[TMP20:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG196:![0-9]+]] +// SIMD4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], [[TMP19]], !dbg [[DBG196]] +// SIMD4-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG196]] +// SIMD4-NEXT: [[TMP21:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG197:![0-9]+]] +// SIMD4-NEXT: ret i32 [[TMP21]], !dbg [[DBG198:![0-9]+]] // SIMD4: lpad: // SIMD4-NEXT: [[TMP22:%.*]] = landingpad { ptr, i32 } -// SIMD4-NEXT: cleanup, !dbg [[DBG198:![0-9]+]] -// SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG198]] -// SIMD4-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG198]] -// SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG198]] -// SIMD4-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG198]] -// SIMD4-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG174]] -// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG174]] +// SIMD4-NEXT: cleanup, !dbg [[DBG199:![0-9]+]] +// SIMD4-NEXT: [[TMP23:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 0, !dbg [[DBG199]] +// SIMD4-NEXT: store ptr [[TMP23]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG199]] +// SIMD4-NEXT: [[TMP24:%.*]] = extractvalue { ptr, i32 } [[TMP22]], 1, !dbg [[DBG199]] +// SIMD4-NEXT: store i32 [[TMP24]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG199]] +// SIMD4-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR3]], !dbg [[DBG175]] +// SIMD4-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG175]] // SIMD4: eh.resume: -// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG174]] -// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG174]] -// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG174]] -// SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG174]] -// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG174]] +// SIMD4-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG175]] +// SIMD4-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG175]] +// SIMD4-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG175]] +// SIMD4-NEXT: [[LPAD_VAL8:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG175]] +// SIMD4-NEXT: resume { ptr, i32 } [[LPAD_VAL8]], !dbg [[DBG175]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG199:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] align 2 !dbg [[DBG200:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] -// SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG205]] -// SIMD4-NEXT: ret void, !dbg [[DBG206:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG206:![0-9]+]] +// SIMD4-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG206]] +// SIMD4-NEXT: ret void, !dbg [[DBG207:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG207:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG208:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG209:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG210:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG211:![0-9]+]] +// SIMD4-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR3]], !dbg [[DBG211:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG212:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_Z6foobarv -// SIMD4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG212:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG213:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[RES:%.*]] = alloca i32, align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META213:![0-9]+]], metadata !DIExpression()), !dbg [[DBG214:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG215:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] -// SIMD4-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG217:![0-9]+]] -// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] -// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG218]] -// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG218]] -// SIMD4-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG219:![0-9]+]] -// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG220]] -// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG220]] -// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG221:![0-9]+]] -// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG222:![0-9]+]] -// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG222]] -// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG222]] -// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG223:![0-9]+]] -// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] -// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG224]] -// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG224]] -// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG225:![0-9]+]] -// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] -// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG226]] -// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG226]] -// SIMD4-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG227:![0-9]+]] -// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG227]] -// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] -// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG228]] -// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG228]] -// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG229:![0-9]+]] -// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG230]] -// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG230]] -// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG232:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr @_ZN6Static1sE, align 4, !dbg [[DBG216:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] +// SIMD4-NEXT: [[TMP1:%.*]] = load i32, ptr @_ZL3gs1, align 4, !dbg [[DBG218:![0-9]+]] +// SIMD4-NEXT: [[TMP2:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG219:![0-9]+]] +// SIMD4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[TMP1]], !dbg [[DBG219]] +// SIMD4-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG219]] +// SIMD4-NEXT: [[TMP3:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG220:![0-9]+]] +// SIMD4-NEXT: [[TMP4:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// SIMD4-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], [[TMP3]], !dbg [[DBG221]] +// SIMD4-NEXT: store i32 [[ADD1]], ptr [[RES]], align 4, !dbg [[DBG221]] +// SIMD4-NEXT: [[TMP5:%.*]] = load i32, ptr @gs3, align 4, !dbg [[DBG222:![0-9]+]] +// SIMD4-NEXT: [[TMP6:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] +// SIMD4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP6]], [[TMP5]], !dbg [[DBG223]] +// SIMD4-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG223]] +// SIMD4-NEXT: [[TMP7:%.*]] = load i32, ptr getelementptr inbounds ([2 x [3 x %struct.S1]], ptr @arr_x, i64 0, i64 1, i64 1), align 4, !dbg [[DBG224:![0-9]+]] +// SIMD4-NEXT: [[TMP8:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] +// SIMD4-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP7]], !dbg [[DBG225]] +// SIMD4-NEXT: store i32 [[ADD3]], ptr [[RES]], align 4, !dbg [[DBG225]] +// SIMD4-NEXT: [[TMP9:%.*]] = load i32, ptr @_ZN2STIiE2stE, align 4, !dbg [[DBG226:![0-9]+]] +// SIMD4-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] +// SIMD4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG227]] +// SIMD4-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG227]] +// SIMD4-NEXT: [[TMP11:%.*]] = load float, ptr @_ZN2STIfE2stE, align 4, !dbg [[DBG228:![0-9]+]] +// SIMD4-NEXT: [[CONV:%.*]] = fptosi float [[TMP11]] to i32, !dbg [[DBG228]] +// SIMD4-NEXT: [[TMP12:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG229:![0-9]+]] +// SIMD4-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP12]], [[CONV]], !dbg [[DBG229]] +// SIMD4-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG229]] +// SIMD4-NEXT: [[TMP13:%.*]] = load i32, ptr @_ZN2STI2S4E2stE, align 4, !dbg [[DBG230:![0-9]+]] +// SIMD4-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// SIMD4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG231]] +// SIMD4-NEXT: store i32 [[ADD6]], ptr [[RES]], align 4, !dbg [[DBG231]] +// SIMD4-NEXT: [[TMP15:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// SIMD4-NEXT: ret i32 [[TMP15]], !dbg [[DBG233:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@__cxx_global_var_init.3 -// SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG233:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG234:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234:![0-9]+]] -// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG234]] -// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG234]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235:![0-9]+]] +// SIMD4-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG235]] +// SIMD4-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG235]] // SIMD4: init.check: -// SIMD4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG234]] -// SIMD4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG235:![0-9]+]] -// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG234]] -// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG234]] +// SIMD4-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG235]] +// SIMD4-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG236:![0-9]+]] +// SIMD4-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR3]], !dbg [[DBG235]] +// SIMD4-NEXT: br label [[INIT_END]], !dbg [[DBG235]] // SIMD4: init.end: -// SIMD4-NEXT: ret void, !dbg [[DBG237:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG238:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG238:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 !dbg [[DBG239:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG241:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META240:![0-9]+]], metadata !DIExpression()), !dbg [[DBG242:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG244:![0-9]+]] -// SIMD4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG244]] -// SIMD4-NEXT: ret void, !dbg [[DBG245:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG245:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG245]] +// SIMD4-NEXT: ret void, !dbg [[DBG246:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG246:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG247:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META248:![0-9]+]], metadata !DIExpression()), !dbg [[DBG249:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG249:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG250:![0-9]+]] +// SIMD4-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]], !dbg [[DBG250:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG251:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG251:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG252:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META252:![0-9]+]], metadata !DIExpression()), !dbg [[DBG253:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META253:![0-9]+]], metadata !DIExpression()), !dbg [[DBG254:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG255:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG257:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG256]] -// SIMD4-NEXT: ret void, !dbg [[DBG258:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG258:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG257]] +// SIMD4-NEXT: ret void, !dbg [[DBG259:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG259:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG260:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META261:![0-9]+]], metadata !DIExpression()), !dbg [[DBG262:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG264:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG265:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG265:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG266:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG266:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG267:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META267:![0-9]+]], metadata !DIExpression()), !dbg [[DBG268:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META268:![0-9]+]], metadata !DIExpression()), !dbg [[DBG269:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG272:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG271]] -// SIMD4-NEXT: ret void, !dbg [[DBG273:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG272:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG273:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG272]] +// SIMD4-NEXT: ret void, !dbg [[DBG274:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG274:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG275:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META275:![0-9]+]], metadata !DIExpression()), !dbg [[DBG276:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG277:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG277:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG279:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG280:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG278:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG280:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG281:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG281:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG282:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META282:![0-9]+]], metadata !DIExpression()), !dbg [[DBG283:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META283:![0-9]+]], metadata !DIExpression()), !dbg [[DBG284:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG286:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG287:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG286]] -// SIMD4-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG287:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG288:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG287]] +// SIMD4-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG289:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG290:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META290:![0-9]+]], metadata !DIExpression()), !dbg [[DBG291:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG292:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG294:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG295:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG293:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG295:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG296:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG296:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG297:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] // SIMD4-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG301:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG301:![0-9]+]] -// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG302:![0-9]+]] -// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG301]] -// SIMD4-NEXT: ret void, !dbg [[DBG303:![0-9]+]] +// SIMD4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG302:![0-9]+]] +// SIMD4-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG303:![0-9]+]] +// SIMD4-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG302]] +// SIMD4-NEXT: ret void, !dbg [[DBG304:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG304:![0-9]+]] { +// SIMD4-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG305:![0-9]+]] { // SIMD4-NEXT: entry: // SIMD4-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // SIMD4-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META305:![0-9]+]], metadata !DIExpression()), !dbg [[DBG306:![0-9]+]] +// SIMD4-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META306:![0-9]+]], metadata !DIExpression()), !dbg [[DBG307:![0-9]+]] // SIMD4-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG307:![0-9]+]] -// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG309:![0-9]+]] -// SIMD4-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// SIMD4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG308:![0-9]+]] +// SIMD4-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG310:![0-9]+]] +// SIMD4-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // SIMD4-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG311:![0-9]+]] { +// SIMD4-SAME: () #[[ATTR0]] !dbg [[DBG312:![0-9]+]] { // SIMD4-NEXT: entry: -// SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG313:![0-9]+]] -// SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG313]] -// SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG313]] +// SIMD4-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG314:![0-9]+]] +// SIMD4-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG314]] +// SIMD4-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG314]] // SIMD4-NEXT: ret void // // @@ -6628,209 +6628,209 @@ // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init // DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG161:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG164:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG166:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG167:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG165:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG167:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG168:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG168:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG169:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META169:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG171:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG172:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG173:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG173:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG174:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG173]] -// DEBUG1-NEXT: ret void, !dbg [[DBG175:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG174:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG175:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG174]] +// DEBUG1-NEXT: ret void, !dbg [[DBG176:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG176:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG177:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META177:![0-9]+]], metadata !DIExpression()), !dbg [[DBG178:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META178:![0-9]+]], metadata !DIExpression()), !dbg [[DBG179:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG179:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG181:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG182:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG180:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG182:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG183:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.4 -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG183:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG184:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG184:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG186:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG187:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG185:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG187:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG188:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG188:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG189:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META189:![0-9]+]], metadata !DIExpression()), !dbg [[DBG191:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META190:![0-9]+]], metadata !DIExpression()), !dbg [[DBG192:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META192:![0-9]+]], metadata !DIExpression()), !dbg [[DBG193:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG194]] -// DEBUG1-NEXT: ret void, !dbg [[DBG195:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG195:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG195]] +// DEBUG1-NEXT: ret void, !dbg [[DBG196:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG196:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG197:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META197:![0-9]+]], metadata !DIExpression()), !dbg [[DBG198:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG199:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG199:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG200:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG200:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG201:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG201:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG202:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META202:![0-9]+]], metadata !DIExpression()), !dbg [[DBG203:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG204:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META205:![0-9]+]], metadata !DIExpression()), !dbg [[DBG206:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG206:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG207:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG206]] -// DEBUG1-NEXT: ret void, !dbg [[DBG208:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG207:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG208:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG207]] +// DEBUG1-NEXT: ret void, !dbg [[DBG209:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG209:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG210:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG211:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META211:![0-9]+]], metadata !DIExpression()), !dbg [[DBG212:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG214:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG215:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG213:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG215:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG216:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.5 -// DEBUG1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG216:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG217:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217:![0-9]+]] -// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219:![0-9]+]] +// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218:![0-9]+]] +// DEBUG1-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220:![0-9]+]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG220:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG221:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG221:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]] // DEBUG1: invoke.cont2: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG222:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG223:![0-9]+]] // DEBUG1: invoke.cont3: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] -// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223:![0-9]+]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224:![0-9]+]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// DEBUG1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG224:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG225:![0-9]+]] // DEBUG1: invoke.cont7: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// DEBUG1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG225:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]] // DEBUG1: invoke.cont8: -// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] +// DEBUG1-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]] // DEBUG1-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG226:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG227:![0-9]+]] // DEBUG1: invoke.cont9: -// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG227:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG227]] +// DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG228:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG228]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP1:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG228:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG228]] -// DEBUG1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG228]] -// DEBUG1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG219]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG219]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG219]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG229:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 0, !dbg [[DBG229]] +// DEBUG1-NEXT: store ptr [[TMP2]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP1]], 1, !dbg [[DBG229]] +// DEBUG1-NEXT: store i32 [[TMP3]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG220]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP4]], !dbg [[DBG220]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG220]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG219]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG219]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG219]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG219]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG219]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP4]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG220]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG220]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG220]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG220]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG220]] // DEBUG1: arraydestroy.done4: -// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG219]] +// DEBUG1-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG220]] // DEBUG1: lpad6: // DEBUG1-NEXT: [[TMP5:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG228]] -// DEBUG1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG228]] -// DEBUG1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG228]] -// DEBUG1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG223]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG223]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG223]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP6:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 0, !dbg [[DBG229]] +// DEBUG1-NEXT: store ptr [[TMP6]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP5]], 1, !dbg [[DBG229]] +// DEBUG1-NEXT: store i32 [[TMP7]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG229]] +// DEBUG1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG224]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP8]], !dbg [[DBG224]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG224]] // DEBUG1: arraydestroy.body11: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG223]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG223]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG223]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG223]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG223]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP8]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG224]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG224]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG224]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG224]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG224]] // DEBUG1: arraydestroy.done15: -// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG223]] +// DEBUG1-NEXT: br label [[EHCLEANUP]], !dbg [[DBG224]] // DEBUG1: ehcleanup: -// DEBUG1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG217]] -// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG217]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG217]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG217]] +// DEBUG1-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG218]] +// DEBUG1-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP9]], i64 0, i64 0, !dbg [[DBG218]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG218]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG218]] // DEBUG1: arraydestroy.body17: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG217]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG217]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG217]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG217]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG217]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG218]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG218]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG218]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG218]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG218]] // DEBUG1: arraydestroy.done21: -// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG217]] +// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG218]] // DEBUG1: eh.resume: -// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG217]] -// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG217]] -// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG217]] -// DEBUG1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG217]] -// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG217]] +// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG218]] +// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG218]] +// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG218]] +// DEBUG1-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG218]] +// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG218]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG229:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG230:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG233:![0-9]+]] -// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG233]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META233:![0-9]+]], metadata !DIExpression()), !dbg [[DBG234:![0-9]+]] +// DEBUG1-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG234]] // DEBUG1: arraydestroy.body: -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG233]] -// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG233]] -// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG233]] -// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG233]] -// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG233]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG234]] +// DEBUG1-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG234]] +// DEBUG1-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG234]] +// DEBUG1-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG234]] +// DEBUG1-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG234]] // DEBUG1: arraydestroy.done1: -// DEBUG1-NEXT: ret void, !dbg [[DBG233]] +// DEBUG1-NEXT: ret void, !dbg [[DBG234]] // // // DEBUG1-LABEL: define {{[^@]+}}@main @@ -6842,528 +6842,528 @@ // DEBUG1-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) // DEBUG1-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META234:![0-9]+]], metadata !DIExpression()), !dbg [[DBG235:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG236:![0-9]+]] -// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG236]] -// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG236]], !prof [[PROF237:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META235:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG237:![0-9]+]] +// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG237]] +// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG237]], !prof [[PROF238:![0-9]+]] // DEBUG1: init.check: -// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG236]] -// DEBUG1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG236]] -// DEBUG1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG236]] +// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG237]] +// DEBUG1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG237]] +// DEBUG1-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG237]] // DEBUG1: init: -// DEBUG1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG236]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7), !dbg [[DBG236]] -// DEBUG1-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG238:![0-9]+]] -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] -// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG239]] +// DEBUG1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG237]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..6, ptr null, ptr @.__kmpc_global_dtor_..7), !dbg [[DBG237]] +// DEBUG1-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG239:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG240:![0-9]+]] +// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG240]] // DEBUG1-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) -// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG240:![0-9]+]] +// DEBUG1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG241:![0-9]+]] // DEBUG1: invoke.cont: -// DEBUG1-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG236]] -// DEBUG1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG236]] -// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG236]] +// DEBUG1-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG237]] +// DEBUG1-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG237]] +// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG237]] // DEBUG1: init.end: -// DEBUG1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG241:![0-9]+]] -// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG242:![0-9]+]] -// DEBUG1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG242]] -// DEBUG1-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG243:![0-9]+]] -// DEBUG1-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG244:![0-9]+]] -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG245:![0-9]+]] -// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG245]] -// DEBUG1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG246:![0-9]+]] -// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG246]] -// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG246]] -// DEBUG1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG247:![0-9]+]] -// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG248:![0-9]+]] -// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG248]] -// DEBUG1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG249:![0-9]+]] -// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG249]] -// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG249]] -// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG250:![0-9]+]] -// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG251:![0-9]+]] -// DEBUG1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG251]] -// DEBUG1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG251]] -// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG252:![0-9]+]] -// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG253:![0-9]+]] -// DEBUG1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG253]] -// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG254:![0-9]+]] -// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG254]] -// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG254]] -// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG255:![0-9]+]] -// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG255]] -// DEBUG1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG255]] -// DEBUG1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG256:![0-9]+]] -// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG256]] -// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG257:![0-9]+]] -// DEBUG1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG257]] -// DEBUG1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG257]] -// DEBUG1-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG258:![0-9]+]] -// DEBUG1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG258]] -// DEBUG1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG259:![0-9]+]] -// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG259]] -// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG259]] -// DEBUG1-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG260:![0-9]+]] -// DEBUG1-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG260]] -// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG260]] -// DEBUG1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG261:![0-9]+]] -// DEBUG1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG261]] -// DEBUG1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG261]] -// DEBUG1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG262:![0-9]+]] -// DEBUG1-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] -// DEBUG1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG263]] -// DEBUG1-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG264:![0-9]+]] -// DEBUG1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG264]] -// DEBUG1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG264]] -// DEBUG1-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG265:![0-9]+]] -// DEBUG1-NEXT: ret i32 [[TMP32]], !dbg [[DBG266:![0-9]+]] +// DEBUG1-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG242:![0-9]+]] +// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG243:![0-9]+]] +// DEBUG1-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG243]] +// DEBUG1-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG244:![0-9]+]] +// DEBUG1-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG245:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG246:![0-9]+]] +// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG246]] +// DEBUG1-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG247:![0-9]+]] +// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG247]] +// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG247]] +// DEBUG1-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG248:![0-9]+]] +// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG249:![0-9]+]] +// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG249]] +// DEBUG1-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG250:![0-9]+]] +// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG250]] +// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG250]] +// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG251:![0-9]+]] +// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG252:![0-9]+]] +// DEBUG1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG252]] +// DEBUG1-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG252]] +// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG253:![0-9]+]] +// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG254:![0-9]+]] +// DEBUG1-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG254]] +// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG255:![0-9]+]] +// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG255]] +// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG255]] +// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG256:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], inrange i64 0, i64 1, !dbg [[DBG256]] +// DEBUG1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG256]] +// DEBUG1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG257:![0-9]+]] +// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG257]] +// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG258:![0-9]+]] +// DEBUG1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG258]] +// DEBUG1-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG258]] +// DEBUG1-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG259:![0-9]+]] +// DEBUG1-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG259]] +// DEBUG1-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG260:![0-9]+]] +// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG260]] +// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG260]] +// DEBUG1-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG261:![0-9]+]] +// DEBUG1-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG261]] +// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG261]] +// DEBUG1-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG262:![0-9]+]] +// DEBUG1-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG262]] +// DEBUG1-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG262]] +// DEBUG1-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG263:![0-9]+]] +// DEBUG1-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG264:![0-9]+]] +// DEBUG1-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG264]] +// DEBUG1-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG265:![0-9]+]] +// DEBUG1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG265]] +// DEBUG1-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG265]] +// DEBUG1-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG266:![0-9]+]] +// DEBUG1-NEXT: ret i32 [[TMP32]], !dbg [[DBG267:![0-9]+]] // DEBUG1: lpad: // DEBUG1-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } -// DEBUG1-NEXT: cleanup, !dbg [[DBG267:![0-9]+]] -// DEBUG1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG267]] -// DEBUG1-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG267]] -// DEBUG1-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG267]] -// DEBUG1-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG267]] -// DEBUG1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG236]] -// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG236]] +// DEBUG1-NEXT: cleanup, !dbg [[DBG268:![0-9]+]] +// DEBUG1-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG268]] +// DEBUG1-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG268]] +// DEBUG1-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG268]] +// DEBUG1-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG268]] +// DEBUG1-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG237]] +// DEBUG1-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG237]] // DEBUG1: eh.resume: -// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG236]] -// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG236]] -// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG236]] -// DEBUG1-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG236]] -// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG236]] +// DEBUG1-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG237]] +// DEBUG1-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG237]] +// DEBUG1-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG237]] +// DEBUG1-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG237]] +// DEBUG1-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG237]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..6 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG268:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG269:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]) // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG271:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG272:![0-9]+]] -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] -// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG273]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG274:![0-9]+]] -// DEBUG1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG271]] -// DEBUG1-NEXT: ret ptr [[TMP5]], !dbg [[DBG271]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META270:![0-9]+]], metadata !DIExpression()), !dbg [[DBG271:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG273:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG274:![0-9]+]] +// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG274]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG275:![0-9]+]] +// DEBUG1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG272]] +// DEBUG1-NEXT: ret ptr [[TMP5]], !dbg [[DBG272]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG275:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG276:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META276:![0-9]+]], metadata !DIExpression()), !dbg [[DBG278:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META277:![0-9]+]], metadata !DIExpression()), !dbg [[DBG279:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META279:![0-9]+]], metadata !DIExpression()), !dbg [[DBG280:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META280:![0-9]+]], metadata !DIExpression()), !dbg [[DBG281:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG281:![0-9]+]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG281]] -// DEBUG1-NEXT: ret void, !dbg [[DBG282:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG282:![0-9]+]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG282]] +// DEBUG1-NEXT: ret void, !dbg [[DBG283:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..7 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG283:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG284:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META284:![0-9]+]], metadata !DIExpression()), !dbg [[DBG285:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG285]] -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR4]], !dbg [[DBG285]] -// DEBUG1-NEXT: ret void, !dbg [[DBG286:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META285:![0-9]+]], metadata !DIExpression()), !dbg [[DBG286:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG286]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR4]], !dbg [[DBG286]] +// DEBUG1-NEXT: ret void, !dbg [[DBG287:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG287:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG288:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META288:![0-9]+]], metadata !DIExpression()), !dbg [[DBG289:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META289:![0-9]+]], metadata !DIExpression()), !dbg [[DBG290:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG290:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG291:![0-9]+]] +// DEBUG1-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG291:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG292:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG292:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG293:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META293:![0-9]+]], metadata !DIExpression()), !dbg [[DBG294:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META294:![0-9]+]], metadata !DIExpression()), !dbg [[DBG295:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META295:![0-9]+]], metadata !DIExpression()), !dbg [[DBG296:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META296:![0-9]+]], metadata !DIExpression()), !dbg [[DBG297:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG297:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG298:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG297]] -// DEBUG1-NEXT: ret void, !dbg [[DBG299:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG298:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG299:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG298]] +// DEBUG1-NEXT: ret void, !dbg [[DBG300:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG300:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG301:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META301:![0-9]+]], metadata !DIExpression()), !dbg [[DBG302:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META302:![0-9]+]], metadata !DIExpression()), !dbg [[DBG303:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG303:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG305:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG306:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG304:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG306:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG307:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_Z6foobarv -// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG307:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG308:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[RES:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]) -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META308:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG310:![0-9]+]] -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG311:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG311]] -// DEBUG1-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG312:![0-9]+]] -// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG313:![0-9]+]] -// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG314:![0-9]+]] -// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG314]] -// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG315:![0-9]+]] -// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG315]] -// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG315]] -// DEBUG1-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG316:![0-9]+]] -// DEBUG1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG317:![0-9]+]] -// DEBUG1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG317]] -// DEBUG1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG317]] -// DEBUG1-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG318:![0-9]+]] -// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG319:![0-9]+]] -// DEBUG1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG319]] -// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG320:![0-9]+]] -// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG320]] -// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG320]] -// DEBUG1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG321:![0-9]+]] -// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG321]] -// DEBUG1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG321]] -// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG322:![0-9]+]] -// DEBUG1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG322]] -// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG323:![0-9]+]] -// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG323]] -// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG323]] -// DEBUG1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG324:![0-9]+]] -// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG324]] -// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG325:![0-9]+]] -// DEBUG1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG325]] -// DEBUG1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG325]] -// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG326:![0-9]+]] -// DEBUG1-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG326]] -// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG326]] -// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG327:![0-9]+]] -// DEBUG1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG327]] -// DEBUG1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG327]] -// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG328:![0-9]+]] -// DEBUG1-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG329:![0-9]+]] -// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG329]] -// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG330:![0-9]+]] -// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG330]] -// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG330]] -// DEBUG1-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG331:![0-9]+]] -// DEBUG1-NEXT: ret i32 [[TMP23]], !dbg [[DBG332:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META309:![0-9]+]], metadata !DIExpression()), !dbg [[DBG310:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG311:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG312:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG312]] +// DEBUG1-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG313:![0-9]+]] +// DEBUG1-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG314:![0-9]+]] +// DEBUG1-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG315:![0-9]+]] +// DEBUG1-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG315]] +// DEBUG1-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG316:![0-9]+]] +// DEBUG1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG316]] +// DEBUG1-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG316]] +// DEBUG1-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG317:![0-9]+]] +// DEBUG1-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG318:![0-9]+]] +// DEBUG1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG318]] +// DEBUG1-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG318]] +// DEBUG1-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG319:![0-9]+]] +// DEBUG1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG320:![0-9]+]] +// DEBUG1-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG320]] +// DEBUG1-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG321:![0-9]+]] +// DEBUG1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG321]] +// DEBUG1-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG321]] +// DEBUG1-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG322:![0-9]+]] +// DEBUG1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], inrange i64 0, i64 1, !dbg [[DBG322]] +// DEBUG1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG322]] +// DEBUG1-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG323:![0-9]+]] +// DEBUG1-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG323]] +// DEBUG1-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG324:![0-9]+]] +// DEBUG1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG324]] +// DEBUG1-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG324]] +// DEBUG1-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG325:![0-9]+]] +// DEBUG1-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG325]] +// DEBUG1-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG326:![0-9]+]] +// DEBUG1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG326]] +// DEBUG1-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG326]] +// DEBUG1-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG327:![0-9]+]] +// DEBUG1-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG327]] +// DEBUG1-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG327]] +// DEBUG1-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG328:![0-9]+]] +// DEBUG1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG328]] +// DEBUG1-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG328]] +// DEBUG1-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG329:![0-9]+]] +// DEBUG1-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG330:![0-9]+]] +// DEBUG1-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG330]] +// DEBUG1-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG331:![0-9]+]] +// DEBUG1-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG331]] +// DEBUG1-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG331]] +// DEBUG1-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG332:![0-9]+]] +// DEBUG1-NEXT: ret i32 [[TMP23]], !dbg [[DBG333:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@__cxx_global_var_init.8 -// DEBUG1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG333:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG334:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG334:![0-9]+]] -// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG334]] -// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG334]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG335:![0-9]+]] +// DEBUG1-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG335]] +// DEBUG1-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG335]] // DEBUG1: init.check: -// DEBUG1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG334]] -// DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG334]] -// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10), !dbg [[DBG334]] -// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG335:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG334]] -// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG334]] +// DEBUG1-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG335]] +// DEBUG1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG335]] +// DEBUG1-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..9, ptr null, ptr @.__kmpc_global_dtor_..10), !dbg [[DBG335]] +// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG336:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG335]] +// DEBUG1-NEXT: br label [[INIT_END]], !dbg [[DBG335]] // DEBUG1: init.end: -// DEBUG1-NEXT: ret void, !dbg [[DBG337:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG338:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..9 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG338:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG339:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META339:![0-9]+]], metadata !DIExpression()), !dbg [[DBG340:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG341:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG342:![0-9]+]] -// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG341]] -// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG341]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META340:![0-9]+]], metadata !DIExpression()), !dbg [[DBG341:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG342:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG343:![0-9]+]] +// DEBUG1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG342]] +// DEBUG1-NEXT: ret ptr [[TMP2]], !dbg [[DBG342]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG343:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG344:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META344:![0-9]+]], metadata !DIExpression()), !dbg [[DBG346:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META345:![0-9]+]], metadata !DIExpression()), !dbg [[DBG347:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META347:![0-9]+]], metadata !DIExpression()), !dbg [[DBG348:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META348:![0-9]+]], metadata !DIExpression()), !dbg [[DBG349:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG349:![0-9]+]] -// DEBUG1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG349]] -// DEBUG1-NEXT: ret void, !dbg [[DBG350:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG350:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG350]] +// DEBUG1-NEXT: ret void, !dbg [[DBG351:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..10 -// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG351:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG352:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META352:![0-9]+]], metadata !DIExpression()), !dbg [[DBG353:![0-9]+]] -// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG353]] -// DEBUG1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR4]], !dbg [[DBG353]] -// DEBUG1-NEXT: ret void, !dbg [[DBG354:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META353:![0-9]+]], metadata !DIExpression()), !dbg [[DBG354:![0-9]+]] +// DEBUG1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG354]] +// DEBUG1-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR4]], !dbg [[DBG354]] +// DEBUG1-NEXT: ret void, !dbg [[DBG355:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG355:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG356:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META356:![0-9]+]], metadata !DIExpression()), !dbg [[DBG357:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META357:![0-9]+]], metadata !DIExpression()), !dbg [[DBG358:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG358:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG359:![0-9]+]] +// DEBUG1-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG359:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG360:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG360:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG361:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META361:![0-9]+]], metadata !DIExpression()), !dbg [[DBG362:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META362:![0-9]+]], metadata !DIExpression()), !dbg [[DBG363:![0-9]+]] // DEBUG1-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META363:![0-9]+]], metadata !DIExpression()), !dbg [[DBG364:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META364:![0-9]+]], metadata !DIExpression()), !dbg [[DBG365:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG365:![0-9]+]] -// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG366:![0-9]+]] -// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG365]] -// DEBUG1-NEXT: ret void, !dbg [[DBG367:![0-9]+]] +// DEBUG1-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG366:![0-9]+]] +// DEBUG1-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG367:![0-9]+]] +// DEBUG1-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG366]] +// DEBUG1-NEXT: ret void, !dbg [[DBG368:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG368:![0-9]+]] { +// DEBUG1-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG369:![0-9]+]] { // DEBUG1-NEXT: entry: // DEBUG1-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG1-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META369:![0-9]+]], metadata !DIExpression()), !dbg [[DBG370:![0-9]+]] +// DEBUG1-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META370:![0-9]+]], metadata !DIExpression()), !dbg [[DBG371:![0-9]+]] // DEBUG1-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG371:![0-9]+]] -// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG373:![0-9]+]] -// DEBUG1-NEXT: ret void, !dbg [[DBG374:![0-9]+]] +// DEBUG1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG372:![0-9]+]] +// DEBUG1-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG374:![0-9]+]] +// DEBUG1-NEXT: ret void, !dbg [[DBG375:![0-9]+]] // // // DEBUG1-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG375:![0-9]+]] { +// DEBUG1-SAME: () #[[ATTR0]] !dbg [[DBG376:![0-9]+]] { // DEBUG1-NEXT: entry: -// DEBUG1-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG376:![0-9]+]] -// DEBUG1-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG376]] -// DEBUG1-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG376]] -// DEBUG1-NEXT: call void @__cxx_global_var_init.5(), !dbg [[DBG376]] -// DEBUG1-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG376]] +// DEBUG1-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG377:![0-9]+]] +// DEBUG1-NEXT: call void @.__omp_threadprivate_init_.(), !dbg [[DBG377]] +// DEBUG1-NEXT: call void @__cxx_global_var_init.4(), !dbg [[DBG377]] +// DEBUG1-NEXT: call void @__cxx_global_var_init.5(), !dbg [[DBG377]] +// DEBUG1-NEXT: call void @.__omp_threadprivate_init_..3(), !dbg [[DBG377]] // DEBUG1-NEXT: ret void // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init // DEBUG2-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG116:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG119:![0-9]+]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG119]] -// DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG120:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4:[0-9]+]], !dbg [[DBG119]] -// DEBUG2-NEXT: ret void, !dbg [[DBG122:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG120:![0-9]+]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB1]], ptr @_ZL3gs1, ptr @.__kmpc_global_ctor_., ptr null, ptr @.__kmpc_global_dtor_.), !dbg [[DBG120]] +// DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @_ZL3gs1, i32 noundef 5), !dbg [[DBG121:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S1D1Ev, ptr @_ZL3gs1, ptr @__dso_handle) #[[ATTR4:[0-9]+]], !dbg [[DBG120]] +// DEBUG2-NEXT: ret void, !dbg [[DBG123:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_. -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG123:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG124:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META125:![0-9]+]], metadata !DIExpression()), !dbg [[DBG127:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG128:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG129:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG128]] -// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG128]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG128:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG129:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]], i32 noundef 5), !dbg [[DBG130:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG129]] +// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG129]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG130:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 !dbg [[DBG131:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META131:![0-9]+]], metadata !DIExpression()), !dbg [[DBG133:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META132:![0-9]+]], metadata !DIExpression()), !dbg [[DBG134:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META134:![0-9]+]], metadata !DIExpression()), !dbg [[DBG135:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META135:![0-9]+]], metadata !DIExpression()), !dbg [[DBG136:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG136:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG136]] -// DEBUG2-NEXT: ret void, !dbg [[DBG137:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG137:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1C2Ei(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG137]] +// DEBUG2-NEXT: ret void, !dbg [[DBG138:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_. -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG138:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG139:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META139:![0-9]+]], metadata !DIExpression()), !dbg [[DBG140:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG140]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR4]], !dbg [[DBG140]] -// DEBUG2-NEXT: ret void, !dbg [[DBG141:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG141]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[TMP1]]) #[[ATTR4]], !dbg [[DBG141]] +// DEBUG2-NEXT: ret void, !dbg [[DBG142:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG142:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] comdat align 2 !dbg [[DBG143:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META143:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META144:![0-9]+]], metadata !DIExpression()), !dbg [[DBG145:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG145:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG146:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S1D2Ev(ptr noundef nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]], !dbg [[DBG146:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG147:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.1 -// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG147:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG148:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG148:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG150:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG151:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2C1Ei(ptr noundef nonnull align 8 dereferenceable(16) @_ZL3gs2, i32 noundef 27), !dbg [[DBG149:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S2D1Ev, ptr @_ZL3gs2, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG151:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG152:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG152:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG153:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META153:![0-9]+]], metadata !DIExpression()), !dbg [[DBG155:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG156:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META156:![0-9]+]], metadata !DIExpression()), !dbg [[DBG157:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG158:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG158]] -// DEBUG2-NEXT: ret void, !dbg [[DBG159:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG159:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2C2Ei(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG159]] +// DEBUG2-NEXT: ret void, !dbg [[DBG160:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG160:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG161:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META162:![0-9]+]], metadata !DIExpression()), !dbg [[DBG163:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG163:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG164:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S2D2Ev(ptr noundef nonnull align 8 dereferenceable(16) [[THIS1]]) #[[ATTR4]], !dbg [[DBG164:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG165:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.2 -// DEBUG2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG165:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG166:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT1:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[EXN_SLOT:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT5:%.*]] = alloca ptr, align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG166:![0-9]+]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4), !dbg [[DBG166]] -// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167:![0-9]+]] -// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG167:![0-9]+]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB3]], ptr @arr_x, ptr @.__kmpc_global_ctor_..3, ptr null, ptr @.__kmpc_global_dtor_..4), !dbg [[DBG167]] +// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168:![0-9]+]] +// DEBUG2-NEXT: store ptr @arr_x, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170:![0-9]+]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) @arr_x, i32 noundef 1) -// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG170:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG171:![0-9]+]] // DEBUG2: invoke.cont: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 1), i32 noundef 2) -// DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG171:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT2:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]] // DEBUG2: invoke.cont2: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr @arr_x, i64 2), i32 noundef 3) -// DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG172:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG173:![0-9]+]] // DEBUG2: invoke.cont3: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] -// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173:![0-9]+]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174:![0-9]+]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i32 noundef 4) -// DEBUG2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG174:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT7:%.*]] unwind label [[LPAD6:%.*]], !dbg [[DBG175:![0-9]+]] // DEBUG2: invoke.cont7: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 1), i32 noundef 5) -// DEBUG2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG175:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT8:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]] // DEBUG2: invoke.cont8: -// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] +// DEBUG2-NEXT: store ptr getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) getelementptr inbounds ([[STRUCT_S1]], ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), i64 2), i32 noundef 6) -// DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG176:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT9:%.*]] unwind label [[LPAD6]], !dbg [[DBG177:![0-9]+]] // DEBUG2: invoke.cont9: -// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG166]] -// DEBUG2-NEXT: ret void, !dbg [[DBG166]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__cxa_atexit(ptr @__cxx_global_array_dtor, ptr null, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG167]] +// DEBUG2-NEXT: ret void, !dbg [[DBG167]] // DEBUG2: lpad: // DEBUG2-NEXT: [[TMP2:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG177:![0-9]+]] -// DEBUG2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG177]] -// DEBUG2-NEXT: store ptr [[TMP3]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1, !dbg [[DBG177]] -// DEBUG2-NEXT: store i32 [[TMP4]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG169]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP5]], !dbg [[DBG169]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG169]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG178:![0-9]+]] +// DEBUG2-NEXT: [[TMP3:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 0, !dbg [[DBG178]] +// DEBUG2-NEXT: store ptr [[TMP3]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP2]], 1, !dbg [[DBG178]] +// DEBUG2-NEXT: store i32 [[TMP4]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT1]], align 8, !dbg [[DBG170]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr @arr_x, [[TMP5]], !dbg [[DBG170]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE4:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG170]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG169]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG169]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG169]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG169]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG169]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP5]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG170]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG170]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG170]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG170]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE4]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG170]] // DEBUG2: arraydestroy.done4: -// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG169]] +// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG170]] // DEBUG2: lpad6: // DEBUG2-NEXT: [[TMP6:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 0, !dbg [[DBG177]] -// DEBUG2-NEXT: store ptr [[TMP7]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 1, !dbg [[DBG177]] -// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG177]] -// DEBUG2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG173]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP9]], !dbg [[DBG173]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG173]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP7:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 0, !dbg [[DBG178]] +// DEBUG2-NEXT: store ptr [[TMP7]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP6]], 1, !dbg [[DBG178]] +// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG178]] +// DEBUG2-NEXT: [[TMP9:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT5]], align 8, !dbg [[DBG174]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY10:%.*]] = icmp eq ptr getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), [[TMP9]], !dbg [[DBG174]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY10]], label [[ARRAYDESTROY_DONE15:%.*]], label [[ARRAYDESTROY_BODY11:%.*]], !dbg [[DBG174]] // DEBUG2: arraydestroy.body11: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG173]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG173]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG173]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG173]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG173]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST12:%.*]] = phi ptr [ [[TMP9]], [[LPAD6]] ], [ [[ARRAYDESTROY_ELEMENT13:%.*]], [[ARRAYDESTROY_BODY11]] ], !dbg [[DBG174]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT13]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST12]], i64 -1, !dbg [[DBG174]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT13]]) #[[ATTR4]], !dbg [[DBG174]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE14:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT13]], getelementptr inbounds ([3 x %struct.S1], ptr @arr_x, i64 1), !dbg [[DBG174]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE14]], label [[ARRAYDESTROY_DONE15]], label [[ARRAYDESTROY_BODY11]], !dbg [[DBG174]] // DEBUG2: arraydestroy.done15: -// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG173]] +// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG174]] // DEBUG2: ehcleanup: -// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG167]] -// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP10]], i64 0, i64 0, !dbg [[DBG167]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG167]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG167]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG168]] +// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP10]], i64 0, i64 0, !dbg [[DBG168]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr @arr_x, [[PAD_ARRAYEND]], !dbg [[DBG168]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG168]] // DEBUG2: arraydestroy.body17: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG167]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG167]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG167]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG167]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG167]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG168]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG168]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG168]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], @arr_x, !dbg [[DBG168]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG168]] // DEBUG2: arraydestroy.done21: -// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG167]] +// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG168]] // DEBUG2: eh.resume: -// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG167]] -// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG167]] -// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG167]] -// DEBUG2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG167]] -// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG167]] +// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG168]] +// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG168]] +// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG168]] +// DEBUG2-NEXT: [[LPAD_VAL22:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG168]] +// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL22]], !dbg [[DBG168]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..3 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG178:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] personality ptr @__gxx_personality_v0 !dbg [[DBG179:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT:%.*]] = alloca ptr, align 8 @@ -7372,136 +7372,136 @@ // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[ARRAYINIT_ENDOFINIT9:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG181:![0-9]+]] -// DEBUG2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG182:![0-9]+]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_BEGIN]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG183:![0-9]+]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_BEGIN1]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META180:![0-9]+]], metadata !DIExpression()), !dbg [[DBG181:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG182:![0-9]+]] +// DEBUG2-NEXT: [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP1]], i64 0, i64 0, !dbg [[DBG183:![0-9]+]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_BEGIN]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYINIT_BEGIN1:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG184:![0-9]+]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_BEGIN1]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN1]], i32 noundef 1) -// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG184:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG185:![0-9]+]] // DEBUG2: invoke.cont: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG183]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[ARRAYINIT_BEGIN1]], i64 1, !dbg [[DBG184]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 noundef 2) -// DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG185:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT3:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]] // DEBUG2: invoke.cont3: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG183]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT4]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT4:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT]], i64 1, !dbg [[DBG184]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT4]], ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT4]], i32 noundef 3) -// DEBUG2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG186:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT5:%.*]] unwind label [[LPAD]], !dbg [[DBG187:![0-9]+]] // DEBUG2: invoke.cont5: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG182]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT7]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG187:![0-9]+]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_BEGIN8]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT7:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 1, !dbg [[DBG183]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT7]], ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYINIT_BEGIN8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_ELEMENT7]], i64 0, i64 0, !dbg [[DBG188:![0-9]+]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_BEGIN8]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN8]], i32 noundef 4) -// DEBUG2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG188:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT11:%.*]] unwind label [[LPAD10:%.*]], !dbg [[DBG189:![0-9]+]] // DEBUG2: invoke.cont11: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG187]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT12:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_BEGIN8]], i64 1, !dbg [[DBG188]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT12]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT12]], i32 noundef 5) -// DEBUG2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG189:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT13:%.*]] unwind label [[LPAD10]], !dbg [[DBG190:![0-9]+]] // DEBUG2: invoke.cont13: -// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG187]] -// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT14]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYINIT_ELEMENT14:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYINIT_ELEMENT12]], i64 1, !dbg [[DBG188]] +// DEBUG2-NEXT: store ptr [[ARRAYINIT_ELEMENT14]], ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]] // DEBUG2-NEXT: invoke void @_ZN2S1C1Ei(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT14]], i32 noundef 6) -// DEBUG2-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG190:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT15:%.*]] unwind label [[LPAD10]], !dbg [[DBG191:![0-9]+]] // DEBUG2: invoke.cont15: -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG181]] -// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG182]] +// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG182]] // DEBUG2: lpad: // DEBUG2-NEXT: [[TMP3:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG180]] -// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[DBG180]] -// DEBUG2-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG180]] -// DEBUG2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[DBG180]] -// DEBUG2-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG180]] -// DEBUG2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG183]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN1]], [[TMP6]], !dbg [[DBG183]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG183]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP4:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 0, !dbg [[DBG181]] +// DEBUG2-NEXT: store ptr [[TMP4]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP5:%.*]] = extractvalue { ptr, i32 } [[TMP3]], 1, !dbg [[DBG181]] +// DEBUG2-NEXT: store i32 [[TMP5]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP6:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT2]], align 8, !dbg [[DBG184]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN1]], [[TMP6]], !dbg [[DBG184]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY]], label [[ARRAYDESTROY_DONE6:%.*]], label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG184]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG183]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG183]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG183]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG183]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP6]], [[LPAD]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG184]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG184]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG184]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[ARRAYINIT_BEGIN1]], !dbg [[DBG184]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE6]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG184]] // DEBUG2: arraydestroy.done6: -// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG183]] +// DEBUG2-NEXT: br label [[EHCLEANUP:%.*]], !dbg [[DBG184]] // DEBUG2: lpad10: // DEBUG2-NEXT: [[TMP7:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG180]] -// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[DBG180]] -// DEBUG2-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG180]] -// DEBUG2-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[DBG180]] -// DEBUG2-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG180]] -// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG187]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN8]], [[TMP10]], !dbg [[DBG187]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG187]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP8:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 0, !dbg [[DBG181]] +// DEBUG2-NEXT: store ptr [[TMP8]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP9:%.*]] = extractvalue { ptr, i32 } [[TMP7]], 1, !dbg [[DBG181]] +// DEBUG2-NEXT: store i32 [[TMP9]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG181]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT9]], align 8, !dbg [[DBG188]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY16:%.*]] = icmp eq ptr [[ARRAYINIT_BEGIN8]], [[TMP10]], !dbg [[DBG188]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY16]], label [[ARRAYDESTROY_DONE21:%.*]], label [[ARRAYDESTROY_BODY17:%.*]], !dbg [[DBG188]] // DEBUG2: arraydestroy.body17: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP10]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG187]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG187]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG187]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG187]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG187]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST18:%.*]] = phi ptr [ [[TMP10]], [[LPAD10]] ], [ [[ARRAYDESTROY_ELEMENT19:%.*]], [[ARRAYDESTROY_BODY17]] ], !dbg [[DBG188]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT19]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST18]], i64 -1, !dbg [[DBG188]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT19]]) #[[ATTR4]], !dbg [[DBG188]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE20:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT19]], [[ARRAYINIT_BEGIN8]], !dbg [[DBG188]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE20]], label [[ARRAYDESTROY_DONE21]], label [[ARRAYDESTROY_BODY17]], !dbg [[DBG188]] // DEBUG2: arraydestroy.done21: -// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG187]] +// DEBUG2-NEXT: br label [[EHCLEANUP]], !dbg [[DBG188]] // DEBUG2: ehcleanup: -// DEBUG2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG182]] -// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG182]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]], !dbg [[DBG182]] +// DEBUG2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[ARRAYINIT_ENDOFINIT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[PAD_ARRAYBEGIN:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYINIT_BEGIN]], i64 0, i64 0, !dbg [[DBG183]] +// DEBUG2-NEXT: [[PAD_ARRAYEND:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[TMP11]], i64 0, i64 0, !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ISEMPTY22:%.*]] = icmp eq ptr [[PAD_ARRAYBEGIN]], [[PAD_ARRAYEND]], !dbg [[DBG183]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_ISEMPTY22]], label [[ARRAYDESTROY_DONE27:%.*]], label [[ARRAYDESTROY_BODY23:%.*]], !dbg [[DBG183]] // DEBUG2: arraydestroy.body23: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG182]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG182]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG182]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG182]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST24:%.*]] = phi ptr [ [[PAD_ARRAYEND]], [[EHCLEANUP]] ], [ [[ARRAYDESTROY_ELEMENT25:%.*]], [[ARRAYDESTROY_BODY23]] ], !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT25]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST24]], i64 -1, !dbg [[DBG183]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT25]]) #[[ATTR4]], !dbg [[DBG183]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE26:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT25]], [[PAD_ARRAYBEGIN]], !dbg [[DBG183]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE26]], label [[ARRAYDESTROY_DONE27]], label [[ARRAYDESTROY_BODY23]], !dbg [[DBG183]] // DEBUG2: arraydestroy.done27: -// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG182]] +// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG183]] // DEBUG2: eh.resume: -// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG182]] -// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG182]] -// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG182]] -// DEBUG2-NEXT: [[LPAD_VAL28:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG182]] -// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL28]], !dbg [[DBG182]] +// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG183]] +// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG183]] +// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG183]] +// DEBUG2-NEXT: [[LPAD_VAL28:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG183]] +// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL28]], !dbg [[DBG183]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..4 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG191:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG192:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META192:![0-9]+]], metadata !DIExpression()), !dbg [[DBG193:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG193]] -// DEBUG2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[DBG193]] -// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG193]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META193:![0-9]+]], metadata !DIExpression()), !dbg [[DBG194:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG194]] +// DEBUG2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP1]], i64 6, !dbg [[DBG194]] +// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG194]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG193]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG193]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG193]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG193]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG193]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG194]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG194]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG194]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], [[TMP1]], !dbg [[DBG194]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG194]] // DEBUG2: arraydestroy.done1: -// DEBUG2-NEXT: ret void, !dbg [[DBG194:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG195:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG195:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG196:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META198:![0-9]+]], metadata !DIExpression()), !dbg [[DBG199:![0-9]+]] -// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG199]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META199:![0-9]+]], metadata !DIExpression()), !dbg [[DBG200:![0-9]+]] +// DEBUG2-NEXT: br label [[ARRAYDESTROY_BODY:%.*]], !dbg [[DBG200]] // DEBUG2: arraydestroy.body: -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG199]] -// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG199]] -// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG199]] -// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG199]] -// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG199]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi ptr [ getelementptr inbounds ([[STRUCT_S1:%.*]], ptr @arr_x, i64 6), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ], !dbg [[DBG200]] +// DEBUG2-NEXT: [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYDESTROY_ELEMENTPAST]], i64 -1, !dbg [[DBG200]] +// DEBUG2-NEXT: call void @_ZN2S1D1Ev(ptr noundef nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]], !dbg [[DBG200]] +// DEBUG2-NEXT: [[ARRAYDESTROY_DONE:%.*]] = icmp eq ptr [[ARRAYDESTROY_ELEMENT]], @arr_x, !dbg [[DBG200]] +// DEBUG2-NEXT: br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]], !dbg [[DBG200]] // DEBUG2: arraydestroy.done1: -// DEBUG2-NEXT: ret void, !dbg [[DBG199]] +// DEBUG2-NEXT: ret void, !dbg [[DBG200]] // // // DEBUG2-LABEL: define {{[^@]+}}@main @@ -7513,388 +7513,388 @@ // DEBUG2-NEXT: [[EHSELECTOR_SLOT:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) // DEBUG2-NEXT: store i32 0, ptr [[RETVAL]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG201:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG202:![0-9]+]] -// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG202]] -// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG202]], !prof [[PROF203:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META201:![0-9]+]], metadata !DIExpression()), !dbg [[DBG202:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load atomic i8, ptr @_ZGVZ4mainE2sm acquire, align 8, !dbg [[DBG203:![0-9]+]] +// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP1]], 0, !dbg [[DBG203]] +// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG203]], !prof [[PROF204:![0-9]+]] // DEBUG2: init.check: -// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG202]] -// DEBUG2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG202]] -// DEBUG2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG202]] +// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_guard_acquire(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG203]] +// DEBUG2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0, !dbg [[DBG203]] +// DEBUG2-NEXT: br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]], !dbg [[DBG203]] // DEBUG2: init: -// DEBUG2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG202]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..5, ptr null, ptr @.__kmpc_global_dtor_..6), !dbg [[DBG202]] -// DEBUG2-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG204:![0-9]+]] -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG205:![0-9]+]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG205]] +// DEBUG2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG203]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB7]], ptr @_ZZ4mainE2sm, ptr @.__kmpc_global_ctor_..5, ptr null, ptr @.__kmpc_global_dtor_..6), !dbg [[DBG203]] +// DEBUG2-NEXT: [[TMP4:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB9]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG205:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP4]], i32 0, i32 0, !dbg [[DBG206:![0-9]+]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG206]] // DEBUG2-NEXT: invoke void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) @_ZZ4mainE2sm, i32 noundef [[TMP5]]) -// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG206:![0-9]+]] +// DEBUG2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[LPAD:%.*]], !dbg [[DBG207:![0-9]+]] // DEBUG2: invoke.cont: -// DEBUG2-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG202]] -// DEBUG2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG202]] -// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG202]] +// DEBUG2-NEXT: [[TMP6:%.*]] = call i32 @__cxa_atexit(ptr @_ZZ4mainEN5SmainD1Ev, ptr @_ZZ4mainE2sm, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG203]] +// DEBUG2-NEXT: call void @__cxa_guard_release(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG203]] +// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG203]] // DEBUG2: init.end: -// DEBUG2-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG207:![0-9]+]] -// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG208:![0-9]+]] -// DEBUG2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG208]] -// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG209:![0-9]+]] -// DEBUG2-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG210:![0-9]+]] -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG211:![0-9]+]] -// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG211]] -// DEBUG2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG212:![0-9]+]] -// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG212]] -// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG212]] -// DEBUG2-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG213:![0-9]+]] -// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG214:![0-9]+]] -// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG214]] -// DEBUG2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG215:![0-9]+]] -// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG215]] -// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG215]] -// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG216:![0-9]+]] -// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG217:![0-9]+]] -// DEBUG2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG217]] -// DEBUG2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG217]] -// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG218:![0-9]+]] -// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG219:![0-9]+]] -// DEBUG2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG219]] -// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG220:![0-9]+]] -// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG220]] -// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG220]] -// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG221:![0-9]+]] -// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], i64 0, i64 1, !dbg [[DBG221]] -// DEBUG2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG221]] -// DEBUG2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG222:![0-9]+]] -// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG222]] -// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG223:![0-9]+]] -// DEBUG2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG223]] -// DEBUG2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG223]] -// DEBUG2-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG224:![0-9]+]] -// DEBUG2-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG224]] -// DEBUG2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG225:![0-9]+]] -// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG225]] -// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG225]] -// DEBUG2-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG226:![0-9]+]] -// DEBUG2-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG226]] -// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG226]] -// DEBUG2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG227:![0-9]+]] -// DEBUG2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG227]] -// DEBUG2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG227]] -// DEBUG2-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG228:![0-9]+]] -// DEBUG2-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG229:![0-9]+]] -// DEBUG2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG229]] -// DEBUG2-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG230:![0-9]+]] -// DEBUG2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG230]] -// DEBUG2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG230]] -// DEBUG2-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] -// DEBUG2-NEXT: ret i32 [[TMP32]], !dbg [[DBG232:![0-9]+]] +// DEBUG2-NEXT: [[TMP7:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB11:[0-9]+]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG208:![0-9]+]] +// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP7]], i32 0, i32 0, !dbg [[DBG209:![0-9]+]] +// DEBUG2-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG209]] +// DEBUG2-NEXT: store i32 [[TMP8]], ptr [[RES]], align 4, !dbg [[DBG210:![0-9]+]] +// DEBUG2-NEXT: [[TMP9:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB13:[0-9]+]], i32 [[TMP0]], ptr @_ZZ4mainE2sm, i64 24, ptr @_ZZ4mainE2sm.cache.), !dbg [[DBG211:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[TMP9]], i32 0, i32 0, !dbg [[DBG212:![0-9]+]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[A2]], align 8, !dbg [[DBG212]] +// DEBUG2-NEXT: [[TMP11:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG213:![0-9]+]] +// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP11]], [[TMP10]], !dbg [[DBG213]] +// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG213]] +// DEBUG2-NEXT: [[TMP12:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB15:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG214:![0-9]+]] +// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[TMP12]], i32 0, i32 0, !dbg [[DBG215:![0-9]+]] +// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG215]] +// DEBUG2-NEXT: [[TMP14:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG216:![0-9]+]] +// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP14]], [[TMP13]], !dbg [[DBG216]] +// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG216]] +// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG217:![0-9]+]] +// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG218:![0-9]+]] +// DEBUG2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG218]] +// DEBUG2-NEXT: store i32 [[ADD5]], ptr [[RES]], align 4, !dbg [[DBG218]] +// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB17:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG219:![0-9]+]] +// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP17]], i32 0, i32 0, !dbg [[DBG220:![0-9]+]] +// DEBUG2-NEXT: [[TMP18:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG220]] +// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG221:![0-9]+]] +// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP19]], [[TMP18]], !dbg [[DBG221]] +// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG221]] +// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB19:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG222:![0-9]+]] +// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP20]], inrange i64 0, i64 1, !dbg [[DBG222]] +// DEBUG2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG222]] +// DEBUG2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX8]], i32 0, i32 0, !dbg [[DBG223:![0-9]+]] +// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A9]], align 4, !dbg [[DBG223]] +// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG224:![0-9]+]] +// DEBUG2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG224]] +// DEBUG2-NEXT: store i32 [[ADD10]], ptr [[RES]], align 4, !dbg [[DBG224]] +// DEBUG2-NEXT: [[TMP23:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB21:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG225:![0-9]+]] +// DEBUG2-NEXT: [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 4, !dbg [[DBG225]] +// DEBUG2-NEXT: [[TMP25:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG226:![0-9]+]] +// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP25]], [[TMP24]], !dbg [[DBG226]] +// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG226]] +// DEBUG2-NEXT: [[TMP26:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB23:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG227:![0-9]+]] +// DEBUG2-NEXT: [[TMP27:%.*]] = load float, ptr [[TMP26]], align 4, !dbg [[DBG227]] +// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP27]] to i32, !dbg [[DBG227]] +// DEBUG2-NEXT: [[TMP28:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG228:![0-9]+]] +// DEBUG2-NEXT: [[ADD12:%.*]] = add nsw i32 [[TMP28]], [[CONV]], !dbg [[DBG228]] +// DEBUG2-NEXT: store i32 [[ADD12]], ptr [[RES]], align 4, !dbg [[DBG228]] +// DEBUG2-NEXT: [[TMP29:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB25:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG229:![0-9]+]] +// DEBUG2-NEXT: [[A13:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP29]], i32 0, i32 0, !dbg [[DBG230:![0-9]+]] +// DEBUG2-NEXT: [[TMP30:%.*]] = load i32, ptr [[A13]], align 4, !dbg [[DBG230]] +// DEBUG2-NEXT: [[TMP31:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG231:![0-9]+]] +// DEBUG2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP31]], [[TMP30]], !dbg [[DBG231]] +// DEBUG2-NEXT: store i32 [[ADD14]], ptr [[RES]], align 4, !dbg [[DBG231]] +// DEBUG2-NEXT: [[TMP32:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG232:![0-9]+]] +// DEBUG2-NEXT: ret i32 [[TMP32]], !dbg [[DBG233:![0-9]+]] // DEBUG2: lpad: // DEBUG2-NEXT: [[TMP33:%.*]] = landingpad { ptr, i32 } -// DEBUG2-NEXT: cleanup, !dbg [[DBG233:![0-9]+]] -// DEBUG2-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG233]] -// DEBUG2-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG233]] -// DEBUG2-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG233]] -// DEBUG2-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG233]] -// DEBUG2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG202]] -// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG202]] +// DEBUG2-NEXT: cleanup, !dbg [[DBG234:![0-9]+]] +// DEBUG2-NEXT: [[TMP34:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 0, !dbg [[DBG234]] +// DEBUG2-NEXT: store ptr [[TMP34]], ptr [[EXN_SLOT]], align 8, !dbg [[DBG234]] +// DEBUG2-NEXT: [[TMP35:%.*]] = extractvalue { ptr, i32 } [[TMP33]], 1, !dbg [[DBG234]] +// DEBUG2-NEXT: store i32 [[TMP35]], ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG234]] +// DEBUG2-NEXT: call void @__cxa_guard_abort(ptr @_ZGVZ4mainE2sm) #[[ATTR4]], !dbg [[DBG203]] +// DEBUG2-NEXT: br label [[EH_RESUME:%.*]], !dbg [[DBG203]] // DEBUG2: eh.resume: -// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG202]] -// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG202]] -// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG202]] -// DEBUG2-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG202]] -// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG202]] +// DEBUG2-NEXT: [[EXN:%.*]] = load ptr, ptr [[EXN_SLOT]], align 8, !dbg [[DBG203]] +// DEBUG2-NEXT: [[SEL:%.*]] = load i32, ptr [[EHSELECTOR_SLOT]], align 4, !dbg [[DBG203]] +// DEBUG2-NEXT: [[LPAD_VAL:%.*]] = insertvalue { ptr, i32 } poison, ptr [[EXN]], 0, !dbg [[DBG203]] +// DEBUG2-NEXT: [[LPAD_VAL15:%.*]] = insertvalue { ptr, i32 } [[LPAD_VAL]], i32 [[SEL]], 1, !dbg [[DBG203]] +// DEBUG2-NEXT: resume { ptr, i32 } [[LPAD_VAL15]], !dbg [[DBG203]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..5 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG234:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG235:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]) // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META235:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG237:![0-9]+]] -// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG238:![0-9]+]] -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG239:![0-9]+]] -// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG239]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG240:![0-9]+]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG237]] -// DEBUG2-NEXT: ret ptr [[TMP5]], !dbg [[DBG237]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META236:![0-9]+]], metadata !DIExpression()), !dbg [[DBG237:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238:![0-9]+]] +// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB5]], i32 [[TMP1]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG239:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG240:![0-9]+]] +// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG240]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC1Ei(ptr noundef nonnull align 8 dereferenceable(24) [[TMP2]], i32 noundef [[TMP4]]), !dbg [[DBG241:![0-9]+]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG238]] +// DEBUG2-NEXT: ret ptr [[TMP5]], !dbg [[DBG238]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG241:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] align 2 !dbg [[DBG242:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG244:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META243:![0-9]+]], metadata !DIExpression()), !dbg [[DBG245:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META246:![0-9]+]], metadata !DIExpression()), !dbg [[DBG247:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG247:![0-9]+]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG247]] -// DEBUG2-NEXT: ret void, !dbg [[DBG248:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG248:![0-9]+]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainC2Ei(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG248]] +// DEBUG2-NEXT: ret void, !dbg [[DBG249:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..6 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG249:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG250:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META250:![0-9]+]], metadata !DIExpression()), !dbg [[DBG251:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG251]] -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR4]], !dbg [[DBG251]] -// DEBUG2-NEXT: ret void, !dbg [[DBG252:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG252]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD1Ev(ptr noundef nonnull align 8 dereferenceable(24) [[TMP1]]) #[[ATTR4]], !dbg [[DBG252]] +// DEBUG2-NEXT: ret void, !dbg [[DBG253:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG253:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG254:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG255:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG256:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG256:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG257:![0-9]+]] +// DEBUG2-NEXT: call void @_ZZ4mainEN5SmainD2Ev(ptr noundef nonnull align 8 dereferenceable(24) [[THIS1]]) #[[ATTR4]], !dbg [[DBG257:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG258:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_Z6foobarv -// DEBUG2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG258:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR6:[0-9]+]] !dbg [[DBG259:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[RES:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB27:[0-9]+]]) -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META259:![0-9]+]], metadata !DIExpression()), !dbg [[DBG260:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG261:![0-9]+]] -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG262:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG262]] -// DEBUG2-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG263:![0-9]+]] -// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG264:![0-9]+]] -// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG265:![0-9]+]] -// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG265]] -// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG266:![0-9]+]] -// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG266]] -// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG266]] -// DEBUG2-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG267:![0-9]+]] -// DEBUG2-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG268:![0-9]+]] -// DEBUG2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG268]] -// DEBUG2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG268]] -// DEBUG2-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG269:![0-9]+]] -// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG270:![0-9]+]] -// DEBUG2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG270]] -// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG271:![0-9]+]] -// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG271]] -// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG271]] -// DEBUG2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG272:![0-9]+]] -// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], i64 0, i64 1, !dbg [[DBG272]] -// DEBUG2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG272]] -// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG273:![0-9]+]] -// DEBUG2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG273]] -// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG274:![0-9]+]] -// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG274]] -// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG274]] -// DEBUG2-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG275:![0-9]+]] -// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG275]] -// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG276:![0-9]+]] -// DEBUG2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG276]] -// DEBUG2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG276]] -// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG277:![0-9]+]] -// DEBUG2-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG277]] -// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG277]] -// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG278:![0-9]+]] -// DEBUG2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG278]] -// DEBUG2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG278]] -// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG279:![0-9]+]] -// DEBUG2-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG280:![0-9]+]] -// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG280]] -// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG281:![0-9]+]] -// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG281]] -// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG281]] -// DEBUG2-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] -// DEBUG2-NEXT: ret i32 [[TMP23]], !dbg [[DBG283:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[RES]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG261:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB27]], i32 [[TMP0]], ptr @_ZN6Static1sE, i64 8, ptr @_ZN6Static1sE.cache.), !dbg [[DBG262:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S3:%.*]], ptr [[TMP1]], i32 0, i32 0, !dbg [[DBG263:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4, !dbg [[DBG263]] +// DEBUG2-NEXT: store i32 [[TMP2]], ptr [[RES]], align 4, !dbg [[DBG264:![0-9]+]] +// DEBUG2-NEXT: [[TMP3:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB29:[0-9]+]], i32 [[TMP0]], ptr @_ZL3gs1, i64 4, ptr @_ZL3gs1.cache.), !dbg [[DBG265:![0-9]+]] +// DEBUG2-NEXT: [[A1:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[TMP3]], i32 0, i32 0, !dbg [[DBG266:![0-9]+]] +// DEBUG2-NEXT: [[TMP4:%.*]] = load i32, ptr [[A1]], align 4, !dbg [[DBG266]] +// DEBUG2-NEXT: [[TMP5:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG267:![0-9]+]] +// DEBUG2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP5]], [[TMP4]], !dbg [[DBG267]] +// DEBUG2-NEXT: store i32 [[ADD]], ptr [[RES]], align 4, !dbg [[DBG267]] +// DEBUG2-NEXT: [[TMP6:%.*]] = load i32, ptr @_ZL3gs2, align 8, !dbg [[DBG268:![0-9]+]] +// DEBUG2-NEXT: [[TMP7:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG269:![0-9]+]] +// DEBUG2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], [[TMP6]], !dbg [[DBG269]] +// DEBUG2-NEXT: store i32 [[ADD2]], ptr [[RES]], align 4, !dbg [[DBG269]] +// DEBUG2-NEXT: [[TMP8:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB31:[0-9]+]], i32 [[TMP0]], ptr @gs3, i64 12, ptr @gs3.cache.), !dbg [[DBG270:![0-9]+]] +// DEBUG2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S5:%.*]], ptr [[TMP8]], i32 0, i32 0, !dbg [[DBG271:![0-9]+]] +// DEBUG2-NEXT: [[TMP9:%.*]] = load i32, ptr [[A3]], align 4, !dbg [[DBG271]] +// DEBUG2-NEXT: [[TMP10:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG272:![0-9]+]] +// DEBUG2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], [[TMP9]], !dbg [[DBG272]] +// DEBUG2-NEXT: store i32 [[ADD4]], ptr [[RES]], align 4, !dbg [[DBG272]] +// DEBUG2-NEXT: [[TMP11:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB33:[0-9]+]], i32 [[TMP0]], ptr @arr_x, i64 24, ptr @arr_x.cache.), !dbg [[DBG273:![0-9]+]] +// DEBUG2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x [3 x %struct.S1]], ptr [[TMP11]], inrange i64 0, i64 1, !dbg [[DBG273]] +// DEBUG2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [3 x %struct.S1], ptr [[ARRAYIDX]], inrange i64 0, i64 1, !dbg [[DBG273]] +// DEBUG2-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], ptr [[ARRAYIDX5]], i32 0, i32 0, !dbg [[DBG274:![0-9]+]] +// DEBUG2-NEXT: [[TMP12:%.*]] = load i32, ptr [[A6]], align 4, !dbg [[DBG274]] +// DEBUG2-NEXT: [[TMP13:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG275:![0-9]+]] +// DEBUG2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP13]], [[TMP12]], !dbg [[DBG275]] +// DEBUG2-NEXT: store i32 [[ADD7]], ptr [[RES]], align 4, !dbg [[DBG275]] +// DEBUG2-NEXT: [[TMP14:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB35:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIiE2stE, i64 4, ptr @_ZN2STIiE2stE.cache.), !dbg [[DBG276:![0-9]+]] +// DEBUG2-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 4, !dbg [[DBG276]] +// DEBUG2-NEXT: [[TMP16:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG277:![0-9]+]] +// DEBUG2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP16]], [[TMP15]], !dbg [[DBG277]] +// DEBUG2-NEXT: store i32 [[ADD8]], ptr [[RES]], align 4, !dbg [[DBG277]] +// DEBUG2-NEXT: [[TMP17:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB37:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STIfE2stE, i64 4, ptr @_ZN2STIfE2stE.cache.), !dbg [[DBG278:![0-9]+]] +// DEBUG2-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP17]], align 4, !dbg [[DBG278]] +// DEBUG2-NEXT: [[CONV:%.*]] = fptosi float [[TMP18]] to i32, !dbg [[DBG278]] +// DEBUG2-NEXT: [[TMP19:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG279:![0-9]+]] +// DEBUG2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP19]], [[CONV]], !dbg [[DBG279]] +// DEBUG2-NEXT: store i32 [[ADD9]], ptr [[RES]], align 4, !dbg [[DBG279]] +// DEBUG2-NEXT: [[TMP20:%.*]] = call ptr @__kmpc_threadprivate_cached(ptr @[[GLOB39:[0-9]+]], i32 [[TMP0]], ptr @_ZN2STI2S4E2stE, i64 8, ptr @_ZN2STI2S4E2stE.cache.), !dbg [[DBG280:![0-9]+]] +// DEBUG2-NEXT: [[A10:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[TMP20]], i32 0, i32 0, !dbg [[DBG281:![0-9]+]] +// DEBUG2-NEXT: [[TMP21:%.*]] = load i32, ptr [[A10]], align 4, !dbg [[DBG281]] +// DEBUG2-NEXT: [[TMP22:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG282:![0-9]+]] +// DEBUG2-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP22]], [[TMP21]], !dbg [[DBG282]] +// DEBUG2-NEXT: store i32 [[ADD11]], ptr [[RES]], align 4, !dbg [[DBG282]] +// DEBUG2-NEXT: [[TMP23:%.*]] = load i32, ptr [[RES]], align 4, !dbg [[DBG283:![0-9]+]] +// DEBUG2-NEXT: ret i32 [[TMP23]], !dbg [[DBG284:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@__cxx_global_var_init.7 -// DEBUG2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG284:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] comdat($_ZN2STI2S4E2stE) !dbg [[DBG285:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG285:![0-9]+]] -// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG285]] -// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG285]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i8, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG286:![0-9]+]] +// DEBUG2-NEXT: [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0, !dbg [[DBG286]] +// DEBUG2-NEXT: br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !dbg [[DBG286]] // DEBUG2: init.check: -// DEBUG2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG285]] -// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG285]] -// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..8, ptr null, ptr @.__kmpc_global_dtor_..9), !dbg [[DBG285]] -// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG286:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG285]] -// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG285]] +// DEBUG2-NEXT: store i8 1, ptr @_ZGVN2STI2S4E2stE, align 8, !dbg [[DBG286]] +// DEBUG2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB41:[0-9]+]]), !dbg [[DBG286]] +// DEBUG2-NEXT: call void @__kmpc_threadprivate_register(ptr @[[GLOB41]], ptr @_ZN2STI2S4E2stE, ptr @.__kmpc_global_ctor_..8, ptr null, ptr @.__kmpc_global_dtor_..9), !dbg [[DBG286]] +// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) @_ZN2STI2S4E2stE, i32 noundef 23), !dbg [[DBG287:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = call i32 @__cxa_atexit(ptr @_ZN2S4D1Ev, ptr @_ZN2STI2S4E2stE, ptr @__dso_handle) #[[ATTR4]], !dbg [[DBG286]] +// DEBUG2-NEXT: br label [[INIT_END]], !dbg [[DBG286]] // DEBUG2: init.end: -// DEBUG2-NEXT: ret void, !dbg [[DBG288:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG289:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..8 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG289:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG290:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META290:![0-9]+]], metadata !DIExpression()), !dbg [[DBG291:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG292:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG293:![0-9]+]] -// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG292]] -// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG292]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META291:![0-9]+]], metadata !DIExpression()), !dbg [[DBG292:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG293:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4C1Ei(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]], i32 noundef 23), !dbg [[DBG294:![0-9]+]] +// DEBUG2-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG293]] +// DEBUG2-NEXT: ret ptr [[TMP2]], !dbg [[DBG293]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C1Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG294:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 !dbg [[DBG295:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META295:![0-9]+]], metadata !DIExpression()), !dbg [[DBG297:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META296:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META298:![0-9]+]], metadata !DIExpression()), !dbg [[DBG299:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG300:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG300:![0-9]+]] -// DEBUG2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG300]] -// DEBUG2-NEXT: ret void, !dbg [[DBG301:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG301:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4C2Ei(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]], i32 noundef [[TMP0]]), !dbg [[DBG301]] +// DEBUG2-NEXT: ret void, !dbg [[DBG302:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..9 -// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG302:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef [[TMP0:%.*]]) #[[ATTR0]] !dbg [[DBG303:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[DOTADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[TMP0]], ptr [[DOTADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG304:![0-9]+]] -// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG304]] -// DEBUG2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR4]], !dbg [[DBG304]] -// DEBUG2-NEXT: ret void, !dbg [[DBG305:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[DOTADDR]], metadata [[META304:![0-9]+]], metadata !DIExpression()), !dbg [[DBG305:![0-9]+]] +// DEBUG2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTADDR]], align 8, !dbg [[DBG305]] +// DEBUG2-NEXT: call void @_ZN2S4D1Ev(ptr noundef nonnull align 4 dereferenceable(8) [[TMP1]]) #[[ATTR4]], !dbg [[DBG305]] +// DEBUG2-NEXT: ret void, !dbg [[DBG306:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D1Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG306:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG307:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META307:![0-9]+]], metadata !DIExpression()), !dbg [[DBG308:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META308:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG309:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG310:![0-9]+]] +// DEBUG2-NEXT: call void @_ZN2S4D2Ev(ptr noundef nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR4]], !dbg [[DBG310:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG311:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1C2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG311:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG312:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG313:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META313:![0-9]+]], metadata !DIExpression()), !dbg [[DBG314:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META314:![0-9]+]], metadata !DIExpression()), !dbg [[DBG315:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META315:![0-9]+]], metadata !DIExpression()), !dbg [[DBG316:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG316:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG317:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG316]] -// DEBUG2-NEXT: ret void, !dbg [[DBG318:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG317:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG318:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG317]] +// DEBUG2-NEXT: ret void, !dbg [[DBG319:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S1D2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG319:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG320:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META320:![0-9]+]], metadata !DIExpression()), !dbg [[DBG321:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META321:![0-9]+]], metadata !DIExpression()), !dbg [[DBG322:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG322:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG324:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG325:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG323:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG325:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG326:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2C2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG326:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG327:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META327:![0-9]+]], metadata !DIExpression()), !dbg [[DBG328:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META328:![0-9]+]], metadata !DIExpression()), !dbg [[DBG329:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META329:![0-9]+]], metadata !DIExpression()), !dbg [[DBG330:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META330:![0-9]+]], metadata !DIExpression()), !dbg [[DBG331:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG331:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG332:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG331]] -// DEBUG2-NEXT: ret void, !dbg [[DBG333:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG332:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG333:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG332]] +// DEBUG2-NEXT: ret void, !dbg [[DBG334:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S2D2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG334:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(16) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG335:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META335:![0-9]+]], metadata !DIExpression()), !dbg [[DBG336:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META336:![0-9]+]], metadata !DIExpression()), !dbg [[DBG337:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG337:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG339:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG340:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S2:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG338:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG340:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG341:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainC2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG341:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG342:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META342:![0-9]+]], metadata !DIExpression()), !dbg [[DBG343:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META343:![0-9]+]], metadata !DIExpression()), !dbg [[DBG344:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META344:![0-9]+]], metadata !DIExpression()), !dbg [[DBG345:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META345:![0-9]+]], metadata !DIExpression()), !dbg [[DBG346:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG346:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG347:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG346]] -// DEBUG2-NEXT: ret void, !dbg [[DBG348:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG347:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG348:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 8, !dbg [[DBG347]] +// DEBUG2-NEXT: ret void, !dbg [[DBG349:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZZ4mainEN5SmainD2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG349:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 8 dereferenceable(24) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 !dbg [[DBG350:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META350:![0-9]+]], metadata !DIExpression()), !dbg [[DBG351:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META351:![0-9]+]], metadata !DIExpression()), !dbg [[DBG352:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG352:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG354:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG355:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_SMAIN:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG353:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 8, !dbg [[DBG355:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG356:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4C2Ei -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG356:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[A:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG357:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META357:![0-9]+]], metadata !DIExpression()), !dbg [[DBG358:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META358:![0-9]+]], metadata !DIExpression()), !dbg [[DBG359:![0-9]+]] // DEBUG2-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META359:![0-9]+]], metadata !DIExpression()), !dbg [[DBG360:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[A_ADDR]], metadata [[META360:![0-9]+]], metadata !DIExpression()), !dbg [[DBG361:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG361:![0-9]+]] -// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG362:![0-9]+]] -// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG361]] -// DEBUG2-NEXT: ret void, !dbg [[DBG363:![0-9]+]] +// DEBUG2-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG362:![0-9]+]] +// DEBUG2-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4, !dbg [[DBG363:![0-9]+]] +// DEBUG2-NEXT: store i32 [[TMP0]], ptr [[A2]], align 4, !dbg [[DBG362]] +// DEBUG2-NEXT: ret void, !dbg [[DBG364:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_ZN2S4D2Ev -// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG364:![0-9]+]] { +// DEBUG2-SAME: (ptr noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] comdat align 2 !dbg [[DBG365:![0-9]+]] { // DEBUG2-NEXT: entry: // DEBUG2-NEXT: [[THIS_ADDR:%.*]] = alloca ptr, align 8 // DEBUG2-NEXT: store ptr [[THIS]], ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META365:![0-9]+]], metadata !DIExpression()), !dbg [[DBG366:![0-9]+]] +// DEBUG2-NEXT: call void @llvm.dbg.declare(metadata ptr [[THIS_ADDR]], metadata [[META366:![0-9]+]], metadata !DIExpression()), !dbg [[DBG367:![0-9]+]] // DEBUG2-NEXT: [[THIS1:%.*]] = load ptr, ptr [[THIS_ADDR]], align 8 -// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG367:![0-9]+]] -// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG369:![0-9]+]] -// DEBUG2-NEXT: ret void, !dbg [[DBG370:![0-9]+]] +// DEBUG2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S4:%.*]], ptr [[THIS1]], i32 0, i32 0, !dbg [[DBG368:![0-9]+]] +// DEBUG2-NEXT: store i32 0, ptr [[A]], align 4, !dbg [[DBG370:![0-9]+]] +// DEBUG2-NEXT: ret void, !dbg [[DBG371:![0-9]+]] // // // DEBUG2-LABEL: define {{[^@]+}}@_GLOBAL__sub_I_threadprivate_codegen.cpp -// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG371:![0-9]+]] { +// DEBUG2-SAME: () #[[ATTR0]] !dbg [[DBG372:![0-9]+]] { // DEBUG2-NEXT: entry: -// DEBUG2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG372:![0-9]+]] -// DEBUG2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG372]] -// DEBUG2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG372]] +// DEBUG2-NEXT: call void @__cxx_global_var_init(), !dbg [[DBG373:![0-9]+]] +// DEBUG2-NEXT: call void @__cxx_global_var_init.1(), !dbg [[DBG373]] +// DEBUG2-NEXT: call void @__cxx_global_var_init.2(), !dbg [[DBG373]] // DEBUG2-NEXT: ret void // Index: clang/test/SemaOpenCL/block-array-capturing.cl =================================================================== --- clang/test/SemaOpenCL/block-array-capturing.cl +++ clang/test/SemaOpenCL/block-array-capturing.cl @@ -12,5 +12,5 @@ } // CHECK: define {{.*}} @__block_typedef_kernel_block_invoke -// CHECK: %{{.*}} = getelementptr inbounds [3 x i32], ptr addrspace(4) %{{.*}}, i64 0, i64 0 +// CHECK: %{{.*}} = getelementptr inbounds [3 x i32], ptr addrspace(4) %{{.*}}, inrange i64 0, i64 0 // CHECK-NOT: call void @llvm.memcpy{{.*}} Index: clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.funcattrs.expected =================================================================== --- clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.funcattrs.expected +++ clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.funcattrs.expected @@ -20,8 +20,8 @@ // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i64 1 // CHECK-NEXT: [[Z:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYIDX]], i32 0, i32 2 // CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_RT:%.*]], ptr [[Z]], i32 0, i32 1 -// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], i64 0, i64 5 -// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], i64 0, i64 13 +// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], inrange i64 0, i64 5 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], inrange i64 0, i64 13 // CHECK-NEXT: ret ptr [[ARRAYIDX2]] // int *foo(struct ST *s) { Index: clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.plain.expected =================================================================== --- clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.plain.expected +++ clang/test/utils/update_cc_test_checks/Inputs/check-attributes.cpp.plain.expected @@ -19,8 +19,8 @@ // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], ptr [[TMP0]], i64 1 // CHECK-NEXT: [[Z:%.*]] = getelementptr inbounds [[STRUCT_ST]], ptr [[ARRAYIDX]], i32 0, i32 2 // CHECK-NEXT: [[B:%.*]] = getelementptr inbounds [[STRUCT_RT:%.*]], ptr [[Z]], i32 0, i32 1 -// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], i64 0, i64 5 -// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], i64 0, i64 13 +// CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [20 x i32]], ptr [[B]], inrange i64 0, i64 5 +// CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [20 x i32], ptr [[ARRAYIDX1]], inrange i64 0, i64 13 // CHECK-NEXT: ret ptr [[ARRAYIDX2]] // int *foo(struct ST *s) { Index: clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected =================================================================== --- clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected +++ clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.generated.expected @@ -87,7 +87,7 @@ // OMP-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // OMP-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 // OMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] +// OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, inrange i64 0, i64 [[IDXPROM]] // OMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8 // OMP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // OMP: omp.body.continue: @@ -158,7 +158,7 @@ // OMP-NEXT: store i32 [[ADD]], ptr [[I]], align 4 // OMP-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4 // OMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP8]] to i64 -// OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] +// OMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, inrange i64 0, i64 [[IDXPROM]] // OMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8 // OMP-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] // OMP: omp.body.continue: @@ -190,7 +190,7 @@ // NOOMP: for.body: // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] +// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, inrange i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP: for.inc: @@ -216,7 +216,7 @@ // NOOMP: for.body: // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] +// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, inrange i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP: for.inc: Index: clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected =================================================================== --- clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected +++ clang/test/utils/update_cc_test_checks/Inputs/generated-funcs.c.no-generated.expected @@ -34,7 +34,7 @@ // NOOMP: for.body: // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] +// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, inrange i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: store double 0.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP: for.inc: @@ -79,7 +79,7 @@ // NOOMP: for.body: // NOOMP-NEXT: [[TMP1:%.*]] = load i32, ptr [[I]], align 4 // NOOMP-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP1]] to i64 -// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, i64 0, i64 [[IDXPROM]] +// NOOMP-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [33554432 x double], ptr @A, inrange i64 0, i64 [[IDXPROM]] // NOOMP-NEXT: store double 1.000000e+00, ptr [[ARRAYIDX]], align 8 // NOOMP-NEXT: br label [[FOR_INC:%.*]] // NOOMP: for.inc: Index: llvm/include/llvm/IR/Instructions.h =================================================================== --- llvm/include/llvm/IR/Instructions.h +++ llvm/include/llvm/IR/Instructions.h @@ -1130,6 +1130,16 @@ /// Determine whether the GEP has the inbounds flag. bool isInBounds() const; + /// Obtain the index with an inrange flag, if any + std::optional getInRangeIndex() const; + + // Set the inrange flag on an index of this GEP instruction + // See LangRef.html for the meaning of inrange on a GEP index + void setInRangeIndex(int Idx); + + /// Clear the inrange flag of this GEP instruction + void resetInRangeIndex(); + /// Accumulate the constant address offset of this GEP if possible. /// /// This routine accepts an APInt into which it will accumulate the constant Index: llvm/include/llvm/IR/Operator.h =================================================================== --- llvm/include/llvm/IR/Operator.h +++ llvm/include/llvm/IR/Operator.h @@ -390,6 +390,14 @@ (SubclassOptionalData & ~IsInBounds) | (B * IsInBounds); } + void setInRangeIndex(int Idx) { + SubclassOptionalData |= (Idx + 1) << 1; + } + + void resetInRangeIndex() { + SubclassOptionalData &= 1; + } + public: /// Test whether this is an inbounds GEP, as defined by LangRef.html. bool isInBounds() const { Index: llvm/lib/AsmParser/LLParser.cpp =================================================================== --- llvm/lib/AsmParser/LLParser.cpp +++ llvm/lib/AsmParser/LLParser.cpp @@ -7965,11 +7965,14 @@ ? cast(BaseType)->getElementCount() : ElementCount::getFixed(0); + std::optional InRangeIndex; while (EatIfPresent(lltok::comma)) { if (Lex.getKind() == lltok::MetadataVar) { AteExtraComma = true; break; } + if (EatIfPresent(lltok::kw_inrange)) + InRangeIndex = Indices.size() + 1; if (parseTypeAndValue(Val, EltLoc, PFS)) return true; if (!Val->getType()->isIntOrIntVectorTy()) @@ -7995,6 +7998,9 @@ Inst = GetElementPtrInst::Create(Ty, Ptr, Indices); if (InBounds) cast(Inst)->setIsInBounds(true); + if (InRangeIndex) + cast(Inst)->setInRangeIndex(*InRangeIndex); + return AteExtraComma ? InstExtraComma : InstNormal; } Index: llvm/lib/Bitcode/Reader/BitcodeReader.cpp =================================================================== --- llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -4936,9 +4936,13 @@ unsigned TyID; Type *Ty; bool InBounds; + std::optional InRangeIndex; if (BitCode == bitc::FUNC_CODE_INST_GEP) { - InBounds = Record[OpNum++]; + uint64_t Op = Record[OpNum++]; + InBounds = Op & 1; + if (Op >> 1) + InRangeIndex = Op >> 1; TyID = Record[OpNum++]; Ty = getTypeByID(TyID); } else { @@ -5001,6 +5005,8 @@ InstructionList.push_back(I); if (InBounds) cast(I)->setIsInBounds(true); + if (InRangeIndex) + cast(I)->setInRangeIndex(*InRangeIndex); break; } Index: llvm/lib/Bitcode/Writer/BitcodeWriter.cpp =================================================================== --- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp +++ llvm/lib/Bitcode/Writer/BitcodeWriter.cpp @@ -2852,7 +2852,11 @@ Code = bitc::FUNC_CODE_INST_GEP; AbbrevToUse = FUNCTION_INST_GEP_ABBREV; auto &GEPInst = cast(I); - Vals.push_back(GEPInst.isInBounds()); + if (std::optional Idx = GEPInst.getInRangeIndex()) { + Vals.push_back((*Idx << 1) | GEPInst.isInBounds()); + } else { + Vals.push_back(GEPInst.isInBounds()); + } Vals.push_back(VE.getTypeID(GEPInst.getSourceElementType())); for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) pushValueAndType(I.getOperand(i), InstID, Vals); @@ -3667,7 +3671,7 @@ { auto Abbv = std::make_shared(); Abbv->Add(BitCodeAbbrevOp(bitc::FUNC_CODE_INST_GEP)); - Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 1)); + Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, 6)); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Fixed, // dest ty Log2_32_Ceil(VE.getTypes().size() + 1))); Abbv->Add(BitCodeAbbrevOp(BitCodeAbbrevOp::Array)); Index: llvm/lib/IR/AsmWriter.cpp =================================================================== --- llvm/lib/IR/AsmWriter.cpp +++ llvm/lib/IR/AsmWriter.cpp @@ -4089,6 +4089,8 @@ // Print out the type of the operands... const Value *Operand = I.getNumOperands() ? I.getOperand(0) : nullptr; + std::optional InRangeIndex; + // Special case conditional branches to swizzle the condition out to the front if (isa(I) && cast(I).isConditional()) { const BranchInst &BI(cast(I)); @@ -4385,6 +4387,7 @@ TypePrinter.print(I.getType(), Out); } else if (Operand) { // Print the normal way. if (const auto *GEP = dyn_cast(&I)) { + InRangeIndex = GEP->getInRangeIndex(); Out << ' '; TypePrinter.print(GEP->getSourceElementType(), Out); Out << ','; @@ -4426,6 +4429,8 @@ Out << ' '; for (unsigned i = 0, E = I.getNumOperands(); i != E; ++i) { if (i) Out << ", "; + if (InRangeIndex && i == *InRangeIndex) + Out << "inrange "; writeOperand(I.getOperand(i), PrintAllTypes); } } Index: llvm/lib/IR/Instruction.cpp =================================================================== --- llvm/lib/IR/Instruction.cpp +++ llvm/lib/IR/Instruction.cpp @@ -202,6 +202,7 @@ case Instruction::GetElementPtr: cast(this)->setIsInBounds(false); + cast(this)->resetInRangeIndex(); break; } if (isa(this)) { Index: llvm/lib/IR/Instructions.cpp =================================================================== --- llvm/lib/IR/Instructions.cpp +++ llvm/lib/IR/Instructions.cpp @@ -1959,6 +1959,18 @@ return cast(this)->isInBounds(); } +std::optional GetElementPtrInst::getInRangeIndex() const { + return cast(this)->getInRangeIndex(); +} + +void GetElementPtrInst::setInRangeIndex(int Idx) { + cast(this)->setInRangeIndex(Idx); +} + +void GetElementPtrInst::resetInRangeIndex() { + cast(this)->resetInRangeIndex(); +} + bool GetElementPtrInst::accumulateConstantOffset(const DataLayout &DL, APInt &Offset) const { // Delegate to the generic GEPOperator implementation. Index: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp =================================================================== --- llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -2072,11 +2072,24 @@ Indices.append(GEP.idx_begin()+1, GEP.idx_end()); } - if (!Indices.empty()) - return replaceInstUsesWith( - GEP, Builder.CreateGEP( - Src->getSourceElementType(), Src->getOperand(0), Indices, "", - isMergedGEPInBounds(*Src, *cast(&GEP)))); + if (!Indices.empty()) { + Value *NewVal = Builder.CreateGEP( + Src->getSourceElementType(), Src->getOperand(0), Indices, "", + isMergedGEPInBounds(*Src, *cast(&GEP))); + GetElementPtrInst *NewGEP = dyn_cast(NewVal); + // If the source pointer has an inrange index, preserve that index in + // the combined instruction + if (Src->getInRangeIndex()) { + NewGEP->setInRangeIndex(*Src->getInRangeIndex()); + } + // If the original GEP has an inrange index, then the combined instruction + // will have the same inrange index offset by the number of indices + // introduced by Src + else if (GEP.getInRangeIndex()) { + NewGEP->setInRangeIndex(Src->getNumOperands() + *GEP.getInRangeIndex() - 2); + } + return replaceInstUsesWith(GEP, NewGEP); + } return nullptr; }