diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -595,16 +595,12 @@ } // CodeSize = 1, hasSideEffects = 0 } // Constraints = "$src1 = $dst", SchedRW -let CodeSize = 2, SchedRW = [WriteALURMW] in { -let Predicates = [UseIncDec] in { +let CodeSize = 2, SchedRW = [WriteALURMW], Predicates = [UseIncDec] in { def INC8m : INCDECM; def INC16m : INCDECM; def INC32m : INCDECM; -} // Predicates -let Predicates = [UseIncDec, In64BitMode] in { def INC64m : INCDECM; -} // Predicates -} // CodeSize = 2, SchedRW +} // CodeSize = 2, SchedRW, Predicates let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in { let isConvertibleToThreeAddress = 1, CodeSize = 2 in { // Can xform into LEA. @@ -621,16 +617,12 @@ } // CodeSize = 1, hasSideEffects = 0 } // Constraints = "$src1 = $dst", SchedRW -let CodeSize = 2, SchedRW = [WriteALURMW] in { -let Predicates = [UseIncDec] in { +let CodeSize = 2, SchedRW = [WriteALURMW], Predicates = [UseIncDec] in { def DEC8m : INCDECM; def DEC16m : INCDECM; def DEC32m : INCDECM; -} // Predicates -let Predicates = [UseIncDec, In64BitMode] in { def DEC64m : INCDECM; -} // Predicates -} // CodeSize = 2, SchedRW +} // CodeSize = 2, SchedRW, Predicates } // Defs = [EFLAGS] // Extra precision multiplication @@ -672,8 +664,7 @@ def MUL32m : MulOpM<0xF7, MRM4m, "mul", Xi32, WriteIMul32, []>; // RAX,RDX = RAX*[mem64] let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in -def MUL64m : MulOpM<0xF7, MRM4m, "mul", Xi64, WriteIMul64, []>, - Requires<[In64BitMode]>; +def MUL64m : MulOpM<0xF7, MRM4m, "mul", Xi64, WriteIMul64, []>; } let hasSideEffects = 0 in { @@ -702,8 +693,7 @@ def IMUL32m : MulOpM<0xF7, MRM5m, "imul", Xi32, WriteIMul32, []>; // RAX,RDX = RAX*[mem64] let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in -def IMUL64m : MulOpM<0xF7, MRM5m, "imul", Xi64, WriteIMul64, []>, - Requires<[In64BitMode]>; +def IMUL64m : MulOpM<0xF7, MRM5m, "imul", Xi64, WriteIMul64, []>; } let Defs = [EFLAGS] in { @@ -784,8 +774,7 @@ def DIV32m : MulOpM<0xF7, MRM6m, "div", Xi32, WriteDiv32, []>; // RDX:RAX/[mem64] = RAX,RDX let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in -def DIV64m : MulOpM<0xF7, MRM6m, "div", Xi64, WriteDiv64, []>, - Requires<[In64BitMode]>; +def DIV64m : MulOpM<0xF7, MRM6m, "div", Xi64, WriteDiv64, []>; } // Signed division/remainder. @@ -814,8 +803,7 @@ def IDIV32m: MulOpM<0xF7, MRM7m, "idiv", Xi32, WriteIDiv32, []>; let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX // RDX:RAX/[mem64] = RAX,RDX -def IDIV64m: MulOpM<0xF7, MRM7m, "idiv", Xi64, WriteIDiv64, []>, - Requires<[In64BitMode]>; +def IDIV64m: MulOpM<0xF7, MRM7m, "idiv", Xi64, WriteIDiv64, []>; } } // hasSideEffects = 0 @@ -838,7 +826,7 @@ def NEG8m : NegOpM<0xF6, "neg", Xi8>; def NEG16m : NegOpM<0xF7, "neg", Xi16>; def NEG32m : NegOpM<0xF7, "neg", Xi32>; -def NEG64m : NegOpM<0xF7, "neg", Xi64>, Requires<[In64BitMode]>; +def NEG64m : NegOpM<0xF7, "neg", Xi64>; } // SchedRW } // Defs = [EFLAGS] @@ -856,7 +844,7 @@ def NOT8m : NotOpM<0xF6, "not", Xi8>; def NOT16m : NotOpM<0xF7, "not", Xi16>; def NOT32m : NotOpM<0xF7, "not", Xi32>; -def NOT64m : NotOpM<0xF7, "not", Xi64>, Requires<[In64BitMode]>; +def NOT64m : NotOpM<0xF7, "not", Xi64>; } // SchedRW } // CodeSize @@ -917,13 +905,11 @@ // first so that they are slightly preferred to the mi forms. def NAME#16mi8 : BinOpMI8_RMW; def NAME#32mi8 : BinOpMI8_RMW; - let Predicates = [In64BitMode] in def NAME#64mi8 : BinOpMI8_RMW; def NAME#8mi : BinOpMI_RMW<0x80, mnemonic, Xi8 , opnode, MemMRM>; def NAME#16mi : BinOpMI_RMW<0x80, mnemonic, Xi16, opnode, MemMRM>; def NAME#32mi : BinOpMI_RMW<0x80, mnemonic, Xi32, opnode, MemMRM>; - let Predicates = [In64BitMode] in def NAME#64mi32 : BinOpMI_RMW<0x80, mnemonic, Xi64, opnode, MemMRM>; // These are for the disassembler since 0x82 opcode behaves like 0x80, but @@ -1002,13 +988,11 @@ // first so that they are slightly preferred to the mi forms. def NAME#16mi8 : BinOpMI8_RMW_FF; def NAME#32mi8 : BinOpMI8_RMW_FF; - let Predicates = [In64BitMode] in def NAME#64mi8 : BinOpMI8_RMW_FF; def NAME#8mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi8 , opnode, MemMRM>; def NAME#16mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi16, opnode, MemMRM>; def NAME#32mi : BinOpMI_RMW_FF<0x80, mnemonic, Xi32, opnode, MemMRM>; - let Predicates = [In64BitMode] in def NAME#64mi32 : BinOpMI_RMW_FF<0x80, mnemonic, Xi64, opnode, MemMRM>; // These are for the disassembler since 0x82 opcode behaves like 0x80, but @@ -1083,13 +1067,11 @@ // first so that they are slightly preferred to the mi forms. def NAME#16mi8 : BinOpMI8_F; def NAME#32mi8 : BinOpMI8_F; - let Predicates = [In64BitMode] in def NAME#64mi8 : BinOpMI8_F; def NAME#8mi : BinOpMI_F<0x80, mnemonic, Xi8 , opnode, MemMRM>; def NAME#16mi : BinOpMI_F<0x80, mnemonic, Xi16, opnode, MemMRM>; def NAME#32mi : BinOpMI_F<0x80, mnemonic, Xi32, opnode, MemMRM>; - let Predicates = [In64BitMode] in def NAME#64mi32 : BinOpMI_F<0x80, mnemonic, Xi64, opnode, MemMRM>; // These are for the disassembler since 0x82 opcode behaves like 0x80, but @@ -1345,7 +1327,6 @@ def TEST8mi : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>; def TEST16mi : BinOpMI_F<0xF6, "test", Xi16, X86testpat, MRM0m>; def TEST32mi : BinOpMI_F<0xF6, "test", Xi32, X86testpat, MRM0m>; - let Predicates = [In64BitMode] in def TEST64mi32 : BinOpMI_F<0xF6, "test", Xi64, X86testpat, MRM0m>; } // Defs = [EFLAGS]