diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -931,6 +931,8 @@
         setOperationAction({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT}, VT,
                            Custom);
 
+        setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
+
         // Operations below are different for between masks and other vectors.
         if (VT.getVectorElementType() == MVT::i1) {
           setOperationAction({ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR, ISD::AND,
@@ -953,8 +955,6 @@
           setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
         }
 
-        setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
-
         setOperationAction(
             {ISD::MLOAD, ISD::MSTORE, ISD::MGATHER, ISD::MSCATTER}, VT, Custom);
 
@@ -3804,6 +3804,17 @@
   unsigned NumElts = VT.getVectorNumElements();
   ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
 
+  // Promote i1 shuffle to i8 shuffle.
+  if (VT.getVectorElementType() == MVT::i1) {
+    MVT WidenVT = MVT::getVectorVT(MVT::i8, VT.getVectorElementCount());
+    V1 = DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V1);
+    V2 = V2.isUndef() ? DAG.getUNDEF(WidenVT)
+                      : DAG.getNode(ISD::ZERO_EXTEND, DL, WidenVT, V2);
+    SDValue Shuffled = DAG.getVectorShuffle(WidenVT, DL, V1, V2, SVN->getMask());
+    return DAG.getSetCC(DL, VT, Shuffled, DAG.getConstant(0, DL, WidenVT),
+                        ISD::SETNE);
+  }
+
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
   auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
diff --git a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
--- a/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/constant-folding-crash.ll
@@ -28,11 +28,12 @@
 ; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32-NEXT:    vmerge.vvm v8, v9, v8, v0
 ; RV32-NEXT:    vmv.x.s a0, v8
-; RV32-NEXT:    vfirst.m a1, v10
-; RV32-NEXT:    seqz a1, a1
 ; RV32-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; RV32-NEXT:    vmv.v.x v8, a1
-; RV32-NEXT:    vmsne.vi v0, v8, 0
+; RV32-NEXT:    vmv.v.i v8, 0
+; RV32-NEXT:    vmv1r.v v0, v10
+; RV32-NEXT:    vmerge.vim v8, v8, 1, v0
+; RV32-NEXT:    vrgather.vi v9, v8, 0
+; RV32-NEXT:    vmsne.vi v0, v9, 0
 ; RV32-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV32-NEXT:    vmv.v.i v8, 10
 ; RV32-NEXT:    vse32.v v8, (a0), v0.t
@@ -50,11 +51,12 @@
 ; RV64-NEXT:    vsetvli zero, zero, e64, m2, ta, ma
 ; RV64-NEXT:    vmerge.vvm v8, v10, v8, v0
 ; RV64-NEXT:    vmv.x.s a0, v8
-; RV64-NEXT:    vfirst.m a1, v12
-; RV64-NEXT:    seqz a1, a1
 ; RV64-NEXT:    vsetvli zero, zero, e8, mf4, ta, ma
-; RV64-NEXT:    vmv.v.x v8, a1
-; RV64-NEXT:    vmsne.vi v0, v8, 0
+; RV64-NEXT:    vmv.v.i v8, 0
+; RV64-NEXT:    vmv1r.v v0, v12
+; RV64-NEXT:    vmerge.vim v8, v8, 1, v0
+; RV64-NEXT:    vrgather.vi v9, v8, 0
+; RV64-NEXT:    vmsne.vi v0, v9, 0
 ; RV64-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 10
 ; RV64-NEXT:    vse32.v v8, (a0), v0.t
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll
@@ -16,16 +16,9 @@
 ; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vslidedown.vi v8, v8, 1
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    vfirst.m a1, v0
-; CHECK-NEXT:    seqz a1, a1
-; CHECK-NEXT:    vmv.v.x v8, a1
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, tu, ma
-; CHECK-NEXT:    vmv.s.x v8, a0
-; CHECK-NEXT:    vsetvli zero, zero, e8, mf8, ta, ma
-; CHECK-NEXT:    vand.vi v8, v8, 1
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vslidedown.vi v9, v8, 1
+; CHECK-NEXT:    vslideup.vi v9, v8, 1
+; CHECK-NEXT:    vmsne.vi v0, v9, 0
 ; CHECK-NEXT:    ret
   %res = call <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1> %a)
   ret <2 x i1> %res
@@ -37,2416 +30,75 @@
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; CHECK-NEXT:    vmv.v.i v8, 0
 ; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
-; CHECK-NEXT:    vslidedown.vi v9, v8, 3
-; CHECK-NEXT:    vmv.x.s a0, v9
-; CHECK-NEXT:    vslide1down.vx v9, v8, a0
-; CHECK-NEXT:    vslidedown.vi v10, v8, 2
-; CHECK-NEXT:    vmv.x.s a0, v10
-; CHECK-NEXT:    vslide1down.vx v9, v9, a0
-; CHECK-NEXT:    vslidedown.vi v8, v8, 1
-; CHECK-NEXT:    vmv.x.s a0, v8
-; CHECK-NEXT:    vslide1down.vx v8, v9, a0
-; CHECK-NEXT:    vfirst.m a0, v0
-; CHECK-NEXT:    seqz a0, a0
-; CHECK-NEXT:    vslide1down.vx v8, v8, a0
-; CHECK-NEXT:    vand.vi v8, v8, 1
-; CHECK-NEXT:    vmsne.vi v0, v8, 0
+; CHECK-NEXT:    vid.v v9
+; CHECK-NEXT:    vrsub.vi v9, v9, 3
+; CHECK-NEXT:    vrgather.vv v10, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v10, 0
 ; CHECK-NEXT:    ret
   %res = call <4 x i1> @llvm.experimental.vector.reverse.v4i1(<4 x i1> %a)
   ret <4 x i1> %res
 }
 
 define <8 x i1> @reverse_v8i1(<8 x i1> %a) {
-; RV32-BITS-UNKNOWN-LABEL: reverse_v8i1:
-; RV32-BITS-UNKNOWN:       # %bb.0:
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-UNKNOWN-NEXT:    ret
-;
-; RV32-BITS-256-LABEL: reverse_v8i1:
-; RV32-BITS-256:       # %bb.0:
-; RV32-BITS-256-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
-; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    slli a1, a0, 24
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 25
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 26
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 27
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 28
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 29
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a0, a0, 30
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vfirst.m a0, v0
-; RV32-BITS-256-NEXT:    seqz a0, a0
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-256-NEXT:    ret
-;
-; RV32-BITS-512-LABEL: reverse_v8i1:
-; RV32-BITS-512:       # %bb.0:
-; RV32-BITS-512-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
-; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    slli a1, a0, 24
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 25
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 26
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 27
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 28
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 29
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a0, a0, 30
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vfirst.m a0, v0
-; RV32-BITS-512-NEXT:    seqz a0, a0
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-512-NEXT:    ret
-;
-; RV64-BITS-UNKNOWN-LABEL: reverse_v8i1:
-; RV64-BITS-UNKNOWN:       # %bb.0:
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 56
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 62
-; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-UNKNOWN-NEXT:    ret
-;
-; RV64-BITS-256-LABEL: reverse_v8i1:
-; RV64-BITS-256:       # %bb.0:
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
-; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    slli a1, a0, 56
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 57
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 58
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 59
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 60
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 61
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a0, a0, 62
-; RV64-BITS-256-NEXT:    srli a0, a0, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vfirst.m a0, v0
-; RV64-BITS-256-NEXT:    seqz a0, a0
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-256-NEXT:    ret
-;
-; RV64-BITS-512-LABEL: reverse_v8i1:
-; RV64-BITS-512:       # %bb.0:
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e8, mf8, ta, ma
-; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    slli a1, a0, 56
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 57
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 58
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 59
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 60
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 61
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a0, a0, 62
-; RV64-BITS-512-NEXT:    srli a0, a0, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vfirst.m a0, v0
-; RV64-BITS-512-NEXT:    seqz a0, a0
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-512-NEXT:    ret
+; CHECK-LABEL: reverse_v8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vid.v v9
+; CHECK-NEXT:    vrsub.vi v9, v9, 7
+; CHECK-NEXT:    vrgather.vv v10, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v10, 0
+; CHECK-NEXT:    ret
   %res = call <8 x i1> @llvm.experimental.vector.reverse.v8i1(<8 x i1> %a)
   ret <8 x i1> %res
 }
 
 define <16 x i1> @reverse_v16i1(<16 x i1> %a) {
-; RV32-BITS-UNKNOWN-LABEL: reverse_v16i1:
-; RV32-BITS-UNKNOWN:       # %bb.0:
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-UNKNOWN-NEXT:    ret
-;
-; RV32-BITS-256-LABEL: reverse_v16i1:
-; RV32-BITS-256:       # %bb.0:
-; RV32-BITS-256-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    slli a1, a0, 16
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 17
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 18
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 19
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 20
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 21
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 22
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 23
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 24
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 25
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 26
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 27
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 28
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 29
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a0, a0, 30
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vfirst.m a0, v0
-; RV32-BITS-256-NEXT:    seqz a0, a0
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-256-NEXT:    ret
-;
-; RV32-BITS-512-LABEL: reverse_v16i1:
-; RV32-BITS-512:       # %bb.0:
-; RV32-BITS-512-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    slli a1, a0, 16
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 17
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 18
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 19
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 20
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 21
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 22
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 23
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 24
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 25
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 26
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 27
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 28
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 29
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a0, a0, 30
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vfirst.m a0, v0
-; RV32-BITS-512-NEXT:    seqz a0, a0
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-512-NEXT:    ret
-;
-; RV64-BITS-UNKNOWN-LABEL: reverse_v16i1:
-; RV64-BITS-UNKNOWN:       # %bb.0:
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 48
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 49
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 50
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 51
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 52
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 53
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 54
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 55
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 56
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 62
-; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-UNKNOWN-NEXT:    ret
-;
-; RV64-BITS-256-LABEL: reverse_v16i1:
-; RV64-BITS-256:       # %bb.0:
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    slli a1, a0, 48
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 49
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 50
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 51
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 52
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 53
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 54
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 55
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 56
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 57
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 58
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 59
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 60
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 61
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a0, a0, 62
-; RV64-BITS-256-NEXT:    srli a0, a0, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vfirst.m a0, v0
-; RV64-BITS-256-NEXT:    seqz a0, a0
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-256-NEXT:    ret
-;
-; RV64-BITS-512-LABEL: reverse_v16i1:
-; RV64-BITS-512:       # %bb.0:
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    slli a1, a0, 48
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 49
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 50
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 51
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 52
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 53
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 54
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 55
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 56
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 57
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 58
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 59
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 60
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 61
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a0, a0, 62
-; RV64-BITS-512-NEXT:    srli a0, a0, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vfirst.m a0, v0
-; RV64-BITS-512-NEXT:    seqz a0, a0
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-512-NEXT:    ret
+; CHECK-LABEL: reverse_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vmv.v.i v8, 0
+; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
+; CHECK-NEXT:    vid.v v9
+; CHECK-NEXT:    vrsub.vi v9, v9, 15
+; CHECK-NEXT:    vrgather.vv v10, v8, v9
+; CHECK-NEXT:    vmsne.vi v0, v10, 0
+; CHECK-NEXT:    ret
   %res = call <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1> %a)
   ret <16 x i1> %res
 }
 
 define <32 x i1> @reverse_v32i1(<32 x i1> %a) {
-; RV32-BITS-UNKNOWN-LABEL: reverse_v32i1:
-; RV32-BITS-UNKNOWN:       # %bb.0:
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    li a2, 32
-; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 1
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 2
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 3
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 4
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 5
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 6
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 7
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 8
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 9
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 10
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 11
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 12
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 13
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 14
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 15
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a0, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-UNKNOWN-NEXT:    ret
-;
-; RV32-BITS-256-LABEL: reverse_v32i1:
-; RV32-BITS-256:       # %bb.0:
-; RV32-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-256-NEXT:    srli a1, a0, 31
-; RV32-BITS-256-NEXT:    li a2, 32
-; RV32-BITS-256-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 1
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 2
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 3
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 4
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 5
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 6
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 7
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 8
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 9
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 10
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 11
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 12
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 13
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 14
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 15
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 16
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 17
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 18
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 19
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 20
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 21
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 22
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 23
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 24
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 25
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 26
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 27
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 28
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a1, a0, 29
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    slli a0, a0, 30
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vfirst.m a0, v0
-; RV32-BITS-256-NEXT:    seqz a0, a0
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-256-NEXT:    ret
-;
-; RV32-BITS-512-LABEL: reverse_v32i1:
-; RV32-BITS-512:       # %bb.0:
-; RV32-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV32-BITS-512-NEXT:    srli a1, a0, 31
-; RV32-BITS-512-NEXT:    li a2, 32
-; RV32-BITS-512-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 1
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 2
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 3
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 4
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 5
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 6
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 7
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 8
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 9
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 10
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 11
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 12
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 13
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 14
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 15
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 16
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 17
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 18
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 19
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 20
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 21
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 22
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 23
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 24
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 25
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 26
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 27
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 28
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a1, a0, 29
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    slli a0, a0, 30
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vfirst.m a0, v0
-; RV32-BITS-512-NEXT:    seqz a0, a0
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-512-NEXT:    ret
-;
-; RV64-BITS-UNKNOWN-LABEL: reverse_v32i1:
-; RV64-BITS-UNKNOWN:       # %bb.0:
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    srliw a1, a0, 31
-; RV64-BITS-UNKNOWN-NEXT:    li a2, 32
-; RV64-BITS-UNKNOWN-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 33
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 34
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 35
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 36
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 37
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 38
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 39
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 40
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 41
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 42
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 43
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 44
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 45
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 46
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 47
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 48
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 49
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 50
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 51
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 52
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 53
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 54
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 55
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 56
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 62
-; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-UNKNOWN-NEXT:    ret
-;
-; RV64-BITS-256-LABEL: reverse_v32i1:
-; RV64-BITS-256:       # %bb.0:
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    srliw a1, a0, 31
-; RV64-BITS-256-NEXT:    li a2, 32
-; RV64-BITS-256-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 33
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 34
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 35
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 36
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 37
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 38
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 39
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 40
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 41
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 42
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 43
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 44
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 45
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 46
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 47
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 48
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 49
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 50
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 51
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 52
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 53
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 54
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 55
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 56
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 57
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 58
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 59
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 60
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 61
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a0, a0, 62
-; RV64-BITS-256-NEXT:    srli a0, a0, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vfirst.m a0, v0
-; RV64-BITS-256-NEXT:    seqz a0, a0
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-256-NEXT:    ret
-;
-; RV64-BITS-512-LABEL: reverse_v32i1:
-; RV64-BITS-512:       # %bb.0:
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    srliw a1, a0, 31
-; RV64-BITS-512-NEXT:    li a2, 32
-; RV64-BITS-512-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 33
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 34
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 35
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 36
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 37
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 38
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 39
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 40
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 41
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 42
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 43
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 44
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 45
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 46
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 47
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 48
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 49
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 50
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 51
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 52
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 53
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 54
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 55
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 56
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 57
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 58
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 59
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 60
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 61
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a0, a0, 62
-; RV64-BITS-512-NEXT:    srli a0, a0, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vfirst.m a0, v0
-; RV64-BITS-512-NEXT:    seqz a0, a0
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-512-NEXT:    ret
+; CHECK-LABEL: reverse_v32i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT:    lui a0, %hi(.LCPI4_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI4_0)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmv.v.i v10, 0
+; CHECK-NEXT:    vmerge.vim v10, v10, 1, v0
+; CHECK-NEXT:    vrgather.vv v12, v10, v8
+; CHECK-NEXT:    vmsne.vi v0, v12, 0
+; CHECK-NEXT:    ret
   %res = call <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1> %a)
   ret <32 x i1> %res
 }
 
 define <64 x i1> @reverse_v64i1(<64 x i1> %a) {
-; RV32-BITS-UNKNOWN-LABEL: reverse_v64i1:
-; RV32-BITS-UNKNOWN:       # %bb.0:
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vslidedown.vi v8, v0, 1
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v8
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    li a0, 64
-; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 1
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 2
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 3
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 4
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 5
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 6
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 7
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 8
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 9
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 10
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 11
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 12
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 13
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 14
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 15
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a2, a1, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a2, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    andi a1, a1, 1
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vmv.x.s a1, v0
-; RV32-BITS-UNKNOWN-NEXT:    srli a2, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 1
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 2
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 3
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 4
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 5
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 6
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 7
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 8
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 9
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 10
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 11
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 12
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 13
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 14
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 15
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 16
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 17
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 18
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 19
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 20
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 21
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 22
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 23
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 24
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 25
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 26
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 27
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 28
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a0, a1, 29
-; RV32-BITS-UNKNOWN-NEXT:    srli a0, a0, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    slli a1, a1, 30
-; RV32-BITS-UNKNOWN-NEXT:    srli a1, a1, 31
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV32-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV32-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-UNKNOWN-NEXT:    ret
-;
-; RV32-BITS-256-LABEL: reverse_v64i1:
-; RV32-BITS-256:       # %bb.0:
-; RV32-BITS-256-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-BITS-256-NEXT:    vslidedown.vi v8, v0, 1
-; RV32-BITS-256-NEXT:    vmv.x.s a1, v8
-; RV32-BITS-256-NEXT:    srli a2, a1, 31
-; RV32-BITS-256-NEXT:    li a0, 64
-; RV32-BITS-256-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 1
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 2
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 3
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 4
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 5
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 6
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 7
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 8
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 9
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 10
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 11
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 12
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 13
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 14
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 15
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 16
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 17
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 18
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 19
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 20
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 21
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 22
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 23
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 24
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 25
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 26
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 27
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 28
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 29
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a2, a1, 30
-; RV32-BITS-256-NEXT:    srli a2, a2, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    andi a1, a1, 1
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-256-NEXT:    vmv.x.s a1, v0
-; RV32-BITS-256-NEXT:    srli a2, a1, 31
-; RV32-BITS-256-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-256-NEXT:    slli a0, a1, 1
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 2
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 3
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 4
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 5
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 6
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 7
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 8
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 9
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 10
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 11
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 12
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 13
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 14
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 15
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 16
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 17
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 18
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 19
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 20
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 21
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 22
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 23
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 24
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 25
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 26
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 27
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 28
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a0, a1, 29
-; RV32-BITS-256-NEXT:    srli a0, a0, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    slli a1, a1, 30
-; RV32-BITS-256-NEXT:    srli a1, a1, 31
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-256-NEXT:    vfirst.m a0, v0
-; RV32-BITS-256-NEXT:    seqz a0, a0
-; RV32-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-256-NEXT:    ret
-;
-; RV32-BITS-512-LABEL: reverse_v64i1:
-; RV32-BITS-512:       # %bb.0:
-; RV32-BITS-512-NEXT:    vsetivli zero, 1, e32, mf2, ta, ma
-; RV32-BITS-512-NEXT:    vslidedown.vi v8, v0, 1
-; RV32-BITS-512-NEXT:    vmv.x.s a1, v8
-; RV32-BITS-512-NEXT:    srli a2, a1, 31
-; RV32-BITS-512-NEXT:    li a0, 64
-; RV32-BITS-512-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 1
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 2
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 3
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 4
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 5
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 6
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 7
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 8
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 9
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 10
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 11
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 12
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 13
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 14
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 15
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 16
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 17
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 18
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 19
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 20
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 21
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 22
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 23
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 24
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 25
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 26
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 27
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 28
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 29
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a2, a1, 30
-; RV32-BITS-512-NEXT:    srli a2, a2, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    andi a1, a1, 1
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    vsetivli zero, 0, e32, mf2, ta, ma
-; RV32-BITS-512-NEXT:    vmv.x.s a1, v0
-; RV32-BITS-512-NEXT:    srli a2, a1, 31
-; RV32-BITS-512-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-BITS-512-NEXT:    slli a0, a1, 1
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 2
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 3
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 4
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 5
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 6
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 7
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 8
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 9
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 10
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 11
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 12
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 13
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 14
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 15
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 16
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 17
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 18
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 19
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 20
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 21
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 22
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 23
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 24
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 25
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 26
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 27
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 28
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a0, a1, 29
-; RV32-BITS-512-NEXT:    srli a0, a0, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    slli a1, a1, 30
-; RV32-BITS-512-NEXT:    srli a1, a1, 31
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-BITS-512-NEXT:    vfirst.m a0, v0
-; RV32-BITS-512-NEXT:    seqz a0, a0
-; RV32-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV32-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV32-BITS-512-NEXT:    ret
-;
-; RV64-BITS-UNKNOWN-LABEL: reverse_v64i1:
-; RV64-BITS-UNKNOWN:       # %bb.0:
-; RV64-BITS-UNKNOWN-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    li a2, 64
-; RV64-BITS-UNKNOWN-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 1
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 2
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 3
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 4
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 5
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 6
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 7
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 8
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 9
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 10
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 11
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 12
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 13
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 14
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 15
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 16
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 17
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 18
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 19
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 20
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 21
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 22
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 23
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 24
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 25
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 26
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 27
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 28
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 29
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 30
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 31
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    srliw a1, a0, 31
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 33
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 34
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 35
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 36
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 37
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 38
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 39
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 40
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 41
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 42
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 43
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 44
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 45
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 46
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 47
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 48
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 49
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 50
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 51
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 52
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 53
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 54
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 55
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 56
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 57
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 58
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 59
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 60
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a1, a0, 61
-; RV64-BITS-UNKNOWN-NEXT:    srli a1, a1, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-UNKNOWN-NEXT:    slli a0, a0, 62
-; RV64-BITS-UNKNOWN-NEXT:    srli a0, a0, 63
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vfirst.m a0, v0
-; RV64-BITS-UNKNOWN-NEXT:    seqz a0, a0
-; RV64-BITS-UNKNOWN-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-UNKNOWN-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-UNKNOWN-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-UNKNOWN-NEXT:    ret
-;
-; RV64-BITS-256-LABEL: reverse_v64i1:
-; RV64-BITS-256:       # %bb.0:
-; RV64-BITS-256-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-BITS-256-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-256-NEXT:    srli a1, a0, 63
-; RV64-BITS-256-NEXT:    li a2, 64
-; RV64-BITS-256-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 1
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 2
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 3
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 4
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 5
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 6
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 7
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 8
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 9
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 10
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 11
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 12
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 13
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 14
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 15
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 16
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 17
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 18
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 19
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 20
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 21
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 22
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 23
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 24
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 25
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 26
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 27
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 28
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 29
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 30
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 31
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    srliw a1, a0, 31
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 33
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 34
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 35
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 36
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 37
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 38
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 39
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 40
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 41
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 42
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 43
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 44
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 45
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 46
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 47
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 48
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 49
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 50
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 51
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 52
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 53
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 54
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 55
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 56
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 57
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 58
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 59
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 60
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a1, a0, 61
-; RV64-BITS-256-NEXT:    srli a1, a1, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-256-NEXT:    slli a0, a0, 62
-; RV64-BITS-256-NEXT:    srli a0, a0, 63
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vfirst.m a0, v0
-; RV64-BITS-256-NEXT:    seqz a0, a0
-; RV64-BITS-256-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-256-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-256-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-256-NEXT:    ret
-;
-; RV64-BITS-512-LABEL: reverse_v64i1:
-; RV64-BITS-512:       # %bb.0:
-; RV64-BITS-512-NEXT:    vsetivli zero, 0, e64, m1, ta, ma
-; RV64-BITS-512-NEXT:    vmv.x.s a0, v0
-; RV64-BITS-512-NEXT:    srli a1, a0, 63
-; RV64-BITS-512-NEXT:    li a2, 64
-; RV64-BITS-512-NEXT:    vsetvli zero, a2, e8, m4, ta, ma
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 1
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 2
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 3
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 4
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 5
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 6
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 7
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 8
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 9
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 10
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 11
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 12
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 13
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 14
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 15
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 16
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 17
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 18
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 19
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 20
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 21
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 22
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 23
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 24
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 25
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 26
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 27
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 28
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 29
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 30
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 31
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    srliw a1, a0, 31
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 33
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 34
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 35
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 36
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 37
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 38
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 39
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 40
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 41
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 42
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 43
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 44
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 45
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 46
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 47
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 48
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 49
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 50
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 51
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 52
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 53
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 54
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 55
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 56
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 57
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 58
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 59
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 60
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a1, a0, 61
-; RV64-BITS-512-NEXT:    srli a1, a1, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-BITS-512-NEXT:    slli a0, a0, 62
-; RV64-BITS-512-NEXT:    srli a0, a0, 63
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vfirst.m a0, v0
-; RV64-BITS-512-NEXT:    seqz a0, a0
-; RV64-BITS-512-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-BITS-512-NEXT:    vand.vi v8, v8, 1
-; RV64-BITS-512-NEXT:    vmsne.vi v0, v8, 0
-; RV64-BITS-512-NEXT:    ret
+; CHECK-LABEL: reverse_v64i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 64
+; CHECK-NEXT:    vsetvli zero, a0, e8, m4, ta, ma
+; CHECK-NEXT:    lui a0, %hi(.LCPI5_0)
+; CHECK-NEXT:    addi a0, a0, %lo(.LCPI5_0)
+; CHECK-NEXT:    vle8.v v8, (a0)
+; CHECK-NEXT:    vmv.v.i v12, 0
+; CHECK-NEXT:    vmerge.vim v12, v12, 1, v0
+; CHECK-NEXT:    vrgather.vv v16, v12, v8
+; CHECK-NEXT:    vmsne.vi v0, v16, 0
+; CHECK-NEXT:    ret
   %res = call <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1> %a)
   ret <64 x i1> %res
 }
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
@@ -8,229 +8,57 @@
 ; RV32-LABEL: vector_deinterleave_v16i1_v32i1:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-NEXT:    vfirst.m a0, v0
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.x.s a0, v0
-; RV32-NEXT:    slli a1, a0, 29
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    slli a1, a0, 27
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    slli a1, a0, 25
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    slli a1, a0, 23
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    slli a1, a0, 21
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    slli a1, a0, 19
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    slli a1, a0, 17
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
+; RV32-NEXT:    vmv.v.i v8, 0
+; RV32-NEXT:    vmerge.vim v10, v8, 1, v0
+; RV32-NEXT:    vid.v v9
+; RV32-NEXT:    vadd.vv v11, v9, v9
+; RV32-NEXT:    vrgather.vv v9, v10, v11
 ; RV32-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
-; RV32-NEXT:    vslidedown.vi v9, v0, 2
-; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-NEXT:    vfirst.m a1, v9
-; RV32-NEXT:    seqz a1, a1
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.x.s a1, v9
-; RV32-NEXT:    slli a2, a1, 29
-; RV32-NEXT:    srli a2, a2, 31
+; RV32-NEXT:    vslidedown.vi v0, v0, 2
 ; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 27
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 25
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 23
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 21
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 19
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 17
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    vand.vi v8, v8, 1
-; RV32-NEXT:    vmsne.vi v0, v8, 0
-; RV32-NEXT:    slli a2, a0, 30
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 28
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 26
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 24
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 22
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 20
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 18
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a0, a0, 16
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 30
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 28
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 26
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 24
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 22
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 20
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a0, a1, 18
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a1, a1, 16
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    vand.vi v8, v8, 1
-; RV32-NEXT:    vmsne.vi v8, v8, 0
+; RV32-NEXT:    vmerge.vim v8, v8, 1, v0
+; RV32-NEXT:    lui a0, 16
+; RV32-NEXT:    addi a0, a0, -256
+; RV32-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV32-NEXT:    vmv.s.x v0, a0
+; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; RV32-NEXT:    vadd.vi v12, v11, -16
+; RV32-NEXT:    vrgather.vv v9, v8, v12, v0.t
+; RV32-NEXT:    vmsne.vi v9, v9, 0
+; RV32-NEXT:    vadd.vi v12, v11, 1
+; RV32-NEXT:    vrgather.vv v13, v10, v12
+; RV32-NEXT:    vadd.vi v10, v11, -15
+; RV32-NEXT:    vrgather.vv v13, v8, v10, v0.t
+; RV32-NEXT:    vmsne.vi v8, v13, 0
+; RV32-NEXT:    vmv.v.v v0, v9
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vector_deinterleave_v16i1_v32i1:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-NEXT:    vfirst.m a0, v0
-; RV64-NEXT:    seqz a0, a0
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.x.s a0, v0
-; RV64-NEXT:    slli a1, a0, 61
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    slli a1, a0, 59
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    slli a1, a0, 57
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    slli a1, a0, 55
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    slli a1, a0, 53
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    slli a1, a0, 51
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    slli a1, a0, 49
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
+; RV64-NEXT:    vmv.v.i v8, 0
+; RV64-NEXT:    vmerge.vim v10, v8, 1, v0
+; RV64-NEXT:    vid.v v9
+; RV64-NEXT:    vadd.vv v11, v9, v9
+; RV64-NEXT:    vrgather.vv v9, v10, v11
 ; RV64-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
-; RV64-NEXT:    vslidedown.vi v9, v0, 2
-; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-NEXT:    vfirst.m a1, v9
-; RV64-NEXT:    seqz a1, a1
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.x.s a1, v9
-; RV64-NEXT:    slli a2, a1, 61
-; RV64-NEXT:    srli a2, a2, 63
+; RV64-NEXT:    vslidedown.vi v0, v0, 2
 ; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 59
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 57
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 55
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 53
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 51
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 49
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    vand.vi v8, v8, 1
-; RV64-NEXT:    vmsne.vi v0, v8, 0
-; RV64-NEXT:    slli a2, a0, 62
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 60
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 58
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 56
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 54
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 52
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 50
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a0, a0, 48
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 62
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 60
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 58
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 56
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 54
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 52
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a0, a1, 50
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a1, a1, 48
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    vand.vi v8, v8, 1
-; RV64-NEXT:    vmsne.vi v8, v8, 0
+; RV64-NEXT:    vmerge.vim v8, v8, 1, v0
+; RV64-NEXT:    lui a0, 16
+; RV64-NEXT:    addiw a0, a0, -256
+; RV64-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
+; RV64-NEXT:    vmv.s.x v0, a0
+; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, mu
+; RV64-NEXT:    vadd.vi v12, v11, -16
+; RV64-NEXT:    vrgather.vv v9, v8, v12, v0.t
+; RV64-NEXT:    vmsne.vi v9, v9, 0
+; RV64-NEXT:    vadd.vi v12, v11, 1
+; RV64-NEXT:    vrgather.vv v13, v10, v12
+; RV64-NEXT:    vadd.vi v10, v11, -15
+; RV64-NEXT:    vrgather.vv v13, v8, v10, v0.t
+; RV64-NEXT:    vmsne.vi v8, v13, 0
+; RV64-NEXT:    vmv.v.v v0, v9
 ; RV64-NEXT:    ret
 %retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec)
 ret {<16 x i1>, <16 x i1>} %retval
diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll
@@ -5,231 +5,28 @@
 ; Integers
 
 define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
-; RV32-LABEL: vector_interleave_v32i1_v16i1:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-NEXT:    vfirst.m a0, v0
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    li a2, 32
-; RV32-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-NEXT:    vslide1down.vx v10, v8, a0
-; RV32-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV32-NEXT:    vfirst.m a0, v8
-; RV32-NEXT:    seqz a0, a0
-; RV32-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-NEXT:    vslide1down.vx v10, v10, a0
-; RV32-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.x.s a0, v0
-; RV32-NEXT:    slli a1, a0, 30
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-NEXT:    vslide1down.vx v10, v10, a1
-; RV32-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV32-NEXT:    vmv.x.s a1, v8
-; RV32-NEXT:    slli a3, a1, 30
-; RV32-NEXT:    srli a3, a3, 31
-; RV32-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV32-NEXT:    vslide1down.vx v8, v10, a3
-; RV32-NEXT:    slli a2, a0, 29
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 29
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 28
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 28
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 27
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 27
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 26
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 26
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 25
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 25
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 24
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 24
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 23
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 23
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 22
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 22
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 21
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 21
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 20
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 20
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 19
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 19
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 18
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 18
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a0, 17
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a2, a1, 17
-; RV32-NEXT:    srli a2, a2, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a2
-; RV32-NEXT:    slli a0, a0, 16
-; RV32-NEXT:    srli a0, a0, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a0
-; RV32-NEXT:    slli a1, a1, 16
-; RV32-NEXT:    srli a1, a1, 31
-; RV32-NEXT:    vslide1down.vx v8, v8, a1
-; RV32-NEXT:    vand.vi v8, v8, 1
-; RV32-NEXT:    vmsne.vi v0, v8, 0
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vector_interleave_v32i1_v16i1:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-NEXT:    vfirst.m a0, v0
-; RV64-NEXT:    seqz a0, a0
-; RV64-NEXT:    li a2, 32
-; RV64-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-NEXT:    vslide1down.vx v10, v8, a0
-; RV64-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; RV64-NEXT:    vfirst.m a0, v8
-; RV64-NEXT:    seqz a0, a0
-; RV64-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-NEXT:    vslide1down.vx v10, v10, a0
-; RV64-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.x.s a0, v0
-; RV64-NEXT:    slli a1, a0, 62
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-NEXT:    vslide1down.vx v10, v10, a1
-; RV64-NEXT:    vsetivli zero, 0, e16, mf4, ta, ma
-; RV64-NEXT:    vmv.x.s a1, v8
-; RV64-NEXT:    slli a3, a1, 62
-; RV64-NEXT:    srli a3, a3, 63
-; RV64-NEXT:    vsetvli zero, a2, e8, m2, ta, ma
-; RV64-NEXT:    vslide1down.vx v8, v10, a3
-; RV64-NEXT:    slli a2, a0, 61
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 61
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 60
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 60
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 59
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 59
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 58
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 58
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 57
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 57
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 56
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 56
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 55
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 55
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 54
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 54
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 53
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 53
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 52
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 52
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 51
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 51
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 50
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 50
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a0, 49
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a2, a1, 49
-; RV64-NEXT:    srli a2, a2, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a2
-; RV64-NEXT:    slli a0, a0, 48
-; RV64-NEXT:    srli a0, a0, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a0
-; RV64-NEXT:    slli a1, a1, 48
-; RV64-NEXT:    srli a1, a1, 63
-; RV64-NEXT:    vslide1down.vx v8, v8, a1
-; RV64-NEXT:    vand.vi v8, v8, 1
-; RV64-NEXT:    vmsne.vi v0, v8, 0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vector_interleave_v32i1_v16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 32
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT:    vmclr.m v9
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, tu, ma
+; CHECK-NEXT:    vslideup.vi v9, v0, 0
+; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
+; CHECK-NEXT:    vslideup.vi v9, v8, 2
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT:    vmv.v.i v10, 0
+; CHECK-NEXT:    vmv1r.v v0, v9
+; CHECK-NEXT:    vmerge.vim v8, v10, 1, v0
+; CHECK-NEXT:    vsetivli zero, 16, e8, m2, ta, ma
+; CHECK-NEXT:    vslidedown.vi v10, v8, 16
+; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
+; CHECK-NEXT:    vwaddu.vv v12, v8, v10
+; CHECK-NEXT:    li a1, -1
+; CHECK-NEXT:    vwmaccu.vx v12, a1, v10
+; CHECK-NEXT:    vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT:    vmsne.vi v0, v12, 0
+; CHECK-NEXT:    ret
 	   %res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
 	   ret <32 x i1> %res
 }