diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -83,7 +83,8 @@
 template <std::size_t N>
 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
                                         const MCPhysReg (&Regs)[N]) {
-  assert(RegNo < N && "Invalid register number");
+  if (RegNo >= N)
+    return MCDisassembler::Fail;
   Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
   return MCDisassembler::Success;
 }
@@ -115,8 +116,8 @@
 static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder) {
-  assert(RegNo <= 30 && "Expecting a register number no more than 30.");
-  assert((RegNo & 1) == 0 && "Expecting an even register number.");
+  if (RegNo > 30 || (RegNo & 1))
+    return MCDisassembler::Fail;
   return decodeRegisterClass(Inst, RegNo >> 1, FpRegs);
 }
 
@@ -348,7 +349,8 @@
   // The cr bit encoding is 0x80 >> cr_reg_num.
 
   unsigned Zeros = llvm::countr_zero(Imm);
-  assert(Zeros < 8 && "Invalid CR bit value");
+  if (Zeros >= 8)
+    return MCDisassembler::Fail;
 
   Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
   return MCDisassembler::Success;
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp-invalid.txt
@@ -0,0 +1,7 @@
+# RUN: llvm-mc --disassemble %s -mcpu=pwr10 -triple \
+# RUN:   powerpc64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
+
+# Regsiter for DSUBQ cannot be greater than 30.
+# CHECK-NOT: dsubq 0, 6, 31
+# CHECK: warning: invalid instruction encoding
+0xfc 0x06 0xfc 0x04