diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2255,7 +2255,14 @@
 // Miscellaneous
 let HasMasked = false, HasVL = false, IRName = "" in {
   let Name = "vreinterpret_v", MaskedPolicyScheme = NonePolicy,
+      IRName = "vreinterpret_v",
       ManualCodegen = [{
+        if (ResultType->isIntOrIntVectorTy(1) ||
+            Ops[0]->getType()->isIntOrIntVectorTy(1)) {
+          ID = Intrinsic::riscv_vreinterpret_v;
+          IntrinsicTypes = {ResultType, Ops[0]->getType()};
+          break;
+        }
         return Builder.CreateBitCast(Ops[0], ResultType);
       }] in {
     // Reinterpret between different type under the same SEW and LMUL
@@ -2274,6 +2281,53 @@
       def vreinterpret_u_ # dst_sew : RVVBuiltin<"Uv" # dst_sew # "Uv",
                                                  dst_sew # "UvUv", "csil", dst_sew # "Uv">;
     }
+
+    // Existing users of FixedSEW - the reinterpretation between different SEW
+    // and same LMUL has the implicit assumption that if FixedSEW is set to the
+    // given element width, then the type will be identified as invalid, thus
+    // skipping definition of reinterpret of SEW=8 to SEW=8. However this blocks
+    // our usage here of defining all possible combinations of a fixed SEW to
+    // any boolean. So we need to separately define SEW=8 here.
+    // Reinterpret from LMUL=1 integer type to vector boolean type
+    def vreintrepret_m1_b8_signed :
+        RVVBuiltin<"Svm",
+                    "mSv",
+                    "c", "m">;
+    def vreintrepret_m1_b8_usigned :
+        RVVBuiltin<"USvm",
+                    "mUSv",
+                    "c", "m">;
+
+    // Reinterpret from vector boolean type to LMUL=1 integer type
+    def vreintrepret_b8_m1_signed :
+        RVVBuiltin<"mSv",
+                    "Svm",
+                    "c", "Sv">;
+    def vreintrepret_b8_m1_usigned :
+        RVVBuiltin<"mUSv",
+                    "USvm",
+                    "c", "USv">;
+
+    foreach dst_sew = ["16", "32", "64"] in {
+      // Reinterpret from LMUL=1 integer type to vector boolean type
+      def vreinterpret_m1_b # dst_sew # _signed:
+        RVVBuiltin<"(FixedSEW:" # dst_sew # ")Svm",
+                    "m(FixedSEW:" # dst_sew # ")Sv",
+                    "c", "m">;
+      def vreinterpret_m1_b # dst_sew # _unsigned:
+        RVVBuiltin<"(FixedSEW:" # dst_sew # ")USvm",
+                    "m(FixedSEW:" # dst_sew # ")USv",
+                    "c", "m">;
+      // Reinterpret from vector boolean type to LMUL=1 integer type
+      def vreinterpret_b # dst_sew # _m1_signed:
+        RVVBuiltin<"m(FixedSEW:" # dst_sew # ")Sv",
+                    "(FixedSEW:" # dst_sew # ")Svm",
+                    "c", "(FixedSEW:" # dst_sew # ")Sv">;
+      def vreinterpret_b # dst_sew # _m1_unsigned:
+        RVVBuiltin<"m(FixedSEW:" # dst_sew # ")USv",
+                    "(FixedSEW:" # dst_sew # ")USvm",
+                    "c", "(FixedSEW:" # dst_sew # ")USv">;
+    }
   }
 
   let Name = "vundefined", SupportOverloading = false,
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vreinterpret.c
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
 // RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
@@ -7,1903 +7,2999 @@
 
 #include <riscv_vector.h>
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC]]
 //
 vuint8mf8_t test_vreinterpret_v_i8mf8_u8mf8(vint8mf8_t src) {
   return __riscv_vreinterpret_v_i8mf8_u8mf8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf4_u8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC]]
 //
 vuint8mf4_t test_vreinterpret_v_i8mf4_u8mf4(vint8mf4_t src) {
   return __riscv_vreinterpret_v_i8mf4_u8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_u8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC]]
 //
 vuint8mf2_t test_vreinterpret_v_i8mf2_u8mf2(vint8mf2_t src) {
   return __riscv_vreinterpret_v_i8mf2_u8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 //
 vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src) {
   return __riscv_vreinterpret_v_i8m1_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 //
 vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src) {
   return __riscv_vreinterpret_v_i8m2_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 //
 vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src) {
   return __riscv_vreinterpret_v_i8m4_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 //
 vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src) {
   return __riscv_vreinterpret_v_i8m8_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf8_i8mf8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC]]
 //
 vint8mf8_t test_vreinterpret_v_u8mf8_i8mf8(vuint8mf8_t src) {
   return __riscv_vreinterpret_v_u8mf8_i8mf8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf4_i8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC]]
 //
 vint8mf4_t test_vreinterpret_v_u8mf4_i8mf4(vuint8mf4_t src) {
   return __riscv_vreinterpret_v_u8mf4_i8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_i8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC]]
 //
 vint8mf2_t test_vreinterpret_v_u8mf2_i8mf2(vuint8mf2_t src) {
   return __riscv_vreinterpret_v_u8mf2_i8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 //
 vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src) {
   return __riscv_vreinterpret_v_u8m1_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 //
 vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src) {
   return __riscv_vreinterpret_v_u8m2_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 //
 vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src) {
   return __riscv_vreinterpret_v_u8m4_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 //
 vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src) {
   return __riscv_vreinterpret_v_u8m8_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_f16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 1 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]
 //
 vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {
   return __riscv_vreinterpret_v_i16mf4_f16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_f16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 2 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
 //
 vfloat16mf2_t test_vreinterpret_v_i16mf2_f16mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_v_i16mf2_f16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_f16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 4 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 //
 vfloat16m1_t test_vreinterpret_v_i16m1_f16m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_f16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 8 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 //
 vfloat16m2_t test_vreinterpret_v_i16m2_f16m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_f16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 16 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 //
 vfloat16m4_t test_vreinterpret_v_i16m4_f16m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_f16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 32 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 //
 vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_f16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 1 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]
 //
 vfloat16mf4_t test_vreinterpret_v_u16mf4_f16mf4(vuint16mf4_t src) {
   return __riscv_vreinterpret_v_u16mf4_f16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_f16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 2 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
 //
 vfloat16mf2_t test_vreinterpret_v_u16mf2_f16mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_v_u16mf2_f16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_f16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 4 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 //
 vfloat16m1_t test_vreinterpret_v_u16m1_f16m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_f16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 8 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 //
 vfloat16m2_t test_vreinterpret_v_u16m2_f16m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_f16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 16 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 //
 vfloat16m4_t test_vreinterpret_v_u16m4_f16m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_f16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 32 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 //
 vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_u16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_i16mf4_u16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC]]
 //
 vuint16mf4_t test_vreinterpret_v_i16mf4_u16mf4(vint16mf4_t src) {
   return __riscv_vreinterpret_v_i16mf4_u16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i16mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC]]
 //
 vuint16mf2_t test_vreinterpret_v_i16mf2_u16mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_v_i16mf2_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 //
 vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 //
 vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 //
 vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 //
 vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_i16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_u16mf4_i16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC]]
 //
 vint16mf4_t test_vreinterpret_v_u16mf4_i16mf4(vuint16mf4_t src) {
   return __riscv_vreinterpret_v_u16mf4_i16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u16mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC]]
 //
 vint16mf2_t test_vreinterpret_v_u16mf2_i16mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_v_u16mf2_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 //
 vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 //
 vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 //
 vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 //
 vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf4_i16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_f16mf4_i16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vint16mf4_t test_vreinterpret_v_f16mf4_i16mf4(vfloat16mf4_t src) {
   return __riscv_vreinterpret_v_f16mf4_i16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_f16mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vint16mf2_t test_vreinterpret_v_f16mf2_i16mf2(vfloat16mf2_t src) {
   return __riscv_vreinterpret_v_f16mf2_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_f16m1_i16m1(vfloat16m1_t src) {
   return __riscv_vreinterpret_v_f16m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_f16m2_i16m2(vfloat16m2_t src) {
   return __riscv_vreinterpret_v_f16m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_f16m4_i16m4(vfloat16m4_t src) {
   return __riscv_vreinterpret_v_f16m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {
   return __riscv_vreinterpret_v_f16m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf4_u16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_f16mf4_u16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vuint16mf4_t test_vreinterpret_v_f16mf4_u16mf4(vfloat16mf4_t src) {
   return __riscv_vreinterpret_v_f16mf4_u16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_f16mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vuint16mf2_t test_vreinterpret_v_f16mf2_u16mf2(vfloat16mf2_t src) {
   return __riscv_vreinterpret_v_f16mf2_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_f16m1_u16m1(vfloat16m1_t src) {
   return __riscv_vreinterpret_v_f16m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_f16m2_u16m2(vfloat16m2_t src) {
   return __riscv_vreinterpret_v_f16m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_f16m4_u16m4(vfloat16m4_t src) {
   return __riscv_vreinterpret_v_f16m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
   return __riscv_vreinterpret_v_f16m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_f32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vreinterpret_v_i32mf2_f32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 1 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 1 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]
 //
 vfloat32mf2_t test_vreinterpret_v_i32mf2_f32mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_v_i32mf2_f32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_f32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 2 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 //
 vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_f32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 4 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 //
 vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_f32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 8 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 //
 vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_f32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 16 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 //
 vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_f32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vreinterpret_v_u32mf2_f32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 1 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 1 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]
 //
 vfloat32mf2_t test_vreinterpret_v_u32mf2_f32mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_v_u32mf2_f32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_f32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 2 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 //
 vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_f32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 4 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 //
 vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_f32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 8 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 //
 vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_f32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 16 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 //
 vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i32mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC]]
 //
 vuint32mf2_t test_vreinterpret_v_i32mf2_u32mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_v_i32mf2_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 //
 vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 //
 vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 //
 vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 //
 vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u32mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC]]
 //
 vint32mf2_t test_vreinterpret_v_u32mf2_i32mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_v_u32mf2_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 //
 vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 //
 vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 //
 vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 //
 vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_f32mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vint32mf2_t test_vreinterpret_v_f32mf2_i32mf2(vfloat32mf2_t src) {
   return __riscv_vreinterpret_v_f32mf2_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src) {
   return __riscv_vreinterpret_v_f32m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src) {
   return __riscv_vreinterpret_v_f32m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src) {
   return __riscv_vreinterpret_v_f32m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src) {
   return __riscv_vreinterpret_v_f32m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_f32mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vuint32mf2_t test_vreinterpret_v_f32mf2_u32mf2(vfloat32mf2_t src) {
   return __riscv_vreinterpret_v_f32mf2_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src) {
   return __riscv_vreinterpret_v_f32m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src) {
   return __riscv_vreinterpret_v_f32m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src) {
   return __riscv_vreinterpret_v_f32m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src) {
   return __riscv_vreinterpret_v_f32m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_f64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 1 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 //
 vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_f64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 2 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 //
 vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_f64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 4 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 //
 vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_f64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 8 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 //
 vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_f64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 1 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 //
 vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_f64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 2 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 //
 vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_f64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 4 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 //
 vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_f64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 8 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 //
 vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 //
 vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 //
 vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 //
 vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 //
 vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 //
 vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 //
 vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 //
 vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 //
 vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src) {
   return __riscv_vreinterpret_v_f64m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src) {
   return __riscv_vreinterpret_v_f64m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src) {
   return __riscv_vreinterpret_v_f64m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src) {
   return __riscv_vreinterpret_v_f64m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src) {
   return __riscv_vreinterpret_v_f64m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src) {
   return __riscv_vreinterpret_v_f64m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src) {
   return __riscv_vreinterpret_v_f64m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_f64m8_u64m8(vfloat64m8_t src) {
   return __riscv_vreinterpret_v_f64m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf4_i16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_i8mf4_i16mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vint16mf4_t test_vreinterpret_v_i8mf4_i16mf4(vint8mf4_t src) {
   return __riscv_vreinterpret_v_i8mf4_i16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i8mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vint16mf2_t test_vreinterpret_v_i8mf2_i16mf2(vint8mf2_t src) {
   return __riscv_vreinterpret_v_i8mf2_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i8m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src) {
   return __riscv_vreinterpret_v_i8m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i8m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src) {
   return __riscv_vreinterpret_v_i8m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i8m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src) {
   return __riscv_vreinterpret_v_i8m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i8m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src) {
   return __riscv_vreinterpret_v_i8m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf4_u16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_u8mf4_u16mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vuint16mf4_t test_vreinterpret_v_u8mf4_u16mf4(vuint8mf4_t src) {
   return __riscv_vreinterpret_v_u8mf4_u16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u8mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vuint16mf2_t test_vreinterpret_v_u8mf2_u16mf2(vuint8mf2_t src) {
   return __riscv_vreinterpret_v_u8mf2_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u8m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src) {
   return __riscv_vreinterpret_v_u8m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u8m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src) {
   return __riscv_vreinterpret_v_u8m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u8m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src) {
   return __riscv_vreinterpret_v_u8m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u8m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src) {
   return __riscv_vreinterpret_v_u8m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i8mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vint32mf2_t test_vreinterpret_v_i8mf2_i32mf2(vint8mf2_t src) {
   return __riscv_vreinterpret_v_i8mf2_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i8m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src) {
   return __riscv_vreinterpret_v_i8m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i8m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src) {
   return __riscv_vreinterpret_v_i8m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i8m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src) {
   return __riscv_vreinterpret_v_i8m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i8m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src) {
   return __riscv_vreinterpret_v_i8m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u8mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vuint32mf2_t test_vreinterpret_v_u8mf2_u32mf2(vuint8mf2_t src) {
   return __riscv_vreinterpret_v_u8mf2_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u8m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src) {
   return __riscv_vreinterpret_v_u8m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u8m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src) {
   return __riscv_vreinterpret_v_u8m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u8m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src) {
   return __riscv_vreinterpret_v_u8m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u8m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src) {
   return __riscv_vreinterpret_v_u8m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i8m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src) {
   return __riscv_vreinterpret_v_i8m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i8m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src) {
   return __riscv_vreinterpret_v_i8m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i8m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src) {
   return __riscv_vreinterpret_v_i8m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i8m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src) {
   return __riscv_vreinterpret_v_i8m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u8m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src) {
   return __riscv_vreinterpret_v_u8m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u8m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src) {
   return __riscv_vreinterpret_v_u8m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u8m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src) {
   return __riscv_vreinterpret_v_u8m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u8m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src) {
   return __riscv_vreinterpret_v_u8m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_i8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i16mf4_i8mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 2 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 2 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
 //
 vint8mf4_t test_vreinterpret_v_i16mf4_i8mf4(vint16mf4_t src) {
   return __riscv_vreinterpret_v_i16mf4_i8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_i8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i16mf2_i8mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vint8mf2_t test_vreinterpret_v_i16mf2_i8mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_v_i16mf2_i8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i16m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i16m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i16m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i16m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_u8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u16mf4_u8mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 2 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 2 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
 //
 vuint8mf4_t test_vreinterpret_v_u16mf4_u8mf4(vuint16mf4_t src) {
   return __riscv_vreinterpret_v_u16mf4_u8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_u8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u16mf2_u8mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vuint8mf2_t test_vreinterpret_v_u16mf2_u8mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_v_u16mf2_u8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u16m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u16m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u16m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u16m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i16mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vint32mf2_t test_vreinterpret_v_i16mf2_i32mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_v_i16mf2_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i16m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i16m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i16m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i16m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u16mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vuint32mf2_t test_vreinterpret_v_u16mf2_u32mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_v_u16mf2_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u16m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u16m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u16m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u16m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i16m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src) {
   return __riscv_vreinterpret_v_i16m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i16m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src) {
   return __riscv_vreinterpret_v_i16m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i16m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src) {
   return __riscv_vreinterpret_v_i16m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i16m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src) {
   return __riscv_vreinterpret_v_i16m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u16m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src) {
   return __riscv_vreinterpret_v_u16m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u16m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src) {
   return __riscv_vreinterpret_v_u16m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u16m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src) {
   return __riscv_vreinterpret_v_u16m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u16m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src) {
   return __riscv_vreinterpret_v_u16m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_i8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i32mf2_i8mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vint8mf2_t test_vreinterpret_v_i32mf2_i8mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_v_i32mf2_i8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i32m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i32m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i32m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i32m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_u8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u32mf2_u8mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vuint8mf2_t test_vreinterpret_v_u32mf2_u8mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_v_u32mf2_u8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u32m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u32m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u32m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u32m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i32mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vint16mf2_t test_vreinterpret_v_i32mf2_i16mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_v_i32mf2_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i32m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i32m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i32m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i32m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u32mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vuint16mf2_t test_vreinterpret_v_u32mf2_u16mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_v_u32mf2_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u32m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u32m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u32m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u32m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i32m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src) {
   return __riscv_vreinterpret_v_i32m1_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i32m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src) {
   return __riscv_vreinterpret_v_i32m2_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i32m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src) {
   return __riscv_vreinterpret_v_i32m4_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i32m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src) {
   return __riscv_vreinterpret_v_i32m8_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u32m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src) {
   return __riscv_vreinterpret_v_u32m1_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u32m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src) {
   return __riscv_vreinterpret_v_u32m2_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u32m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src) {
   return __riscv_vreinterpret_v_u32m4_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u32m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src) {
   return __riscv_vreinterpret_v_u32m8_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i64m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i64m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i64m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i64m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u64m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u64m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u64m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u64m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i64m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i64m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i64m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i64m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u64m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u64m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u64m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u64m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i64m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src) {
   return __riscv_vreinterpret_v_i64m1_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i64m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src) {
   return __riscv_vreinterpret_v_i64m2_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i64m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src) {
   return __riscv_vreinterpret_v_i64m4_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i64m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src) {
   return __riscv_vreinterpret_v_i64m8_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u64m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src) {
   return __riscv_vreinterpret_v_u64m1_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u64m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src) {
   return __riscv_vreinterpret_v_u64m2_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u64m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src) {
   return __riscv_vreinterpret_v_u64m4_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u64m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src) {
   return __riscv_vreinterpret_v_u64m8_u32m8(src);
 }
 
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i8m1_b64(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_i8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b64_i8m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i8m1_b32(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_i8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b32_i8m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i8m1_b16(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_i8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b16_i8m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i8m1_b8(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b8_i8m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_i8m1_b4(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_i8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b4_i8m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_i8m1_b2(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_i8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b2_i8m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_i8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vreinterpret.v.nxv64i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
+//
+vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {
+  return __riscv_vreinterpret_v_i8m1_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_i8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv64i1(<vscale x 64 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b1_i8m1(vbool1_t src) {
+  return __riscv_vreinterpret_v_b1_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u8m1_b64(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_u8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b64_u8m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u8m1_b32(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_u8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b32_u8m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u8m1_b16(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_u8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b16_u8m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u8m1_b8(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b8_u8m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_u8m1_b4(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_u8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b4_u8m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_u8m1_b2(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_u8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b2_u8m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_u8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vreinterpret.v.nxv64i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
+//
+vbool1_t test_vreinterpret_v_u8m1_b1(vuint8m1_t src) {
+  return __riscv_vreinterpret_v_u8m1_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_u8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv64i1(<vscale x 64 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b1_u8m1(vbool1_t src) {
+  return __riscv_vreinterpret_v_b1_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i16m1_b64(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_i16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b64_i16m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i16m1_b32(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_i16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b32_i16m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i16m1_b16(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b16_i16m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i16m1_b8(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_i16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b8_i16m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_i16m1_b4(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_i16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b4_i16m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_i16m1_b2(vint16m1_t src) {
+  return __riscv_vreinterpret_v_i16m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_i16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b2_i16m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u16m1_b64(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_u16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b64_u16m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u16m1_b32(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_u16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b32_u16m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u16m1_b16(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b16_u16m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u16m1_b8(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_u16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b8_u16m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_u16m1_b4(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_u16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b4_u16m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_u16m1_b2(vuint16m1_t src) {
+  return __riscv_vreinterpret_v_u16m1_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_u16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b2_u16m1(vbool2_t src) {
+  return __riscv_vreinterpret_v_b2_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i32m1_b64(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_i32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b64_i32m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i32m1_b32(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b32_i32m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i32m1_b16(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_i32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b16_i32m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i32m1_b8(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_i32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b8_i32m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_i32m1_b4(vint32m1_t src) {
+  return __riscv_vreinterpret_v_i32m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_i32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b4_i32m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u32m1_b64(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_u32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b64_u32m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u32m1_b32(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b32_u32m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u32m1_b16(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_u32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b16_u32m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u32m1_b8(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_u32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b8_u32m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_u32m1_b4(vuint32m1_t src) {
+  return __riscv_vreinterpret_v_u32m1_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_u32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b4_u32m1(vbool4_t src) {
+  return __riscv_vreinterpret_v_b4_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i64m1_b64(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b64_i64m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i64m1_b32(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_i64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b32_i64m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i64m1_b16(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_i64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b16_i64m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i64m1_b8(vint64m1_t src) {
+  return __riscv_vreinterpret_v_i64m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_i64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b8_i64m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u64m1_b64(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b64_u64m1(vbool64_t src) {
+  return __riscv_vreinterpret_v_b64_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u64m1_b32(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_u64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b32_u64m1(vbool32_t src) {
+  return __riscv_vreinterpret_v_b32_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u64m1_b16(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_u64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b16_u64m1(vbool16_t src) {
+  return __riscv_vreinterpret_v_b16_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u64m1_b8(vuint64m1_t src) {
+  return __riscv_vreinterpret_v_u64m1_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_u64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b8_u64m1(vbool8_t src) {
+  return __riscv_vreinterpret_v_b8_u64m1(src);
+}
+
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vreinterpret.c
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
 // RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
@@ -7,1903 +7,2999 @@
 
 #include <riscv_vector.h>
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf8_u8mf8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_i8mf8_u8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC]]
 //
 vuint8mf8_t test_vreinterpret_v_i8mf8_u8mf8(vint8mf8_t src) {
   return __riscv_vreinterpret_u8mf8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf4_u8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i8mf4_u8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC]]
 //
 vuint8mf4_t test_vreinterpret_v_i8mf4_u8mf4(vint8mf4_t src) {
   return __riscv_vreinterpret_u8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_u8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i8mf2_u8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC]]
 //
 vuint8mf2_t test_vreinterpret_v_i8mf2_u8mf2(vint8mf2_t src) {
   return __riscv_vreinterpret_u8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i8m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 //
 vuint8m1_t test_vreinterpret_v_i8m1_u8m1(vint8m1_t src) {
   return __riscv_vreinterpret_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i8m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 //
 vuint8m2_t test_vreinterpret_v_i8m2_u8m2(vint8m2_t src) {
   return __riscv_vreinterpret_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i8m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 //
 vuint8m4_t test_vreinterpret_v_i8m4_u8m4(vint8m4_t src) {
   return __riscv_vreinterpret_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i8m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 //
 vuint8m8_t test_vreinterpret_v_i8m8_u8m8(vint8m8_t src) {
   return __riscv_vreinterpret_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf8_i8mf8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vreinterpret_v_u8mf8_i8mf8
+// CHECK-RV64-SAME: (<vscale x 1 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i8> [[SRC]]
 //
 vint8mf8_t test_vreinterpret_v_u8mf8_i8mf8(vuint8mf8_t src) {
   return __riscv_vreinterpret_i8mf8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf4_i8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u8mf4_i8mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[SRC]]
 //
 vint8mf4_t test_vreinterpret_v_u8mf4_i8mf4(vuint8mf4_t src) {
   return __riscv_vreinterpret_i8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_i8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u8mf2_i8mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[SRC]]
 //
 vint8mf2_t test_vreinterpret_v_u8mf2_i8mf2(vuint8mf2_t src) {
   return __riscv_vreinterpret_i8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u8m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[SRC]]
 //
 vint8m1_t test_vreinterpret_v_u8m1_i8m1(vuint8m1_t src) {
   return __riscv_vreinterpret_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u8m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[SRC]]
 //
 vint8m2_t test_vreinterpret_v_u8m2_i8m2(vuint8m2_t src) {
   return __riscv_vreinterpret_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u8m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[SRC]]
 //
 vint8m4_t test_vreinterpret_v_u8m4_i8m4(vuint8m4_t src) {
   return __riscv_vreinterpret_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u8m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[SRC]]
 //
 vint8m8_t test_vreinterpret_v_u8m8_i8m8(vuint8m8_t src) {
   return __riscv_vreinterpret_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_f16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vreinterpret_v_i16mf4_f16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 1 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]
 //
 vfloat16mf4_t test_vreinterpret_v_i16mf4_f16mf4(vint16mf4_t src) {
   return __riscv_vreinterpret_f16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_f16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vreinterpret_v_i16mf2_f16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 2 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
 //
 vfloat16mf2_t test_vreinterpret_v_i16mf2_f16mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_f16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_f16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_i16m1_f16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 4 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 //
 vfloat16m1_t test_vreinterpret_v_i16m1_f16m1(vint16m1_t src) {
   return __riscv_vreinterpret_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_f16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_i16m2_f16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 8 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 //
 vfloat16m2_t test_vreinterpret_v_i16m2_f16m2(vint16m2_t src) {
   return __riscv_vreinterpret_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_f16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_i16m4_f16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 16 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 //
 vfloat16m4_t test_vreinterpret_v_i16m4_f16m4(vint16m4_t src) {
   return __riscv_vreinterpret_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_f16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_i16m8_f16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 32 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 //
 vfloat16m8_t test_vreinterpret_v_i16m8_f16m8(vint16m8_t src) {
   return __riscv_vreinterpret_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_f16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vreinterpret_v_u16mf4_f16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 1 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 1 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x half> [[TMP0]]
 //
 vfloat16mf4_t test_vreinterpret_v_u16mf4_f16mf4(vuint16mf4_t src) {
   return __riscv_vreinterpret_f16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_f16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vreinterpret_v_u16mf2_f16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 2 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 2 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x half> [[TMP0]]
 //
 vfloat16mf2_t test_vreinterpret_v_u16mf2_f16mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_f16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_f16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vreinterpret_v_u16m1_f16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 4 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 4 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x half> [[TMP0]]
 //
 vfloat16m1_t test_vreinterpret_v_u16m1_f16m1(vuint16m1_t src) {
   return __riscv_vreinterpret_f16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_f16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vreinterpret_v_u16m2_f16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 8 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 8 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x half> [[TMP0]]
 //
 vfloat16m2_t test_vreinterpret_v_u16m2_f16m2(vuint16m2_t src) {
   return __riscv_vreinterpret_f16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_f16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vreinterpret_v_u16m4_f16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 16 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 16 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x half> [[TMP0]]
 //
 vfloat16m4_t test_vreinterpret_v_u16m4_f16m4(vuint16m4_t src) {
   return __riscv_vreinterpret_f16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_f16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vreinterpret_v_u16m8_f16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 32 x half>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 32 x half>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x half> [[TMP0]]
 //
 vfloat16m8_t test_vreinterpret_v_u16m8_f16m8(vuint16m8_t src) {
   return __riscv_vreinterpret_f16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_u16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_i16mf4_u16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC]]
 //
 vuint16mf4_t test_vreinterpret_v_i16mf4_u16mf4(vint16mf4_t src) {
   return __riscv_vreinterpret_u16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i16mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC]]
 //
 vuint16mf2_t test_vreinterpret_v_i16mf2_u16mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i16m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 //
 vuint16m1_t test_vreinterpret_v_i16m1_u16m1(vint16m1_t src) {
   return __riscv_vreinterpret_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i16m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 //
 vuint16m2_t test_vreinterpret_v_i16m2_u16m2(vint16m2_t src) {
   return __riscv_vreinterpret_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i16m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 //
 vuint16m4_t test_vreinterpret_v_i16m4_u16m4(vint16m4_t src) {
   return __riscv_vreinterpret_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i16m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 //
 vuint16m8_t test_vreinterpret_v_i16m8_u16m8(vint16m8_t src) {
   return __riscv_vreinterpret_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_i16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_u16mf4_i16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[SRC]]
 //
 vint16mf4_t test_vreinterpret_v_u16mf4_i16mf4(vuint16mf4_t src) {
   return __riscv_vreinterpret_i16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u16mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[SRC]]
 //
 vint16mf2_t test_vreinterpret_v_u16mf2_i16mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u16m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[SRC]]
 //
 vint16m1_t test_vreinterpret_v_u16m1_i16m1(vuint16m1_t src) {
   return __riscv_vreinterpret_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u16m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[SRC]]
 //
 vint16m2_t test_vreinterpret_v_u16m2_i16m2(vuint16m2_t src) {
   return __riscv_vreinterpret_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u16m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[SRC]]
 //
 vint16m4_t test_vreinterpret_v_u16m4_i16m4(vuint16m4_t src) {
   return __riscv_vreinterpret_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u16m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[SRC]]
 //
 vint16m8_t test_vreinterpret_v_u16m8_i16m8(vuint16m8_t src) {
   return __riscv_vreinterpret_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf4_i16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_f16mf4_i16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vint16mf4_t test_vreinterpret_v_f16mf4_i16mf4(vfloat16mf4_t src) {
   return __riscv_vreinterpret_i16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_f16mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vint16mf2_t test_vreinterpret_v_f16mf2_i16mf2(vfloat16mf2_t src) {
   return __riscv_vreinterpret_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_f16m1_i16m1(vfloat16m1_t src) {
   return __riscv_vreinterpret_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_f16m2_i16m2(vfloat16m2_t src) {
   return __riscv_vreinterpret_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_f16m4_i16m4(vfloat16m4_t src) {
   return __riscv_vreinterpret_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_f16m8_i16m8(vfloat16m8_t src) {
   return __riscv_vreinterpret_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf4_u16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_f16mf4_u16mf4
+// CHECK-RV64-SAME: (<vscale x 1 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x half> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vuint16mf4_t test_vreinterpret_v_f16mf4_u16mf4(vfloat16mf4_t src) {
   return __riscv_vreinterpret_u16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_f16mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 2 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x half> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vuint16mf2_t test_vreinterpret_v_f16mf2_u16mf2(vfloat16mf2_t src) {
   return __riscv_vreinterpret_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_f16m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x half> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_f16m1_u16m1(vfloat16m1_t src) {
   return __riscv_vreinterpret_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_f16m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 8 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x half> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_f16m2_u16m2(vfloat16m2_t src) {
   return __riscv_vreinterpret_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_f16m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 16 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x half> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_f16m4_u16m4(vfloat16m4_t src) {
   return __riscv_vreinterpret_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f16m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_f16m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 32 x half> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x half> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_f16m8_u16m8(vfloat16m8_t src) {
   return __riscv_vreinterpret_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_f32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vreinterpret_v_i32mf2_f32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 1 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 1 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]
 //
 vfloat32mf2_t test_vreinterpret_v_i32mf2_f32mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_f32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_f32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_i32m1_f32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 2 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 //
 vfloat32m1_t test_vreinterpret_v_i32m1_f32m1(vint32m1_t src) {
   return __riscv_vreinterpret_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_f32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_i32m2_f32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 4 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 //
 vfloat32m2_t test_vreinterpret_v_i32m2_f32m2(vint32m2_t src) {
   return __riscv_vreinterpret_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_f32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_i32m4_f32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 8 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 //
 vfloat32m4_t test_vreinterpret_v_i32m4_f32m4(vint32m4_t src) {
   return __riscv_vreinterpret_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_f32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_i32m8_f32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 16 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 //
 vfloat32m8_t test_vreinterpret_v_i32m8_f32m8(vint32m8_t src) {
   return __riscv_vreinterpret_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_f32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vreinterpret_v_u32mf2_f32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 1 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 1 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x float> [[TMP0]]
 //
 vfloat32mf2_t test_vreinterpret_v_u32mf2_f32mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_f32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_f32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vreinterpret_v_u32m1_f32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 2 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 2 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x float> [[TMP0]]
 //
 vfloat32m1_t test_vreinterpret_v_u32m1_f32m1(vuint32m1_t src) {
   return __riscv_vreinterpret_f32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_f32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vreinterpret_v_u32m2_f32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 4 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 4 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x float> [[TMP0]]
 //
 vfloat32m2_t test_vreinterpret_v_u32m2_f32m2(vuint32m2_t src) {
   return __riscv_vreinterpret_f32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_f32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vreinterpret_v_u32m4_f32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 8 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 8 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x float> [[TMP0]]
 //
 vfloat32m4_t test_vreinterpret_v_u32m4_f32m4(vuint32m4_t src) {
   return __riscv_vreinterpret_f32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_f32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vreinterpret_v_u32m8_f32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 16 x float>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 16 x float>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x float> [[TMP0]]
 //
 vfloat32m8_t test_vreinterpret_v_u32m8_f32m8(vuint32m8_t src) {
   return __riscv_vreinterpret_f32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i32mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC]]
 //
 vuint32mf2_t test_vreinterpret_v_i32mf2_u32mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i32m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 //
 vuint32m1_t test_vreinterpret_v_i32m1_u32m1(vint32m1_t src) {
   return __riscv_vreinterpret_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i32m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 //
 vuint32m2_t test_vreinterpret_v_i32m2_u32m2(vint32m2_t src) {
   return __riscv_vreinterpret_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i32m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 //
 vuint32m4_t test_vreinterpret_v_i32m4_u32m4(vint32m4_t src) {
   return __riscv_vreinterpret_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i32m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 //
 vuint32m8_t test_vreinterpret_v_i32m8_u32m8(vint32m8_t src) {
   return __riscv_vreinterpret_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u32mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[SRC]]
 //
 vint32mf2_t test_vreinterpret_v_u32mf2_i32mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u32m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[SRC]]
 //
 vint32m1_t test_vreinterpret_v_u32m1_i32m1(vuint32m1_t src) {
   return __riscv_vreinterpret_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u32m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[SRC]]
 //
 vint32m2_t test_vreinterpret_v_u32m2_i32m2(vuint32m2_t src) {
   return __riscv_vreinterpret_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u32m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[SRC]]
 //
 vint32m4_t test_vreinterpret_v_u32m4_i32m4(vuint32m4_t src) {
   return __riscv_vreinterpret_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u32m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[SRC]]
 //
 vint32m8_t test_vreinterpret_v_u32m8_i32m8(vuint32m8_t src) {
   return __riscv_vreinterpret_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_f32mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vint32mf2_t test_vreinterpret_v_f32mf2_i32mf2(vfloat32mf2_t src) {
   return __riscv_vreinterpret_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_f32m1_i32m1(vfloat32m1_t src) {
   return __riscv_vreinterpret_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_f32m2_i32m2(vfloat32m2_t src) {
   return __riscv_vreinterpret_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_f32m4_i32m4(vfloat32m4_t src) {
   return __riscv_vreinterpret_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_f32m8_i32m8(vfloat32m8_t src) {
   return __riscv_vreinterpret_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_f32mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 1 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x float> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vuint32mf2_t test_vreinterpret_v_f32mf2_u32mf2(vfloat32mf2_t src) {
   return __riscv_vreinterpret_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_f32m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x float> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_f32m1_u32m1(vfloat32m1_t src) {
   return __riscv_vreinterpret_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_f32m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 4 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x float> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_f32m2_u32m2(vfloat32m2_t src) {
   return __riscv_vreinterpret_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_f32m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 8 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x float> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_f32m4_u32m4(vfloat32m4_t src) {
   return __riscv_vreinterpret_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f32m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_f32m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 16 x float> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x float> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_f32m8_u32m8(vfloat32m8_t src) {
   return __riscv_vreinterpret_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_f64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_i64m1_f64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 1 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 //
 vfloat64m1_t test_vreinterpret_v_i64m1_f64m1(vint64m1_t src) {
   return __riscv_vreinterpret_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_f64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_i64m2_f64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 2 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 //
 vfloat64m2_t test_vreinterpret_v_i64m2_f64m2(vint64m2_t src) {
   return __riscv_vreinterpret_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_f64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_i64m4_f64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 4 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 //
 vfloat64m4_t test_vreinterpret_v_i64m4_f64m4(vint64m4_t src) {
   return __riscv_vreinterpret_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_f64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_i64m8_f64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 8 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 //
 vfloat64m8_t test_vreinterpret_v_i64m8_f64m8(vint64m8_t src) {
   return __riscv_vreinterpret_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_f64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vreinterpret_v_u64m1_f64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 1 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 1 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x double> [[TMP0]]
 //
 vfloat64m1_t test_vreinterpret_v_u64m1_f64m1(vuint64m1_t src) {
   return __riscv_vreinterpret_f64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_f64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vreinterpret_v_u64m2_f64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 2 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 2 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x double> [[TMP0]]
 //
 vfloat64m2_t test_vreinterpret_v_u64m2_f64m2(vuint64m2_t src) {
   return __riscv_vreinterpret_f64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_f64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vreinterpret_v_u64m4_f64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 4 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 4 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x double> [[TMP0]]
 //
 vfloat64m4_t test_vreinterpret_v_u64m4_f64m4(vuint64m4_t src) {
   return __riscv_vreinterpret_f64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_f64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vreinterpret_v_u64m8_f64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 8 x double>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 8 x double>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x double> [[TMP0]]
 //
 vfloat64m8_t test_vreinterpret_v_u64m8_f64m8(vuint64m8_t src) {
   return __riscv_vreinterpret_f64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i64m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 //
 vuint64m1_t test_vreinterpret_v_i64m1_u64m1(vint64m1_t src) {
   return __riscv_vreinterpret_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i64m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 //
 vuint64m2_t test_vreinterpret_v_i64m2_u64m2(vint64m2_t src) {
   return __riscv_vreinterpret_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i64m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 //
 vuint64m4_t test_vreinterpret_v_i64m4_u64m4(vint64m4_t src) {
   return __riscv_vreinterpret_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i64m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 //
 vuint64m8_t test_vreinterpret_v_i64m8_u64m8(vint64m8_t src) {
   return __riscv_vreinterpret_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u64m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[SRC]]
 //
 vint64m1_t test_vreinterpret_v_u64m1_i64m1(vuint64m1_t src) {
   return __riscv_vreinterpret_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u64m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[SRC]]
 //
 vint64m2_t test_vreinterpret_v_u64m2_i64m2(vuint64m2_t src) {
   return __riscv_vreinterpret_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u64m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[SRC]]
 //
 vint64m4_t test_vreinterpret_v_u64m4_i64m4(vuint64m4_t src) {
   return __riscv_vreinterpret_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u64m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC:%.*]]
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[SRC]]
 //
 vint64m8_t test_vreinterpret_v_u64m8_i64m8(vuint64m8_t src) {
   return __riscv_vreinterpret_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_f64m1_i64m1(vfloat64m1_t src) {
   return __riscv_vreinterpret_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_f64m2_i64m2(vfloat64m2_t src) {
   return __riscv_vreinterpret_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_f64m4_i64m4(vfloat64m4_t src) {
   return __riscv_vreinterpret_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_f64m8_i64m8(vfloat64m8_t src) {
   return __riscv_vreinterpret_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_f64m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x double> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_f64m1_u64m1(vfloat64m1_t src) {
   return __riscv_vreinterpret_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_f64m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 2 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x double> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_f64m2_u64m2(vfloat64m2_t src) {
   return __riscv_vreinterpret_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_f64m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 4 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x double> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_f64m4_u64m4(vfloat64m4_t src) {
   return __riscv_vreinterpret_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_f64m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_f64m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 8 x double> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x double> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_f64m8_u64m8(vfloat64m8_t src) {
   return __riscv_vreinterpret_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf4_i16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_i8mf4_i16mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vint16mf4_t test_vreinterpret_v_i8mf4_i16mf4(vint8mf4_t src) {
   return __riscv_vreinterpret_i16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i8mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vint16mf2_t test_vreinterpret_v_i8mf2_i16mf2(vint8mf2_t src) {
   return __riscv_vreinterpret_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i8m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_i8m1_i16m1(vint8m1_t src) {
   return __riscv_vreinterpret_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i8m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_i8m2_i16m2(vint8m2_t src) {
   return __riscv_vreinterpret_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i8m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_i8m4_i16m4(vint8m4_t src) {
   return __riscv_vreinterpret_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i8m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_i8m8_i16m8(vint8m8_t src) {
   return __riscv_vreinterpret_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf4_u16mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i16> @test_vreinterpret_v_u8mf4_u16mf4
+// CHECK-RV64-SAME: (<vscale x 2 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC:%.*]] to <vscale x 1 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i8> [[SRC]] to <vscale x 1 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i16> [[TMP0]]
 //
 vuint16mf4_t test_vreinterpret_v_u8mf4_u16mf4(vuint8mf4_t src) {
   return __riscv_vreinterpret_u16mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u8mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vuint16mf2_t test_vreinterpret_v_u8mf2_u16mf2(vuint8mf2_t src) {
   return __riscv_vreinterpret_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u8m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_u8m1_u16m1(vuint8m1_t src) {
   return __riscv_vreinterpret_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u8m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_u8m2_u16m2(vuint8m2_t src) {
   return __riscv_vreinterpret_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u8m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_u8m4_u16m4(vuint8m4_t src) {
   return __riscv_vreinterpret_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u8m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_u8m8_u16m8(vuint8m8_t src) {
   return __riscv_vreinterpret_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i8mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vint32mf2_t test_vreinterpret_v_i8mf2_i32mf2(vint8mf2_t src) {
   return __riscv_vreinterpret_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i8m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_i8m1_i32m1(vint8m1_t src) {
   return __riscv_vreinterpret_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i8m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_i8m2_i32m2(vint8m2_t src) {
   return __riscv_vreinterpret_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i8m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_i8m4_i32m4(vint8m4_t src) {
   return __riscv_vreinterpret_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i8m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_i8m8_i32m8(vint8m8_t src) {
   return __riscv_vreinterpret_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u8mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 4 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i8> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vuint32mf2_t test_vreinterpret_v_u8mf2_u32mf2(vuint8mf2_t src) {
   return __riscv_vreinterpret_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u8m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_u8m1_u32m1(vuint8m1_t src) {
   return __riscv_vreinterpret_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u8m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_u8m2_u32m2(vuint8m2_t src) {
   return __riscv_vreinterpret_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u8m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_u8m4_u32m4(vuint8m4_t src) {
   return __riscv_vreinterpret_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u8m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_u8m8_u32m8(vuint8m8_t src) {
   return __riscv_vreinterpret_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i8m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_i8m1_i64m1(vint8m1_t src) {
   return __riscv_vreinterpret_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i8m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_i8m2_i64m2(vint8m2_t src) {
   return __riscv_vreinterpret_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i8m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_i8m4_i64m4(vint8m4_t src) {
   return __riscv_vreinterpret_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i8m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i8m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_i8m8_i64m8(vint8m8_t src) {
   return __riscv_vreinterpret_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u8m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i8> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_u8m1_u64m1(vuint8m1_t src) {
   return __riscv_vreinterpret_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u8m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 16 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i8> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_u8m2_u64m2(vuint8m2_t src) {
   return __riscv_vreinterpret_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u8m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 32 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i8> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_u8m4_u64m4(vuint8m4_t src) {
   return __riscv_vreinterpret_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u8m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u8m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 64 x i8> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 64 x i8> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_u8m8_u64m8(vuint8m8_t src) {
   return __riscv_vreinterpret_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf4_i8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_i16mf4_i8mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 2 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 2 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
 //
 vint8mf4_t test_vreinterpret_v_i16mf4_i8mf4(vint16mf4_t src) {
   return __riscv_vreinterpret_i8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_i8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i16mf2_i8mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vint8mf2_t test_vreinterpret_v_i16mf2_i8mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_i8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i16m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vint8m1_t test_vreinterpret_v_i16m1_i8m1(vint16m1_t src) {
   return __riscv_vreinterpret_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i16m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vint8m2_t test_vreinterpret_v_i16m2_i8m2(vint16m2_t src) {
   return __riscv_vreinterpret_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i16m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vint8m4_t test_vreinterpret_v_i16m4_i8m4(vint16m4_t src) {
   return __riscv_vreinterpret_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i16m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vint8m8_t test_vreinterpret_v_i16m8_i8m8(vint16m8_t src) {
   return __riscv_vreinterpret_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf4_u8mf4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vreinterpret_v_u16mf4_u8mf4
+// CHECK-RV64-SAME: (<vscale x 1 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC:%.*]] to <vscale x 2 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i16> [[SRC]] to <vscale x 2 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i8> [[TMP0]]
 //
 vuint8mf4_t test_vreinterpret_v_u16mf4_u8mf4(vuint16mf4_t src) {
   return __riscv_vreinterpret_u8mf4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_u8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u16mf2_u8mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vuint8mf2_t test_vreinterpret_v_u16mf2_u8mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_u8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u16m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vuint8m1_t test_vreinterpret_v_u16m1_u8m1(vuint16m1_t src) {
   return __riscv_vreinterpret_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u16m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vuint8m2_t test_vreinterpret_v_u16m2_u8m2(vuint16m2_t src) {
   return __riscv_vreinterpret_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u16m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vuint8m4_t test_vreinterpret_v_u16m4_u8m4(vuint16m4_t src) {
   return __riscv_vreinterpret_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u16m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vuint8m8_t test_vreinterpret_v_u16m8_u8m8(vuint16m8_t src) {
   return __riscv_vreinterpret_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16mf2_i32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_i16mf2_i32mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vint32mf2_t test_vreinterpret_v_i16mf2_i32mf2(vint16mf2_t src) {
   return __riscv_vreinterpret_i32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i16m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_i16m1_i32m1(vint16m1_t src) {
   return __riscv_vreinterpret_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i16m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_i16m2_i32m2(vint16m2_t src) {
   return __riscv_vreinterpret_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i16m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_i16m4_i32m4(vint16m4_t src) {
   return __riscv_vreinterpret_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i16m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_i16m8_i32m8(vint16m8_t src) {
   return __riscv_vreinterpret_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16mf2_u32mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vreinterpret_v_u16mf2_u32mf2
+// CHECK-RV64-SAME: (<vscale x 2 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC:%.*]] to <vscale x 1 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i16> [[SRC]] to <vscale x 1 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i32> [[TMP0]]
 //
 vuint32mf2_t test_vreinterpret_v_u16mf2_u32mf2(vuint16mf2_t src) {
   return __riscv_vreinterpret_u32mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u16m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_u16m1_u32m1(vuint16m1_t src) {
   return __riscv_vreinterpret_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u16m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_u16m2_u32m2(vuint16m2_t src) {
   return __riscv_vreinterpret_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u16m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_u16m4_u32m4(vuint16m4_t src) {
   return __riscv_vreinterpret_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u16m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_u16m8_u32m8(vuint16m8_t src) {
   return __riscv_vreinterpret_u32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i16m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_i16m1_i64m1(vint16m1_t src) {
   return __riscv_vreinterpret_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i16m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_i16m2_i64m2(vint16m2_t src) {
   return __riscv_vreinterpret_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i16m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_i16m4_i64m4(vint16m4_t src) {
   return __riscv_vreinterpret_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i16m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i16m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_i16m8_i64m8(vint16m8_t src) {
   return __riscv_vreinterpret_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u16m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i16> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_u16m1_u64m1(vuint16m1_t src) {
   return __riscv_vreinterpret_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u16m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 8 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i16> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_u16m2_u64m2(vuint16m2_t src) {
   return __riscv_vreinterpret_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u16m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 16 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i16> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_u16m4_u64m4(vuint16m4_t src) {
   return __riscv_vreinterpret_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u16m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u16m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 32 x i16> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 32 x i16> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_u16m8_u64m8(vuint16m8_t src) {
   return __riscv_vreinterpret_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_i8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_i32mf2_i8mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vint8mf2_t test_vreinterpret_v_i32mf2_i8mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_i8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i32m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vint8m1_t test_vreinterpret_v_i32m1_i8m1(vint32m1_t src) {
   return __riscv_vreinterpret_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i32m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vint8m2_t test_vreinterpret_v_i32m2_i8m2(vint32m2_t src) {
   return __riscv_vreinterpret_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i32m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vint8m4_t test_vreinterpret_v_i32m4_i8m4(vint32m4_t src) {
   return __riscv_vreinterpret_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i32m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vint8m8_t test_vreinterpret_v_i32m8_i8m8(vint32m8_t src) {
   return __riscv_vreinterpret_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_u8mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vreinterpret_v_u32mf2_u8mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 4 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 4 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i8> [[TMP0]]
 //
 vuint8mf2_t test_vreinterpret_v_u32mf2_u8mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_u8mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u32m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vuint8m1_t test_vreinterpret_v_u32m1_u8m1(vuint32m1_t src) {
   return __riscv_vreinterpret_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u32m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vuint8m2_t test_vreinterpret_v_u32m2_u8m2(vuint32m2_t src) {
   return __riscv_vreinterpret_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u32m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vuint8m4_t test_vreinterpret_v_u32m4_u8m4(vuint32m4_t src) {
   return __riscv_vreinterpret_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u32m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vuint8m8_t test_vreinterpret_v_u32m8_u8m8(vuint32m8_t src) {
   return __riscv_vreinterpret_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32mf2_i16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_i32mf2_i16mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vint16mf2_t test_vreinterpret_v_i32mf2_i16mf2(vint32mf2_t src) {
   return __riscv_vreinterpret_i16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i32m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_i32m1_i16m1(vint32m1_t src) {
   return __riscv_vreinterpret_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i32m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_i32m2_i16m2(vint32m2_t src) {
   return __riscv_vreinterpret_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i32m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_i32m4_i16m4(vint32m4_t src) {
   return __riscv_vreinterpret_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i32m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_i32m8_i16m8(vint32m8_t src) {
   return __riscv_vreinterpret_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32mf2_u16mf2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i16> @test_vreinterpret_v_u32mf2_u16mf2
+// CHECK-RV64-SAME: (<vscale x 1 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC:%.*]] to <vscale x 2 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i32> [[SRC]] to <vscale x 2 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i16> [[TMP0]]
 //
 vuint16mf2_t test_vreinterpret_v_u32mf2_u16mf2(vuint32mf2_t src) {
   return __riscv_vreinterpret_u16mf2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u32m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_u32m1_u16m1(vuint32m1_t src) {
   return __riscv_vreinterpret_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u32m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_u32m2_u16m2(vuint32m2_t src) {
   return __riscv_vreinterpret_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u32m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_u32m4_u16m4(vuint32m4_t src) {
   return __riscv_vreinterpret_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u32m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_u32m8_u16m8(vuint32m8_t src) {
   return __riscv_vreinterpret_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m1_i64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_i32m1_i64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vint64m1_t test_vreinterpret_v_i32m1_i64m1(vint32m1_t src) {
   return __riscv_vreinterpret_i64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m2_i64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_i32m2_i64m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vint64m2_t test_vreinterpret_v_i32m2_i64m2(vint32m2_t src) {
   return __riscv_vreinterpret_i64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m4_i64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_i32m4_i64m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vint64m4_t test_vreinterpret_v_i32m4_i64m4(vint32m4_t src) {
   return __riscv_vreinterpret_i64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i32m8_i64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_i32m8_i64m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vint64m8_t test_vreinterpret_v_i32m8_i64m8(vint32m8_t src) {
   return __riscv_vreinterpret_i64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m1_u64m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_u32m1_u64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC:%.*]] to <vscale x 1 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i32> [[SRC]] to <vscale x 1 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
 //
 vuint64m1_t test_vreinterpret_v_u32m1_u64m1(vuint32m1_t src) {
   return __riscv_vreinterpret_u64m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m2_u64m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i64> @test_vreinterpret_v_u32m2_u64m2
+// CHECK-RV64-SAME: (<vscale x 4 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC:%.*]] to <vscale x 2 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i32> [[SRC]] to <vscale x 2 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i64> [[TMP0]]
 //
 vuint64m2_t test_vreinterpret_v_u32m2_u64m2(vuint32m2_t src) {
   return __riscv_vreinterpret_u64m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m4_u64m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i64> @test_vreinterpret_v_u32m4_u64m4
+// CHECK-RV64-SAME: (<vscale x 8 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC:%.*]] to <vscale x 4 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i32> [[SRC]] to <vscale x 4 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i64> [[TMP0]]
 //
 vuint64m4_t test_vreinterpret_v_u32m4_u64m4(vuint32m4_t src) {
   return __riscv_vreinterpret_u64m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u32m8_u64m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i64> @test_vreinterpret_v_u32m8_u64m8
+// CHECK-RV64-SAME: (<vscale x 16 x i32> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC:%.*]] to <vscale x 8 x i64>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 16 x i32> [[SRC]] to <vscale x 8 x i64>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i64> [[TMP0]]
 //
 vuint64m8_t test_vreinterpret_v_u32m8_u64m8(vuint32m8_t src) {
   return __riscv_vreinterpret_u64m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_i64m1_i8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vint8m1_t test_vreinterpret_v_i64m1_i8m1(vint64m1_t src) {
   return __riscv_vreinterpret_i8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_i64m2_i8m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vint8m2_t test_vreinterpret_v_i64m2_i8m2(vint64m2_t src) {
   return __riscv_vreinterpret_i8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_i64m4_i8m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vint8m4_t test_vreinterpret_v_i64m4_i8m4(vint64m4_t src) {
   return __riscv_vreinterpret_i8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_i64m8_i8m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vint8m8_t test_vreinterpret_v_i64m8_i8m8(vint64m8_t src) {
   return __riscv_vreinterpret_i8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u8m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_u64m1_u8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 8 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 8 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
 //
 vuint8m1_t test_vreinterpret_v_u64m1_u8m1(vuint64m1_t src) {
   return __riscv_vreinterpret_u8m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u8m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i8> @test_vreinterpret_v_u64m2_u8m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 16 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 16 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i8> [[TMP0]]
 //
 vuint8m2_t test_vreinterpret_v_u64m2_u8m2(vuint64m2_t src) {
   return __riscv_vreinterpret_u8m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u8m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i8> @test_vreinterpret_v_u64m4_u8m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 32 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 32 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i8> [[TMP0]]
 //
 vuint8m4_t test_vreinterpret_v_u64m4_u8m4(vuint64m4_t src) {
   return __riscv_vreinterpret_u8m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u8m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i8> @test_vreinterpret_v_u64m8_u8m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 64 x i8>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 64 x i8>
 // CHECK-RV64-NEXT:    ret <vscale x 64 x i8> [[TMP0]]
 //
 vuint8m8_t test_vreinterpret_v_u64m8_u8m8(vuint64m8_t src) {
   return __riscv_vreinterpret_u8m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_i64m1_i16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vint16m1_t test_vreinterpret_v_i64m1_i16m1(vint64m1_t src) {
   return __riscv_vreinterpret_i16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_i64m2_i16m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vint16m2_t test_vreinterpret_v_i64m2_i16m2(vint64m2_t src) {
   return __riscv_vreinterpret_i16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_i64m4_i16m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vint16m4_t test_vreinterpret_v_i64m4_i16m4(vint64m4_t src) {
   return __riscv_vreinterpret_i16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_i64m8_i16m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vint16m8_t test_vreinterpret_v_i64m8_i16m8(vint64m8_t src) {
   return __riscv_vreinterpret_i16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u16m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_u64m1_u16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 4 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 4 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
 //
 vuint16m1_t test_vreinterpret_v_u64m1_u16m1(vuint64m1_t src) {
   return __riscv_vreinterpret_u16m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u16m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i16> @test_vreinterpret_v_u64m2_u16m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 8 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 8 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i16> [[TMP0]]
 //
 vuint16m2_t test_vreinterpret_v_u64m2_u16m2(vuint64m2_t src) {
   return __riscv_vreinterpret_u16m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u16m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i16> @test_vreinterpret_v_u64m4_u16m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 16 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 16 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i16> [[TMP0]]
 //
 vuint16m4_t test_vreinterpret_v_u64m4_u16m4(vuint64m4_t src) {
   return __riscv_vreinterpret_u16m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u16m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i16> @test_vreinterpret_v_u64m8_u16m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 32 x i16>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 32 x i16>
 // CHECK-RV64-NEXT:    ret <vscale x 32 x i16> [[TMP0]]
 //
 vuint16m8_t test_vreinterpret_v_u64m8_u16m8(vuint64m8_t src) {
   return __riscv_vreinterpret_u16m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m1_i32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_i64m1_i32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vint32m1_t test_vreinterpret_v_i64m1_i32m1(vint64m1_t src) {
   return __riscv_vreinterpret_i32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m2_i32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_i64m2_i32m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vint32m2_t test_vreinterpret_v_i64m2_i32m2(vint64m2_t src) {
   return __riscv_vreinterpret_i32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m4_i32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_i64m4_i32m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vint32m4_t test_vreinterpret_v_i64m4_i32m4(vint64m4_t src) {
   return __riscv_vreinterpret_i32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_i64m8_i32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_i64m8_i32m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vint32m8_t test_vreinterpret_v_i64m8_i32m8(vint64m8_t src) {
   return __riscv_vreinterpret_i32m8(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m1_u32m1(
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_u64m1_u32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC:%.*]] to <vscale x 2 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 1 x i64> [[SRC]] to <vscale x 2 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
 //
 vuint32m1_t test_vreinterpret_v_u64m1_u32m1(vuint64m1_t src) {
   return __riscv_vreinterpret_u32m1(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m2_u32m2(
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vreinterpret_v_u64m2_u32m2
+// CHECK-RV64-SAME: (<vscale x 2 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC:%.*]] to <vscale x 4 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 2 x i64> [[SRC]] to <vscale x 4 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 4 x i32> [[TMP0]]
 //
 vuint32m2_t test_vreinterpret_v_u64m2_u32m2(vuint64m2_t src) {
   return __riscv_vreinterpret_u32m2(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m4_u32m4(
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vreinterpret_v_u64m4_u32m4
+// CHECK-RV64-SAME: (<vscale x 4 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC:%.*]] to <vscale x 8 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 4 x i64> [[SRC]] to <vscale x 8 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 8 x i32> [[TMP0]]
 //
 vuint32m4_t test_vreinterpret_v_u64m4_u32m4(vuint64m4_t src) {
   return __riscv_vreinterpret_u32m4(src);
 }
 
-// CHECK-RV64-LABEL: @test_vreinterpret_v_u64m8_u32m8(
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vreinterpret_v_u64m8_u32m8
+// CHECK-RV64-SAME: (<vscale x 8 x i64> [[SRC:%.*]]) #[[ATTR0]] {
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC:%.*]] to <vscale x 16 x i32>
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = bitcast <vscale x 8 x i64> [[SRC]] to <vscale x 16 x i32>
 // CHECK-RV64-NEXT:    ret <vscale x 16 x i32> [[TMP0]]
 //
 vuint32m8_t test_vreinterpret_v_u64m8_u32m8(vuint64m8_t src) {
   return __riscv_vreinterpret_u32m8(src);
 }
 
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i8m1_b64(vint8m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_i8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b64_i8m1(vbool64_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i8m1_b32(vint8m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_i8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b32_i8m1(vbool32_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i8m1_b16(vint8m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_i8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b16_i8m1(vbool16_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i8m1_b8(vint8m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_i8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b8_i8m1(vbool8_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_i8m1_b4(vint8m1_t src) {
+  return __riscv_vreinterpret_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_i8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b4_i8m1(vbool4_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_i8m1_b2(vint8m1_t src) {
+  return __riscv_vreinterpret_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_i8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b2_i8m1(vbool2_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_i8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vreinterpret.v.nxv64i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
+//
+vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {
+  return __riscv_vreinterpret_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_i8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv64i1(<vscale x 64 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vint8m1_t test_vreinterpret_v_b1_i8m1(vbool1_t src) {
+  return __riscv_vreinterpret_i8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u8m1_b64
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u8m1_b64(vuint8m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b64_u8m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b64_u8m1(vbool64_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u8m1_b32
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u8m1_b32(vuint8m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b32_u8m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b32_u8m1(vbool32_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u8m1_b16
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u8m1_b16(vuint8m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b16_u8m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b16_u8m1(vbool16_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u8m1_b8
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u8m1_b8(vuint8m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b8_u8m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b8_u8m1(vbool8_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u8m1_b4
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_u8m1_b4(vuint8m1_t src) {
+  return __riscv_vreinterpret_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b4_u8m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b4_u8m1(vbool4_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u8m1_b2
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_u8m1_b2(vuint8m1_t src) {
+  return __riscv_vreinterpret_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b2_u8m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b2_u8m1(vbool2_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 64 x i1> @test_vreinterpret_v_u8m1_b1
+// CHECK-RV64-SAME: (<vscale x 8 x i8> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vreinterpret.v.nxv64i1.nxv8i8(<vscale x 8 x i8> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 64 x i1> [[TMP0]]
+//
+vbool1_t test_vreinterpret_v_u8m1_b1(vuint8m1_t src) {
+  return __riscv_vreinterpret_b1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i8> @test_vreinterpret_v_b1_u8m1
+// CHECK-RV64-SAME: (<vscale x 64 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i8> @llvm.riscv.vreinterpret.v.nxv8i8.nxv64i1(<vscale x 64 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i8> [[TMP0]]
+//
+vuint8m1_t test_vreinterpret_v_b1_u8m1(vbool1_t src) {
+  return __riscv_vreinterpret_u8m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i16m1_b64(vint16m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_i16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b64_i16m1(vbool64_t src) {
+  return __riscv_vreinterpret_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i16m1_b32(vint16m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_i16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b32_i16m1(vbool32_t src) {
+  return __riscv_vreinterpret_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i16m1_b16(vint16m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_i16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b16_i16m1(vbool16_t src) {
+  return __riscv_vreinterpret_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i16m1_b8(vint16m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_i16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b8_i16m1(vbool8_t src) {
+  return __riscv_vreinterpret_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_i16m1_b4(vint16m1_t src) {
+  return __riscv_vreinterpret_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_i16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b4_i16m1(vbool4_t src) {
+  return __riscv_vreinterpret_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_i16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_i16m1_b2(vint16m1_t src) {
+  return __riscv_vreinterpret_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_i16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vint16m1_t test_vreinterpret_v_b2_i16m1(vbool2_t src) {
+  return __riscv_vreinterpret_i16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u16m1_b64
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u16m1_b64(vuint16m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b64_u16m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b64_u16m1(vbool64_t src) {
+  return __riscv_vreinterpret_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u16m1_b32
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u16m1_b32(vuint16m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b32_u16m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b32_u16m1(vbool32_t src) {
+  return __riscv_vreinterpret_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u16m1_b16
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u16m1_b16(vuint16m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b16_u16m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b16_u16m1(vbool16_t src) {
+  return __riscv_vreinterpret_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u16m1_b8
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u16m1_b8(vuint16m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b8_u16m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b8_u16m1(vbool8_t src) {
+  return __riscv_vreinterpret_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u16m1_b4
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_u16m1_b4(vuint16m1_t src) {
+  return __riscv_vreinterpret_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b4_u16m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b4_u16m1(vbool4_t src) {
+  return __riscv_vreinterpret_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 32 x i1> @test_vreinterpret_v_u16m1_b2
+// CHECK-RV64-SAME: (<vscale x 4 x i16> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vreinterpret.v.nxv32i1.nxv4i16(<vscale x 4 x i16> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 32 x i1> [[TMP0]]
+//
+vbool2_t test_vreinterpret_v_u16m1_b2(vuint16m1_t src) {
+  return __riscv_vreinterpret_b2(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i16> @test_vreinterpret_v_b2_u16m1
+// CHECK-RV64-SAME: (<vscale x 32 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i16> @llvm.riscv.vreinterpret.v.nxv4i16.nxv32i1(<vscale x 32 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i16> [[TMP0]]
+//
+vuint16m1_t test_vreinterpret_v_b2_u16m1(vbool2_t src) {
+  return __riscv_vreinterpret_u16m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i32m1_b64(vint32m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_i32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b64_i32m1(vbool64_t src) {
+  return __riscv_vreinterpret_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i32m1_b32(vint32m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b32_i32m1(vbool32_t src) {
+  return __riscv_vreinterpret_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i32m1_b16(vint32m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_i32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b16_i32m1(vbool16_t src) {
+  return __riscv_vreinterpret_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i32m1_b8(vint32m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_i32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b8_i32m1(vbool8_t src) {
+  return __riscv_vreinterpret_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_i32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_i32m1_b4(vint32m1_t src) {
+  return __riscv_vreinterpret_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_i32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vint32m1_t test_vreinterpret_v_b4_i32m1(vbool4_t src) {
+  return __riscv_vreinterpret_i32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u32m1_b64
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u32m1_b64(vuint32m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b64_u32m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b64_u32m1(vbool64_t src) {
+  return __riscv_vreinterpret_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u32m1_b32
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u32m1_b32(vuint32m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b32_u32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b32_u32m1(vbool32_t src) {
+  return __riscv_vreinterpret_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u32m1_b16
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u32m1_b16(vuint32m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b16_u32m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b16_u32m1(vbool16_t src) {
+  return __riscv_vreinterpret_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u32m1_b8
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u32m1_b8(vuint32m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b8_u32m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b8_u32m1(vbool8_t src) {
+  return __riscv_vreinterpret_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i1> @test_vreinterpret_v_u32m1_b4
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vreinterpret.v.nxv16i1.nxv2i32(<vscale x 2 x i32> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 16 x i1> [[TMP0]]
+//
+vbool4_t test_vreinterpret_v_u32m1_b4(vuint32m1_t src) {
+  return __riscv_vreinterpret_b4(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vreinterpret_v_b4_u32m1
+// CHECK-RV64-SAME: (<vscale x 16 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vreinterpret.v.nxv2i32.nxv16i1(<vscale x 16 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i32> [[TMP0]]
+//
+vuint32m1_t test_vreinterpret_v_b4_u32m1(vbool4_t src) {
+  return __riscv_vreinterpret_u32m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_i64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_i64m1_b64(vint64m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_i64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b64_i64m1(vbool64_t src) {
+  return __riscv_vreinterpret_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_i64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_i64m1_b32(vint64m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_i64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b32_i64m1(vbool32_t src) {
+  return __riscv_vreinterpret_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_i64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_i64m1_b16(vint64m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_i64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b16_i64m1(vbool16_t src) {
+  return __riscv_vreinterpret_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_i64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_i64m1_b8(vint64m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_i64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vint64m1_t test_vreinterpret_v_b8_i64m1(vbool8_t src) {
+  return __riscv_vreinterpret_i64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i1> @test_vreinterpret_v_u64m1_b64
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vreinterpret.v.nxv1i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i1> [[TMP0]]
+//
+vbool64_t test_vreinterpret_v_u64m1_b64(vuint64m1_t src) {
+  return __riscv_vreinterpret_b64(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b64_u64m1
+// CHECK-RV64-SAME: (<vscale x 1 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv1i1(<vscale x 1 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b64_u64m1(vbool64_t src) {
+  return __riscv_vreinterpret_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i1> @test_vreinterpret_v_u64m1_b32
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vreinterpret.v.nxv2i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 2 x i1> [[TMP0]]
+//
+vbool32_t test_vreinterpret_v_u64m1_b32(vuint64m1_t src) {
+  return __riscv_vreinterpret_b32(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b32_u64m1
+// CHECK-RV64-SAME: (<vscale x 2 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv2i1(<vscale x 2 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b32_u64m1(vbool32_t src) {
+  return __riscv_vreinterpret_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i1> @test_vreinterpret_v_u64m1_b16
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vreinterpret.v.nxv4i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 4 x i1> [[TMP0]]
+//
+vbool16_t test_vreinterpret_v_u64m1_b16(vuint64m1_t src) {
+  return __riscv_vreinterpret_b16(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b16_u64m1
+// CHECK-RV64-SAME: (<vscale x 4 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv4i1(<vscale x 4 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b16_u64m1(vbool16_t src) {
+  return __riscv_vreinterpret_u64m1(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i1> @test_vreinterpret_v_u64m1_b8
+// CHECK-RV64-SAME: (<vscale x 1 x i64> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vreinterpret.v.nxv8i1.nxv1i64(<vscale x 1 x i64> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 8 x i1> [[TMP0]]
+//
+vbool8_t test_vreinterpret_v_u64m1_b8(vuint64m1_t src) {
+  return __riscv_vreinterpret_b8(src);
+}
+
+// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i64> @test_vreinterpret_v_b8_u64m1
+// CHECK-RV64-SAME: (<vscale x 8 x i1> [[SRC:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = call <vscale x 1 x i64> @llvm.riscv.vreinterpret.v.nxv1i64.nxv8i1(<vscale x 8 x i1> [[SRC]])
+// CHECK-RV64-NEXT:    ret <vscale x 1 x i64> [[TMP0]]
+//
+vuint64m1_t test_vreinterpret_v_b8_u64m1(vbool8_t src) {
+  return __riscv_vreinterpret_u64m1(src);
+}
+
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -1415,6 +1415,11 @@
   defm vfncvt_f_f_w : RISCVConversion;
   defm vfncvt_rod_f_f_w : RISCVConversion;
 
+  def int_riscv_vreinterpret_v
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                                [llvm_anyvector_ty],
+                                [IntrNoMem]>, RISCVVIntrinsic;
+
   // Output: (vector)
   // Input: (passthru, mask type input, vl)
   def int_riscv_viota
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1378,6 +1378,15 @@
       // By default we do not custom select any intrinsic.
     default:
       break;
+    case Intrinsic::riscv_vreinterpret_v: {
+      // The reinterpret intrinsic between m1 vector integer types and vector
+      // boolean type is just for going across the type-safe boundary of RVV
+      // intrinsics. It is essentially a nop. Directly replacing the node with
+      // the input operand.
+      ReplaceUses(SDValue(Node, 0), Node->getOperand(1));
+      CurDAG->RemoveDeadNode(Node);
+      return;
+    }
     case Intrinsic::riscv_vmsgeu:
     case Intrinsic::riscv_vmsge: {
       SDValue Src1 = Node->getOperand(1);