diff --git a/llvm/include/llvm/ADT/SparseSet.h b/llvm/include/llvm/ADT/SparseSet.h
--- a/llvm/include/llvm/ADT/SparseSet.h
+++ b/llvm/include/llvm/ADT/SparseSet.h
@@ -203,6 +203,7 @@
   ///
   iterator findIndex(unsigned Idx) {
     assert(Idx < Universe && "Key out of range");
+    assert(Sparse != nullptr && "Invalid sparse type");
     const unsigned Stride = std::numeric_limits<SparseT>::max() + 1u;
     for (unsigned i = Sparse[Idx], e = size(); i < e; i += Stride) {
       const unsigned FoundIdx = ValIndexOf(Dense[i]);
diff --git a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
--- a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
+++ b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
@@ -100,7 +100,7 @@
 
     auto P = std::make_shared<PoolEntry>(*this, std::move(ValueKey));
     EntrySet.insert(P.get());
-    return PoolRef(std::move(P), &P->getValue());
+    return PoolRef(P, &P->getValue());
   }
 };
 
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -1273,6 +1273,7 @@
       F.needsUnwindTableEntry())
     return CFISection::EH;
 
+  assert(MMI != nullptr && "Invalid machine module info");
   if (MMI->hasDebugInfo() || TM.Options.ForceDwarfFrameSection)
     return CFISection::Debug;
 
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
--- a/llvm/lib/CodeGen/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -724,6 +724,8 @@
 
 bool ScheduleDAGTopologicalSort::IsReachable(const SUnit *SU,
                                              const SUnit *TargetSU) {
+  assert(TargetSU != nullptr && "Invalid target SUnit");
+  assert(SU != nullptr && "Invalid SUnit");
   FixOrder();
   // If insertion of the edge SU->TargetSU would create a cycle
   // then there is a path from TargetSU to SU.
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -571,6 +571,7 @@
 /// pointers as MVT::iPTR.  If HandleUnknown is true, unknown types are returned
 /// as Other, otherwise they are invalid.
 MVT MVT::getVT(Type *Ty, bool HandleUnknown){
+  assert(Ty != nullptr && "Invalid type");
   switch (Ty->getTypeID()) {
   default:
     if (HandleUnknown) return MVT(MVT::Other);
diff --git a/llvm/lib/IR/Mangler.cpp b/llvm/lib/IR/Mangler.cpp
--- a/llvm/lib/IR/Mangler.cpp
+++ b/llvm/lib/IR/Mangler.cpp
@@ -119,6 +119,7 @@
 void Mangler::getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV,
                                 bool CannotUsePrivateLabel) const {
   ManglerPrefixTy PrefixTy = Default;
+  assert(GV != nullptr && "Invalid Global Value");
   if (GV->hasPrivateLinkage()) {
     if (CannotUsePrivateLabel)
       PrefixTy = LinkerPrivate;
diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -316,8 +316,11 @@
       return resolveRecordTypes(RecTy1, RecTy2);
   }
 
+  assert(T1 != nullptr && "Invalid record type");
   if (T1->typeIsConvertibleTo(T2))
     return T2;
+
+  assert(T2 != nullptr && "Invalid record type");
   if (T2->typeIsConvertibleTo(T1))
     return T1;
 
diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -3604,6 +3604,7 @@
   bool HasAVX512 = STI.hasAVX512();
   bool HasVLX = STI.hasVLX();
 
+  assert(RC != nullptr && "Invalid target register class");
   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
   default:
     llvm_unreachable("Unknown spill size");
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -3958,6 +3958,7 @@
     }
   }
 
+  assert(SrcGIEquivOrNull != nullptr && "Invalid SrcGIEquivOrNull value");
   // No check required. We already did it by swapping the opcode.
   if (!SrcGIEquivOrNull->isValueUnset("IfSignExtend") &&
       Predicate.isSignExtLoad())
diff --git a/patch.diff b/patch.diff
new file mode 100644
--- /dev/null
+++ b/patch.diff
@@ -0,0 +1,116 @@
+diff --git a/llvm/include/llvm/ADT/SparseSet.h b/llvm/include/llvm/ADT/SparseSet.h
+--- a/llvm/include/llvm/ADT/SparseSet.h
++++ b/llvm/include/llvm/ADT/SparseSet.h
+@@ -203,6 +203,7 @@
+   ///
+   iterator findIndex(unsigned Idx) {
+     assert(Idx < Universe && "Key out of range");
++    assert(Sparse != nullptr && "Invalid sparse type");
+     const unsigned Stride = std::numeric_limits<SparseT>::max() + 1u;
+     for (unsigned i = Sparse[Idx], e = size(); i < e; i += Stride) {
+       const unsigned FoundIdx = ValIndexOf(Dense[i]);
+diff --git a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
+--- a/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
++++ b/llvm/include/llvm/CodeGen/PBQP/CostAllocator.h
+@@ -100,7 +100,7 @@
+ 
+     auto P = std::make_shared<PoolEntry>(*this, std::move(ValueKey));
+     EntrySet.insert(P.get());
+-    return PoolRef(std::move(P), &P->getValue());
++    return PoolRef(P, &P->getValue());
+   }
+ };
+ 
+diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+--- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
++++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+@@ -1135,6 +1135,7 @@
+ }
+ 
+ inline unsigned SDValue::getOpcode() const {
++  assert(Node != nullptr && "Invalid Node");
+   return Node->getOpcode();
+ }
+ 
+diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
++++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+@@ -1273,6 +1273,7 @@
+       F.needsUnwindTableEntry())
+     return CFISection::EH;
+ 
++  assert(MMI != nullptr && "Invalid machine module info");
+   if (MMI->hasDebugInfo() || TM.Options.ForceDwarfFrameSection)
+     return CFISection::Debug;
+ 
+diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
+--- a/llvm/lib/CodeGen/ScheduleDAG.cpp
++++ b/llvm/lib/CodeGen/ScheduleDAG.cpp
+@@ -724,6 +724,8 @@
+ 
+ bool ScheduleDAGTopologicalSort::IsReachable(const SUnit *SU,
+                                              const SUnit *TargetSU) {
++  assert(TargetSU != nullptr && "Invalid target SUnit");
++  assert(SU != nullptr && "Invalid SUnit");
+   FixOrder();
+   // If insertion of the edge SU->TargetSU would create a cycle
+   // then there is a path from TargetSU to SU.
+diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
+--- a/llvm/lib/CodeGen/ValueTypes.cpp
++++ b/llvm/lib/CodeGen/ValueTypes.cpp
+@@ -571,6 +571,7 @@
+ /// pointers as MVT::iPTR.  If HandleUnknown is true, unknown types are returned
+ /// as Other, otherwise they are invalid.
+ MVT MVT::getVT(Type *Ty, bool HandleUnknown){
++  assert(Ty != nullptr && "Invalid type");
+   switch (Ty->getTypeID()) {
+   default:
+     if (HandleUnknown) return MVT(MVT::Other);
+diff --git a/llvm/lib/IR/Mangler.cpp b/llvm/lib/IR/Mangler.cpp
+--- a/llvm/lib/IR/Mangler.cpp
++++ b/llvm/lib/IR/Mangler.cpp
+@@ -119,6 +119,7 @@
+ void Mangler::getNameWithPrefix(raw_ostream &OS, const GlobalValue *GV,
+                                 bool CannotUsePrivateLabel) const {
+   ManglerPrefixTy PrefixTy = Default;
++  assert(GV != nullptr && "Invalid Global Value");
+   if (GV->hasPrivateLinkage()) {
+     if (CannotUsePrivateLabel)
+       PrefixTy = LinkerPrivate;
+diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
+--- a/llvm/lib/TableGen/Record.cpp
++++ b/llvm/lib/TableGen/Record.cpp
+@@ -318,8 +318,11 @@
+       return resolveRecordTypes(RecTy1, RecTy2);
+   }
+ 
++  assert(T1 != nullptr && "Invalid record type");
+   if (T1->typeIsConvertibleTo(T2))
+     return T2;
++
++  assert(T2 != nullptr && "Invalid record type");
+   if (T2->typeIsConvertibleTo(T1))
+     return T1;
+ 
+diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
+--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
++++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
+@@ -3603,6 +3603,7 @@
+   bool HasAVX512 = STI.hasAVX512();
+   bool HasVLX = STI.hasVLX();
+ 
++  assert(RC != nullptr && "Invalid target register class");
+   switch (STI.getRegisterInfo()->getSpillSize(*RC)) {
+   default:
+     llvm_unreachable("Unknown spill size");
+diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
+--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
++++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
+@@ -3958,6 +3958,7 @@
+     }
+   }
+ 
++  assert(SrcGIEquivOrNull != nullptr && "Invalid SrcGIEquivOrNull value");
+   // No check required. We already did it by swapping the opcode.
+   if (!SrcGIEquivOrNull->isValueUnset("IfSignExtend") &&
+       Predicate.isSignExtLoad())