diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -173,6 +173,7 @@ // MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" +// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh" // MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b" diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -239,6 +239,7 @@ def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; @@ -250,6 +251,7 @@ } let Latency = 2 in { +def : WriteRes; def : WriteRes; def : WriteRes; } @@ -265,6 +267,22 @@ def : WriteRes; } +// Half precision. +let Latency = 5 in { +def : WriteRes; +def : WriteRes; +def : WriteRes; +} +let Latency = 3 in { +def : WriteRes; +def : WriteRes; +} + +let Latency = 14, ResourceCycles = [1, 13] in { +def : WriteRes; +def : WriteRes; +} + // Single precision. let Latency = 5 in { def : WriteRes; @@ -299,21 +317,33 @@ // Conversions let Latency = 3 in { +def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; +def : WriteRes; +def : WriteRes; def : WriteRes; def : WriteRes; def : WriteRes; @@ -690,36 +720,55 @@ def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; +def : ReadAdvance; def : ReadAdvance; def : ReadAdvance; @@ -911,5 +960,4 @@ defm : UnsupportedSchedZbkb; defm : UnsupportedSchedZbkx; defm : UnsupportedSchedZfa; -defm : UnsupportedSchedZfh; }