diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -3702,11 +3702,21 @@
     setOrigin(&I, getOrigin(&I, 0));
   }
 
+  void handleIsFpClass(IntrinsicInst &I) {
+    IRBuilder<> IRB(&I);
+    Value *Shadow = getShadow(&I, 0);
+    setShadow(&I, IRB.CreateICmpNE(Shadow, getCleanShadow(Shadow)));
+    setOrigin(&I, getOrigin(&I, 0));
+  }
+
   void visitIntrinsicInst(IntrinsicInst &I) {
     switch (I.getIntrinsicID()) {
     case Intrinsic::abs:
       handleAbsIntrinsic(I);
       break;
+    case Intrinsic::is_fpclass:
+      handleIsFpClass(I);
+      break;
     case Intrinsic::lifetime_start:
       handleLifetimeStart(I);
       break;
diff --git a/llvm/test/Instrumentation/MemorySanitizer/create-class-from-logic-fcmp.ll b/llvm/test/Instrumentation/MemorySanitizer/create-class-from-logic-fcmp.ll
deleted file mode 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/create-class-from-logic-fcmp.ll
+++ /dev/null
@@ -1,6868 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=instcombine < %s | FileCheck %s
-; RUN: opt -S -passes=msan < %s | FileCheck %s --check-prefixes=MSAN
-; RUN: opt -S -passes='module(instcombine),msan' < %s | FileCheck %s --check-prefixes=IC_MSAN
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
-
-; Test and/or of fcmps that could be folded to llvm.is.fpclass
-
-; --------------------------------------------------------------------
-; Base pattern, !isfinite(x) || x == 0.0
-; --------------------------------------------------------------------
-
-; Base pattern !isfinite(x) || x == 0.0
-define i1 @not_isfinite_or_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0:![0-9]+]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Base pattern x == 0.0 || !isfinite(x)
-define i1 @not_isfinite_or_zero_f16_commute_or(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_commute_or(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_commute_or(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP2]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[CMPZERO]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_commute_or(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpinf, %cmpzero
-  ret i1 %class
-}
-
-; Base pattern !isfinite(x) || x == -0.0
-define i1 @not_isfinite_or_zero_f16_negzero(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_negzero(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_negzero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH8000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_negzero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, -0.0
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @not_isfinite_or_fabs_oeq_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_fabs_oeq_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_fabs_oeq_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_fabs_oeq_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %fabs, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Base pattern !isfinite(x) || x == 0.0
-define <2 x i1> @not_isfinite_or_zero_v2f16(<2 x half> %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_v2f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_v2f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP2:%.*]] = trunc <2 x i16> [[_MSPROP]] to <2 x i1>
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP3:%.*]] = trunc <2 x i16> [[_MSPROP1]] to <2 x i1>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; MSAN-NEXT:    [[TMP4:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP5:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP6:%.*]] = and <2 x i1> [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and <2 x i1> [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and <2 x i1> [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or <2 x i1> [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store <2 x i1> [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
-  %class = or <2 x i1> %cmpzero, %cmpinf
-  ret <2 x i1> %class
-}
-
-; Base pattern !isfinite(x) || x == <0.0, -0.0>
-define <2 x i1> @not_isfinite_or_zero_v2f16_pos0_neg0_vec(<2 x half> %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
-; CHECK-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
-; MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP2:%.*]] = trunc <2 x i16> [[_MSPROP]] to <2 x i1>
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP3:%.*]] = trunc <2 x i16> [[_MSPROP1]] to <2 x i1>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], <half 0xH0000, half 0xH8000>
-; MSAN-NEXT:    [[TMP4:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP5:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP6:%.*]] = and <2 x i1> [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and <2 x i1> [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and <2 x i1> [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or <2 x i1> [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store <2 x i1> [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp oeq <2 x half> %x, <half 0.0, half -0.0>
-  %class = or <2 x i1> %cmpzero, %cmpinf
-  ret <2 x i1> %class
-}
-
-; Base pattern x == 0.0 || !isfinite(x)
-define <2 x i1> @not_isfinite_or_zero_v2f16_commute_or(<2 x half> %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_v2f16_commute_or(
-; CHECK-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_v2f16_commute_or(
-; MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP2:%.*]] = trunc <2 x i16> [[_MSPROP]] to <2 x i1>
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP3:%.*]] = trunc <2 x i16> [[_MSPROP1]] to <2 x i1>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; MSAN-NEXT:    [[TMP4:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP5:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP6:%.*]] = and <2 x i1> [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and <2 x i1> [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and <2 x i1> [[TMP2]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or <2 x i1> [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or <2 x i1> [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPINF]], [[CMPZERO]]
-; MSAN-NEXT:    store <2 x i1> [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16_commute_or(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
-  %class = or <2 x i1> %cmpinf, %cmpzero
-  ret <2 x i1> %class
-}
-
-; Positive test
-define i1 @oeq_isinf_or_oeq_zero(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_isinf_or_oeq_zero(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_isinf_or_oeq_zero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_isinf_or_oeq_zero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Missing fabs for infinity check
-define i1 @ueq_inf_or_oeq_zero(half %x) sanitize_memory {
-; CHECK-LABEL: @ueq_inf_or_oeq_zero(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_inf_or_oeq_zero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_inf_or_oeq_zero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Extra fabs.
-define i1 @oeq_isinf_or_fabs_oeq_zero(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_isinf_or_fabs_oeq_zero(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_isinf_or_fabs_oeq_zero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_isinf_or_fabs_oeq_zero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 612)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %fabs, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Positive test
-define i1 @ueq_0_or_oeq_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @ueq_0_or_oeq_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_0_or_oeq_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_0_or_oeq_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 611)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH0000
-  %cmpzero = fcmp oeq half %x, 0xH7C00
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Positive test
-define i1 @not_isfinite_or_zero_f16_not_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_not_inf(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_not_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C01
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_not_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C01
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Positive test
-define i1 @ueq_inf_or_ueq_zero(half %x) sanitize_memory {
-; CHECK-LABEL: @ueq_inf_or_ueq_zero(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_inf_or_ueq_zero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp ueq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_inf_or_ueq_zero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp ueq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Positive test
-define i1 @not_isfinite_and_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_and_zero_f16(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @not_isfinite_and_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_and_zero_f16(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = and i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @not_isfinite_or_zero_f16_multi_use_cmp0(half %x, ptr %ptr) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp0(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    store i1 [[CMPINF]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp0(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0:![0-9]+]]
-; MSAN:       4:
-; MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7:[0-9]+]]
-; MSAN-NEXT:    unreachable
-; MSAN:       5:
-; MSAN-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; MSAN-NEXT:    [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080
-; MSAN-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
-; MSAN-NEXT:    store i1 [[TMP3]], ptr [[TMP8]], align 1
-; MSAN-NEXT:    store i1 [[CMPINF]], ptr [[PTR]], align 1
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP9:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP10:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP11:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP9]], [[TMP3]]
-; MSAN-NEXT:    [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP3]]
-; MSAN-NEXT:    [[TMP14:%.*]] = and i1 [[TMP9]], [[TMP11]]
-; MSAN-NEXT:    [[TMP15:%.*]] = or i1 [[TMP12]], [[TMP13]]
-; MSAN-NEXT:    [[TMP16:%.*]] = or i1 [[TMP15]], [[TMP14]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp0(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]]
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       5:
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
-; IC_MSAN-NEXT:    store i1 [[TMP3]], ptr [[TMP8]], align 1
-; IC_MSAN-NEXT:    store i1 [[CMPINF]], ptr [[PTR]], align 1
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP11:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP9]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP14:%.*]] = and i1 [[TMP9]], [[TMP11]]
-; IC_MSAN-NEXT:    [[TMP15:%.*]] = or i1 [[TMP12]], [[TMP13]]
-; IC_MSAN-NEXT:    [[TMP16:%.*]] = or i1 [[TMP15]], [[TMP14]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  store i1 %cmpinf, ptr %ptr
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @not_isfinite_or_zero_f16_multi_use_cmp1(half %x, ptr %ptr) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp1(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT:    store i1 [[CMPZERO]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp1(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
-; MSAN:       5:
-; MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; MSAN-NEXT:    unreachable
-; MSAN:       6:
-; MSAN-NEXT:    [[TMP7:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; MSAN-NEXT:    [[TMP8:%.*]] = xor i64 [[TMP7]], 87960930222080
-; MSAN-NEXT:    [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr
-; MSAN-NEXT:    store i1 [[TMP4]], ptr [[TMP9]], align 1
-; MSAN-NEXT:    store i1 [[CMPZERO]], ptr [[PTR]], align 1
-; MSAN-NEXT:    [[TMP10:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP11:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP3]]
-; MSAN-NEXT:    [[TMP14:%.*]] = and i1 [[TMP4]], [[TMP11]]
-; MSAN-NEXT:    [[TMP15:%.*]] = or i1 [[TMP12]], [[TMP13]]
-; MSAN-NEXT:    [[TMP16:%.*]] = or i1 [[TMP15]], [[TMP14]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_multi_use_cmp1(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
-; IC_MSAN:       5:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       6:
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = xor i64 [[TMP7]], 87960930222080
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr
-; IC_MSAN-NEXT:    store i1 [[TMP4]], ptr [[TMP9]], align 1
-; IC_MSAN-NEXT:    store i1 [[CMPZERO]], ptr [[PTR]], align 1
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP11:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP13:%.*]] = and i1 [[TMP10]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP14:%.*]] = and i1 [[TMP4]], [[TMP11]]
-; IC_MSAN-NEXT:    [[TMP15:%.*]] = or i1 [[TMP12]], [[TMP13]]
-; IC_MSAN-NEXT:    [[TMP16:%.*]] = or i1 [[TMP15]], [[TMP14]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP16]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  store i1 %cmpzero, ptr %ptr
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @not_isfinite_or_zero_f16_neg_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_neg_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ueq half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_neg_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_neg_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ueq half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xHFC00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @olt_0_or_fabs_ueq_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @olt_0_or_fabs_ueq_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_0_or_fabs_ueq_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp olt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_0_or_fabs_ueq_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp olt half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @oeq_0_or_fabs_ult_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_0_or_fabs_ult_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_0_or_fabs_ult_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_0_or_fabs_ult_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ult half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @not_isfinite_or_zero_f16_multi_not_0(half %x, ptr %ptr) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_multi_not_0(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH3C00
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_multi_not_0(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH3C00
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_multi_not_0(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH3C00
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 1.0
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @not_isfinite_or_zero_f16_fabs_wrong_val(half %x, half %y) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_fabs_wrong_val(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_fabs_wrong_val(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; MSAN-NEXT:    [[TMP2:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP2]], 0
-; MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP5]], [[TMP3]]
-; MSAN-NEXT:    [[TMP9:%.*]] = and i1 [[TMP4]], [[TMP6]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP8]]
-; MSAN-NEXT:    [[TMP11:%.*]] = or i1 [[TMP10]], [[TMP9]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP11]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_fabs_wrong_val(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP2]], 0
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP5]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = and i1 [[TMP4]], [[TMP6]]
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP8]]
-; IC_MSAN-NEXT:    [[TMP11:%.*]] = or i1 [[TMP10]], [[TMP9]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP11]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %y)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; Negative test
-define i1 @not_isfinite_or_zero_f16_not_fabs(half %x) sanitize_memory {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_not_fabs(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.canonicalize.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_not_fabs(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.canonicalize.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_not_fabs(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.canonicalize.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.canonicalize.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-; --------------------------------------------------------------------
-; Negated pattern, isfinite(x) && !(x == 0.0)
-; --------------------------------------------------------------------
-
-; Negation of base pattern, isfinite(x) && !(x == 0.0)
-define i1 @negated_isfinite_or_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, 0xH0000
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Commuted !(x == 0.0) && isfinite(x)
-define i1 @negated_isfinite_or_zero_f16_commute_and(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_commute_and(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_commute_and(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPINF]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[CMPZERO]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPINF]], [[CMPZERO]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_commute_and(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, 0xH0000
-  %not.class = and i1 %cmpinf, %cmpzero
-  ret i1 %not.class
-}
-
-; isfinite(x) && !(x == -0.0)
-define i1 @negated_isfinite_or_zero_f16_negzero(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_negzero(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_negzero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH8000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_negzero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, -0.0
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Negated pattern
-define <2 x i1> @negated_isfinite_or_zero_v2f16(<2 x half> %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_v2f16(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret <2 x i1> [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_v2f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP2:%.*]] = trunc <2 x i16> [[_MSPROP]] to <2 x i1>
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP3:%.*]] = trunc <2 x i16> [[_MSPROP1]] to <2 x i1>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une <2 x half> [[X]], zeroinitializer
-; MSAN-NEXT:    [[TMP4:%.*]] = and <2 x i1> [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and <2 x i1> [[CMPZERO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and <2 x i1> [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or <2 x i1> [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or <2 x i1> [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and <2 x i1> [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store <2 x i1> [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_v2f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp une <2 x half> %x, zeroinitializer
-  %not.class = and <2 x i1> %cmpzero, %cmpinf
-  ret <2 x i1> %not.class
-}
-
-; Negated pattern, commuted vector and
-define <2 x i1> @negated_isfinite_or_zero_v2f16_comumte(<2 x half> %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_v2f16_comumte(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret <2 x i1> [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_v2f16_comumte(
-; MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP2:%.*]] = trunc <2 x i16> [[_MSPROP]] to <2 x i1>
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or <2 x i16> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP3:%.*]] = trunc <2 x i16> [[_MSPROP1]] to <2 x i1>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une <2 x half> [[X]], zeroinitializer
-; MSAN-NEXT:    [[TMP4:%.*]] = and <2 x i1> [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and <2 x i1> [[CMPINF]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and <2 x i1> [[TMP2]], [[CMPZERO]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or <2 x i1> [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or <2 x i1> [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and <2 x i1> [[CMPINF]], [[CMPZERO]]
-; MSAN-NEXT:    store <2 x i1> [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_v2f16_comumte(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[NOT_CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp one <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp une <2 x half> %x, zeroinitializer
-  %not.class = and <2 x i1> %cmpinf, %cmpzero
-  ret <2 x i1> %not.class
-}
-
-; Positive test
-define i1 @negated_isfinite_or_zero_f16_not_une_zero(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_not_une_zero(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_not_une_zero(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp one half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_not_une_zero(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp one half %x, 0xH0000
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Positive test
-define i1 @negated_isfinite_and_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_and_zero_f16(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @negated_isfinite_and_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_and_zero_f16(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, 0xH0000
-  %not.class = or i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Negative test
-define i1 @negated_isfinite_or_zero_f16_swapped_constants(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_swapped_constants(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 412)
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_swapped_constants(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp one half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_swapped_constants(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 412)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpzero = fcmp one half %fabs, 0xH0000
-  %cmpinf = fcmp une half %x, 0xH7C00
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Negative test
-define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0(half %x, ptr %ptr) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; CHECK-NEXT:    store i1 [[CMPINF]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]]
-; MSAN:       4:
-; MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; MSAN-NEXT:    unreachable
-; MSAN:       5:
-; MSAN-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; MSAN-NEXT:    [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080
-; MSAN-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
-; MSAN-NEXT:    store i1 [[TMP3]], ptr [[TMP8]], align 1
-; MSAN-NEXT:    store i1 [[CMPINF]], ptr [[PTR]], align 1
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP9:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP10:%.*]] = and i1 [[TMP9]], [[TMP3]]
-; MSAN-NEXT:    [[TMP11:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP9]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP13:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; MSAN-NEXT:    [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP14]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF0]]
-; IC_MSAN:       4:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       5:
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
-; IC_MSAN-NEXT:    store i1 [[TMP3]], ptr [[TMP8]], align 1
-; IC_MSAN-NEXT:    store i1 [[CMPINF]], ptr [[PTR]], align 1
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = and i1 [[TMP9]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP11:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP9]], [[CMPINF]]
-; IC_MSAN-NEXT:    [[TMP13:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; IC_MSAN-NEXT:    [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP14]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  store i1 %cmpinf, ptr %ptr
-  %cmpzero = fcmp une half %x, 0xH0000
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Negative test
-define i1 @negated_isfinite_or_zero_f16_multi_use_cmp1(half %x, ptr %ptr) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp1(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; CHECK-NEXT:    store i1 [[CMPZERO]], ptr [[PTR:%.*]], align 1
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp1(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
-; MSAN:       5:
-; MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; MSAN-NEXT:    unreachable
-; MSAN:       6:
-; MSAN-NEXT:    [[TMP7:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; MSAN-NEXT:    [[TMP8:%.*]] = xor i64 [[TMP7]], 87960930222080
-; MSAN-NEXT:    [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr
-; MSAN-NEXT:    store i1 [[TMP4]], ptr [[TMP9]], align 1
-; MSAN-NEXT:    store i1 [[CMPZERO]], ptr [[PTR]], align 1
-; MSAN-NEXT:    [[TMP10:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP11:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP4]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP13:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; MSAN-NEXT:    [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP14]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp1(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF0]]
-; IC_MSAN:       5:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       6:
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = ptrtoint ptr [[PTR:%.*]] to i64
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = xor i64 [[TMP7]], 87960930222080
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr
-; IC_MSAN-NEXT:    store i1 [[TMP4]], ptr [[TMP9]], align 1
-; IC_MSAN-NEXT:    store i1 [[CMPZERO]], ptr [[PTR]], align 1
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP11:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP12:%.*]] = and i1 [[TMP4]], [[CMPINF]]
-; IC_MSAN-NEXT:    [[TMP13:%.*]] = or i1 [[TMP10]], [[TMP11]]
-; IC_MSAN-NEXT:    [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP14]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, 0xH0000
-  store i1 %cmpzero, ptr %ptr
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Negative test
-define i1 @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_multi_use_cmp0_not_one_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp une half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, 0xH0000
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; Negative test
-define i1 @negated_isfinite_or_zero_f16_fabs_wrong_value(half %x, half %y) sanitize_memory {
-; CHECK-LABEL: @negated_isfinite_or_zero_f16_fabs_wrong_value(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; MSAN-LABEL: @negated_isfinite_or_zero_f16_fabs_wrong_value(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; MSAN-NEXT:    [[TMP2:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP2]], 0
-; MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP6]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[TMP7]]
-; MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP9]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-; IC_MSAN-LABEL: @negated_isfinite_or_zero_f16_fabs_wrong_value(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[Y:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp one half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP2]], 0
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[CMPINF]]
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP5]], [[TMP6]]
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP8]], [[TMP7]]
-; IC_MSAN-NEXT:    [[NOT_CLASS:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP9]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT_CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %y)
-  %cmpinf = fcmp one half %fabs, 0xH7C00
-  %cmpzero = fcmp une half %x, 0xH0000
-  %not.class = and i1 %cmpzero, %cmpinf
-  ret i1 %not.class
-}
-
-; --------------------------------------------------------------------
-; Other fcmp to class recognition
-; --------------------------------------------------------------------
-
-define i1 @fcmp_une_0_or_fcmp_une_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_une_0_or_fcmp_une_inf(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @fcmp_une_0_or_fcmp_une_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP2]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @fcmp_une_0_or_fcmp_une_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %cmpzero = fcmp une half %x, 0.0
-  %cmpinf = fcmp une half %x, 0xH7C00
-  %or = or i1 %cmpzero, %cmpinf
-  ret i1 %or
-}
-
-define i1 @fcmp_one_0_and_fcmp_une_fabs_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp one half [[X]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @fcmp_one_0_and_fcmp_une_fabs_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 408)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpzero = fcmp one half %x, 0.0
-  %cmpinf = fcmp une half %fabs, 0xH7C00
-  %and = and i1 %cmpzero, %cmpinf
-  ret i1 %and
-}
-
-define i1 @fcmp_une_0_and_fcmp_une_fabs_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPZERO]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @fcmp_une_0_and_fcmp_une_fabs_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 411)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpzero = fcmp une half %x, 0.0
-  %cmpinf = fcmp une half %fabs, 0xH7C00
-  %and = and i1 %cmpzero, %cmpinf
-  ret i1 %and
-}
-
-define i1 @fcmp_une_0_and_fcmp_une_neginf(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_une_0_and_fcmp_une_neginf(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @fcmp_une_0_and_fcmp_une_neginf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[X]], 0xHFC00
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP2]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @fcmp_une_0_and_fcmp_une_neginf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %cmpzero = fcmp une half %x, 0.0
-  %cmpinf = fcmp une half %x, 0xHFC00
-  %or = or i1 %cmpzero, %cmpinf
-  ret i1 %or
-}
-
-define i1 @issubnormal_or_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_or_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @issubnormal_or_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @issubnormal_or_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %class
-}
-
-define i1 @olt_smallest_normal_or_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @olt_smallest_normal_or_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 764)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_or_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_or_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 764)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400 ; missing fabs
-  %class = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %class
-}
-
-define i1 @not_issubnormal_or_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @not_issubnormal_or_inf(
-; CHECK-NEXT:    [[NOT:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 267)
-; CHECK-NEXT:    ret i1 [[NOT]]
-;
-; MSAN-LABEL: @not_issubnormal_or_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp une half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[NOT:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[NOT]]
-;
-; IC_MSAN-LABEL: @not_issubnormal_or_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[NOT:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 267)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[NOT]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp une half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
-  %not = and i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %not
-}
-
-define i1 @issubnormal_uge_or_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_uge_or_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @issubnormal_uge_or_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @issubnormal_uge_or_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %class
-}
-
-; Negative test, not smallest normal
-define i1 @issubnormal_or_inf_wrong_val(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_or_inf_wrong_val(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0401
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @issubnormal_or_inf_wrong_val(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0401
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @issubnormal_or_inf_wrong_val(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0401
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0401
-  %class = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %class
-}
-
-define i1 @issubnormal_or_inf_neg_smallest_normal(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_or_inf_neg_smallest_normal(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[CMPINF]]
-;
-; MSAN-LABEL: @issubnormal_or_inf_neg_smallest_normal(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH8400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @issubnormal_or_inf_neg_smallest_normal(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CMPINF]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH8400
-  %class = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fneg_fabs_olt_neg_smallest_normal_or_inf(half %x) sanitize_memory {
-; CHECK-LABEL: @fneg_fabs_olt_neg_smallest_normal_or_inf(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp ogt half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fneg_fabs_olt_neg_smallest_normal_or_inf(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[FNEG_FABS:%.*]] = fneg half [[FABS]]
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FNEG_FABS]], 0xH8400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fneg_fabs_olt_neg_smallest_normal_or_inf(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; IC_MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp ogt half [[FABS]], 0xH0400
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; IC_MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; IC_MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %fneg.fabs = fneg half %fabs
-  %cmp.smallest.normal = fcmp olt half %fneg.fabs, 0xH8400
-  %class = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %class
-}
-
-define i1 @issubnormal_or_finite_olt(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_or_finite_olt(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 504)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @issubnormal_or_finite_olt(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp olt half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @issubnormal_or_finite_olt(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 504)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp olt half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %or = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %or
-}
-
-; inf | nan | zero | subnormal
-define i1 @issubnormal_or_finite_uge(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_or_finite_uge(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 759)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @issubnormal_or_finite_uge(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp uge half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @issubnormal_or_finite_uge(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 759)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp uge half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %or = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %or
-}
-
-define i1 @issubnormal_and_finite_olt(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_and_finite_olt(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @issubnormal_and_finite_olt(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp olt half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[CMPINF]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @issubnormal_and_finite_olt(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp olt half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %and = and i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %and
-}
-
-define i1 @not_zero_and_subnormal(half %x) sanitize_memory {
-; CHECK-LABEL: @not_zero_and_subnormal(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_zero_and_subnormal(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMP_ZERO:%.*]] = fcmp one half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMP_ZERO]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_zero_and_subnormal(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmp.zero = fcmp one half %fabs, 0.0
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %or = or i1 %cmp.smallest.normal, %cmp.zero
-  ret i1 %or
-}
-
-define i1 @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp uge half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @fcmp_fabs_uge_inf_or_fabs_uge_smallest_norm(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp uge half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
-  %or = or i1 %cmp.smallest.normal, %cmpinf
-  ret i1 %or
-}
-
-; --------------------------------------------------------------------
-; Test ord/uno
-; --------------------------------------------------------------------
-
-define i1 @is_finite_and_ord(half %x) sanitize_memory {
-; CHECK-LABEL: @is_finite_and_ord(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[AND:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @is_finite_and_ord(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[IS_FINITE:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], [[TMP1]]
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], [[X]]
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[ORD]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[IS_FINITE]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[ORD]], [[IS_FINITE]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @is_finite_and_ord(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.finite = fcmp ueq half %fabs, 0xH7C00
-  %ord = fcmp ord half %x, %x
-  %and = and i1 %ord, %is.finite
-  ret i1 %and
-}
-
-define i1 @is_finite_and_uno(half %x) sanitize_memory {
-; CHECK-LABEL: @is_finite_and_uno(
-; CHECK-NEXT:    [[AND:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @is_finite_and_uno(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[IS_FINITE:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], [[TMP1]]
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], [[X]]
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[UNO]], [[TMP2]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[IS_FINITE]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[UNO]], [[IS_FINITE]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @is_finite_and_uno(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.finite = fcmp ueq half %fabs, 0xH7C00
-  %uno = fcmp uno half %x, %x
-  %and = and i1 %uno, %is.finite
-  ret i1 %and
-}
-
-define i1 @is_finite_or_ord(half %x) sanitize_memory {
-; CHECK-LABEL: @is_finite_or_ord(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @is_finite_or_ord(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[IS_FINITE:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], [[TMP1]]
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], [[X]]
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[IS_FINITE]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[ORD]], [[IS_FINITE]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @is_finite_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.finite = fcmp ueq half %fabs, 0xH7C00
-  %ord = fcmp ord half %x, %x
-  %or = or i1 %ord, %is.finite
-  ret i1 %or
-}
-
-define i1 @is_finite_or_uno(half %x) sanitize_memory {
-; CHECK-LABEL: @is_finite_or_uno(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @is_finite_or_uno(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[IS_FINITE:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], [[TMP1]]
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], [[X]]
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[IS_FINITE]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[UNO]], [[IS_FINITE]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @is_finite_or_uno(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.finite = fcmp ueq half %fabs, 0xH7C00
-  %uno = fcmp uno half %x, %x
-  %or = or i1 %uno, %is.finite
-  ret i1 %or
-}
-
-define i1 @oeq_isinf_or_uno(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_isinf_or_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_isinf_or_uno(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP2]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[UNO]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_isinf_or_uno(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0000
-  %class = or i1 %cmpinf, %uno
-  ret i1 %class
-}
-
-define i1 @oeq_isinf_or_ord(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_isinf_or_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_isinf_or_ord(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP2]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPINF]], [[UNO]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_isinf_or_ord(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %uno = fcmp ord half %x, 0xH0000
-  %class = or i1 %cmpinf, %uno
-  ret i1 %class
-}
-
-define i1 @oeq_isinf_and_uno(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_isinf_and_uno(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @oeq_isinf_and_uno(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPINF]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[UNO]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPINF]], [[UNO]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @oeq_isinf_and_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0000
-  %and = and i1 %cmpinf, %uno
-  ret i1 %and
-}
-
-define i1 @oeq_isinf_and_ord(half %x) sanitize_memory {
-; CHECK-LABEL: @oeq_isinf_and_ord(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @oeq_isinf_and_ord(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[TMP2]], [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 [[CMPINF]], [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP2]], [[UNO]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP4]], [[TMP5]]
-; MSAN-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP6]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[CMPINF]], [[UNO]]
-; MSAN-NEXT:    store i1 [[TMP8]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @oeq_isinf_and_ord(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp oeq half %fabs, 0xH7C00
-  %uno = fcmp ord half %x, 0xH0000
-  %and = and i1 %cmpinf, %uno
-  ret i1 %and
-}
-
-; --------------------------------------------------------------------
-; isnormal(x) || x == 0.0
-; --------------------------------------------------------------------
-
-define i1 @isnormal_or_zero(half %x) #0 {
-; CHECK-LABEL: @isnormal_or_zero(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[AND1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
-; CHECK-NEXT:    ret i1 [[AND1]]
-;
-; MSAN-LABEL: @isnormal_or_zero(
-; MSAN-NEXT:  entry:
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ISEQ:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X]])
-; MSAN-NEXT:    [[ISINF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[ISNORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP0:%.*]] = and i1 [[ISEQ]], false
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 false, [[ISINF]]
-; MSAN-NEXT:    [[TMP2:%.*]] = or i1 false, [[TMP0]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 [[TMP2]], [[TMP1]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[ISEQ]], [[ISINF]]
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 [[ISNORMAL]], false
-; MSAN-NEXT:    [[TMP5:%.*]] = and i1 false, [[AND]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 false, [[TMP4]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP6]], [[TMP5]]
-; MSAN-NEXT:    [[AND1:%.*]] = and i1 [[ISNORMAL]], [[AND]]
-; MSAN-NEXT:    [[CMP:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP8:%.*]] = xor i1 [[CMP]], true
-; MSAN-NEXT:    [[TMP9:%.*]] = xor i1 [[AND1]], true
-; MSAN-NEXT:    [[TMP10:%.*]] = and i1 [[TMP8]], false
-; MSAN-NEXT:    [[TMP11:%.*]] = and i1 false, [[TMP9]]
-; MSAN-NEXT:    [[TMP12:%.*]] = or i1 false, [[TMP10]]
-; MSAN-NEXT:    [[TMP13:%.*]] = or i1 [[TMP12]], [[TMP11]]
-; MSAN-NEXT:    [[SPEC_SELECT:%.*]] = or i1 [[CMP]], [[AND1]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[SPEC_SELECT]]
-;
-; IC_MSAN-LABEL: @isnormal_or_zero(
-; IC_MSAN-NEXT:  entry:
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND1:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 360)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND1]]
-;
-entry:
-  %iseq = fcmp ord half %x, 0xH0000
-  %fabs = tail call half @llvm.fabs.f16(half %x)
-  %isinf = fcmp ult half %fabs, 0xH7C00
-  %isnormal = fcmp uge half %fabs, 0xH0400
-  %and = and i1 %iseq, %isinf
-  %and1 = and i1 %isnormal, %and
-  %cmp = fcmp oeq half %x, 0xH0000
-  %spec.select = or i1 %cmp, %and1
-  ret i1 %spec.select
-}
-
-define i1 @isnormal_uge_or_zero_oeq(half %x) #0 {
-; CHECK-LABEL: @isnormal_uge_or_zero_oeq(
-; CHECK-NEXT:  entry:
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 879)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @isnormal_uge_or_zero_oeq(
-; MSAN-NEXT:  entry:
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = tail call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP0:%.*]] = xor i1 [[IS_NORMAL]], true
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 [[TMP0]], false
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 [[TMP4]], [[TMP3]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_NORMAL]], [[IS_ZERO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @isnormal_uge_or_zero_oeq(
-; IC_MSAN-NEXT:  entry:
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 879)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-entry:
-  %fabs = tail call half @llvm.fabs.f16(half %x)
-  %is.normal = fcmp uge half %fabs, 0xH0400
-  %is.zero = fcmp oeq half %x, 0xH0000
-  %or = or i1 %is.normal, %is.zero
-  ret i1 %or
-}
-
-; --------------------------------------------------------------------
-; smallest_normal check part of isnormal(x)
-; --------------------------------------------------------------------
-
-; -> ord
-define i1 @isnormalinf_or_ord(half %x) #0 {
-; CHECK-LABEL: @isnormalinf_or_ord(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @isnormalinf_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_NORMAL_INF]], [[IS_ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @isnormalinf_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %is.ord = fcmp ord half %x, 0xH0000
-  %or = or i1 %is.normal.inf, %is.ord
-  ret i1 %or
-}
-
-; -> ord
-define i1 @ord_or_isnormalinf(half %x) #0 {
-; CHECK-LABEL: @ord_or_isnormalinf(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @ord_or_isnormalinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_ORD]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_ORD]], [[IS_NORMAL_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @ord_or_isnormalinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %is.ord = fcmp ord half %x, 0xH0000
-  %or = or i1 %is.ord, %is.normal.inf
-  ret i1 %or
-}
-
-; No fabs
-; -> iszero
-define i1 @une_or_oge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @une_or_oge_smallest_normal(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @une_or_oge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[IS_UNE:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_UNE]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_UNE]], [[IS_NORMAL_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @une_or_oge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %is.normal.inf = fcmp oge half %x, 0xH0400
-  %is.une = fcmp une half %x, 0xH0000
-  %or = or i1 %is.une, %is.normal.inf
-  ret i1 %or
-}
-
-; -> normal | inf
-define i1 @isnormalinf_or_inf(half %x) #0 {
-; CHECK-LABEL: @isnormalinf_or_inf(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @isnormalinf_or_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @isnormalinf_or_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %is.inf = fcmp oeq half %fabs, 0xH7C00
-  %or = or i1 %is.normal.inf, %is.inf
-  ret i1 %or
-}
-
-; -> pinf | pnormal
-define i1 @posisnormalinf_or_posinf(half %x) #0 {
-; CHECK-LABEL: @posisnormalinf_or_posinf(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @posisnormalinf_or_posinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_POS_NORMAL_INF:%.*]] = fcmp oge half [[X]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_POS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_POS_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @posisnormalinf_or_posinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.pos.normal.inf = fcmp oge half %x, 0xH0400
-  %is.inf = fcmp oeq half %fabs, 0xH7C00
-  %or = or i1 %is.pos.normal.inf, %is.inf
-  ret i1 %or
-}
-
-; -> normal | inf
-define i1 @isnormalinf_or_posinf(half %x) #0 {
-; CHECK-LABEL: @isnormalinf_or_posinf(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @isnormalinf_or_posinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_POS_INF:%.*]] = fcmp oeq half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_POS_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[IS_NORMAL_INF]], [[IS_POS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @isnormalinf_or_posinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 780)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %is.pos.inf = fcmp oeq half %x, 0xH7C00
-  %or = or i1 %is.normal.inf, %is.pos.inf
-  ret i1 %or
-}
-
-; -> pinf|ninf
-define i1 @isnormalinf_and_inf(half %x) #0 {
-; CHECK-LABEL: @isnormalinf_and_inf(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @isnormalinf_and_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[IS_NORMAL_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[IS_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[IS_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @isnormalinf_and_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %is.inf = fcmp oeq half %fabs, 0xH7C00
-  %and = and i1 %is.normal.inf, %is.inf
-  ret i1 %and
-}
-
-; -> pinf
-define i1 @posisnormalinf_and_posinf(half %x) #0 {
-; CHECK-LABEL: @posisnormalinf_and_posinf(
-; CHECK-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @posisnormalinf_and_posinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_POS_NORMAL_INF:%.*]] = fcmp oge half [[X]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[IS_POS_NORMAL_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[IS_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[IS_POS_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @posisnormalinf_and_posinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.pos.normal.inf = fcmp oge half %x, 0xH0400
-  %is.inf = fcmp oeq half %fabs, 0xH7C00
-  %and = and i1 %is.pos.normal.inf, %is.inf
-  ret i1 %and
-}
-
-; -> pinf
-define i1 @isnormalinf_and_posinf(half %x) #0 {
-; CHECK-LABEL: @isnormalinf_and_posinf(
-; CHECK-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @isnormalinf_and_posinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_POS_INF:%.*]] = fcmp oeq half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[IS_NORMAL_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[IS_POS_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[IS_NORMAL_INF]], [[IS_POS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @isnormalinf_and_posinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %is.pos.inf = fcmp oeq half %x, 0xH7C00
-  %and = and i1 %is.normal.inf, %is.pos.inf
-  ret i1 %and
-}
-
-; --------------------------------------------------------------------
-; smallest_normal check part of isnormal(x) with inverted compare
-; --------------------------------------------------------------------
-
-; -> true
-define i1 @not_isnormalinf_or_ord(half %x) #0 {
-; CHECK-LABEL: @not_isnormalinf_or_ord(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @not_isnormalinf_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[NOT_IS_NORMAL_INF:%.*]] = fcmp ult half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[NOT_IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_NORMAL_INF]], [[IS_ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_isnormalinf_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %not.is.normal.inf = fcmp ult half %fabs, 0xH0400
-  %is.ord = fcmp ord half %x, 0xH0000
-  %or = or i1 %not.is.normal.inf, %is.ord
-  ret i1 %or
-}
-
-; -> subnormal | zero
-define i1 @not_isnormalinf_and_ord(half %x) #0 {
-; CHECK-LABEL: @not_isnormalinf_and_ord(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @not_isnormalinf_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[NOT_IS_NORMAL_INF:%.*]] = fcmp ult half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[NOT_IS_NORMAL_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[IS_ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[NOT_IS_NORMAL_INF]], [[IS_ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @not_isnormalinf_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %not.is.normal.inf = fcmp ult half %fabs, 0xH0400
-  %is.ord = fcmp ord half %x, 0xH0000
-  %and = and i1 %not.is.normal.inf, %is.ord
-  ret i1 %and
-}
-
-; -> ~ninf
-define i1 @not_isnormalinf_or_inf(half %x) #0 {
-; CHECK-LABEL: @not_isnormalinf_or_inf(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_isnormalinf_or_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[NOT_IS_NORMAL_INF:%.*]] = fcmp ult half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp olt half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[NOT_IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_isnormalinf_or_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %not.is.normal.inf = fcmp ult half %fabs, 0xH0400
-  %is.inf = fcmp olt half %fabs, 0xH7C00
-  %or = or i1 %not.is.normal.inf, %is.inf
-  ret i1 %or
-}
-
-; -> subnormal | zero | nan
-define i1 @not_isnormalinf_or_uno(half %x) #0 {
-; CHECK-LABEL: @not_isnormalinf_or_uno(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 243)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_isnormalinf_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[NOT_IS_NORMAL_INF:%.*]] = fcmp ult half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_UNO:%.*]] = fcmp uno half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[NOT_IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_NORMAL_INF]], [[IS_UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_isnormalinf_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 243)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %not.is.normal.inf = fcmp ult half %fabs, 0xH0400
-  %is.uno = fcmp uno half %fabs, 0.0
-  %or = or i1 %not.is.normal.inf, %is.uno
-  ret i1 %or
-}
-
-; -> subnormal | zero | nan
-define i1 @not_isnormalinf_or_uno_nofabs(half %x) #0 {
-; CHECK-LABEL: @not_isnormalinf_or_uno_nofabs(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 243)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_isnormalinf_or_uno_nofabs(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[NOT_IS_NORMAL_INF:%.*]] = fcmp ult half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[NOT_IS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_NORMAL_INF]], [[IS_UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_isnormalinf_or_uno_nofabs(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 243)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %not.is.normal.inf = fcmp ult half %fabs, 0xH0400
-  %is.uno = fcmp uno half %x, 0.0
-  %or = or i1 %not.is.normal.inf, %is.uno
-  ret i1 %or
-}
-
-; -> ~pnormal
-define i1 @not_negisnormalinf_or_inf(half %x) #0 {
-; CHECK-LABEL: @not_negisnormalinf_or_inf(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_negisnormalinf_or_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[NOT_IS_NEG_NORMAL_INF:%.*]] = fcmp ult half [[X]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[NOT_IS_NEG_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_NEG_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_negisnormalinf_or_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %not.is.neg.normal.inf = fcmp ult half %x, 0xH0400
-  %is.inf = fcmp oeq half %fabs, 0xH7C00
-  %or = or i1 %not.is.neg.normal.inf, %is.inf
-  ret i1 %or
-}
-
-; -> ~pnormal
-define i1 @not_negisnormalinf_or_posinf(half %x) #0 {
-; CHECK-LABEL: @not_negisnormalinf_or_posinf(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_negisnormalinf_or_posinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[NOT_IS_POS_NORMAL_INF:%.*]] = fcmp ult half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[IS_INF:%.*]] = fcmp oeq half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[NOT_IS_POS_NORMAL_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[NOT_IS_POS_NORMAL_INF]], [[IS_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_negisnormalinf_or_posinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %not.is.pos.normal.inf = fcmp ult half %x, 0xH0400
-  %is.inf = fcmp oeq half %x, 0xH7C00
-  %or = or i1 %not.is.pos.normal.inf, %is.inf
-  ret i1 %or
-}
-
-; -> ninf | nnormal
-define i1 @not_isposnormalinf_and_isnormalinf(half %x) #0 {
-; CHECK-LABEL: @not_isposnormalinf_and_isnormalinf(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 12)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @not_isposnormalinf_and_isnormalinf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[NOT_IS_POS_NORMAL_INF:%.*]] = fcmp ult half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; MSAN-NEXT:    [[IS_NORMAL_INF:%.*]] = fcmp oge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[NOT_IS_POS_NORMAL_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[IS_NORMAL_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[NOT_IS_POS_NORMAL_INF]], [[IS_NORMAL_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @not_isposnormalinf_and_isnormalinf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 12)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %not.is.pos.normal.inf = fcmp ult half %x, 0xH0400
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.normal.inf = fcmp oge half %fabs, 0xH0400
-  %and = and i1 %not.is.pos.normal.inf, %is.normal.inf
-  ret i1 %and
-}
-
-; -> ord
-define i1 @olt_smallest_normal_or_ord(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_or_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %ord = fcmp ord half %x, 0.0
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %ord
-  ret i1 %class
-}
-
-; -> ~pinf
-define i1 @olt_smallest_normal_or_uno(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_or_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 255)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 255)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %uno = fcmp uno half %x, 0.0
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %uno
-  ret i1 %class
-}
-
-define i1 @olt_smallest_normal_or_finite(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_or_finite(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_or_finite(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_FINITE:%.*]] = fcmp olt half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_FINITE]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[IS_FINITE]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_or_finite(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.finite = fcmp olt half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %is.finite
-  ret i1 %class
-}
-
-define i1 @uge_smallest_normal_or_ord(half %x) #0 {
-; CHECK-LABEL: @uge_smallest_normal_or_ord(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @uge_smallest_normal_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @uge_smallest_normal_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %ord = fcmp ord half %x, 0.0
-  %cmp.smallest.normal = fcmp uge half %x, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %ord
-  ret i1 %class
-}
-
-; -> nan | pnormal | pinf
-define i1 @uge_smallest_normal_or_uno(half %x) #0 {
-; CHECK-LABEL: @uge_smallest_normal_or_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 771)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @uge_smallest_normal_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @uge_smallest_normal_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 771)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %uno = fcmp uno half %x, 0.0
-  %cmp.smallest.normal = fcmp uge half %x, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %uno
-  ret i1 %class
-}
-
-; -> uno
-define i1 @uge_smallest_normal_and_uno(half %x) #0 {
-; CHECK-LABEL: @uge_smallest_normal_and_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @uge_smallest_normal_and_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[UNO]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @uge_smallest_normal_and_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %uno = fcmp uno half %x, 0.0
-  %cmp.smallest.normal = fcmp uge half %x, 0xH0400
-  %class = and i1 %cmp.smallest.normal, %uno
-  ret i1 %class
-}
-
-; -> true
-define i1 @olt_infinity_or_finite(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_or_finite(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_or_finite(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[LT_INFINITY]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[LT_INFINITY]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_or_finite(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %cmp.smallest.normal, %lt.infinity
-  ret i1 %class
-}
-
-; -> zero|subnormal|normal
-define i1 @olt_infinity_and_finite(half %x) #0 { ; bustttedddd
-; CHECK-LABEL: @olt_infinity_and_finite(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_and_finite(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[LT_INFINITY]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[CMP_SMALLEST_NORMAL]], [[LT_INFINITY]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_and_finite(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = and i1 %cmp.smallest.normal, %lt.infinity
-  ret i1 %class
-}
-
-; -> ord
-define i1 @olt_infinity_or_ord(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_or_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[LT_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[LT_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %ord = fcmp ord half %x, 0xH0400
-  %class = or i1 %lt.infinity, %ord
-  ret i1 %class
-}
-
-; -> ~posinf
-define i1 @olt_infinity_or_uno(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_or_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[LT_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[LT_INFINITY]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0400
-  %class = or i1 %lt.infinity, %uno
-  ret i1 %class
-}
-
-define i1 @olt_infinity_or_subnormal(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_or_subnormal(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_or_subnormal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[LT_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_SUBNORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[LT_INFINITY]], [[IS_SUBNORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_or_subnormal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.subnormal = fcmp olt half %fabs, 0xH0400
-  %class = or i1 %lt.infinity, %is.subnormal
-  ret i1 %class
-}
-
-define i1 @olt_infinity_and_subnormal(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_and_subnormal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_and_subnormal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[LT_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[IS_SUBNORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[LT_INFINITY]], [[IS_SUBNORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_and_subnormal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.subnormal = fcmp olt half %fabs, 0xH0400
-  %class = and i1 %lt.infinity, %is.subnormal
-  ret i1 %class
-}
-
-define i1 @olt_infinity_and_not_subnormal(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_and_not_subnormal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 268)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_and_not_subnormal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[NOT_SUBNORMAL:%.*]] = xor i1 [[IS_SUBNORMAL]], true
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[LT_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[NOT_SUBNORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[LT_INFINITY]], [[NOT_SUBNORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_and_not_subnormal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 268)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.subnormal = fcmp olt half %fabs, 0xH0400
-  %not.subnormal = xor i1 %is.subnormal, true
-  %class = and i1 %lt.infinity, %not.subnormal
-  ret i1 %class
-}
-
-; -> ninf
-define i1 @olt_infinity_and_ueq_inf(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_and_ueq_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_infinity_and_ueq_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X]])
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[LT_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[EQ_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[LT_INFINITY]], [[EQ_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_and_ueq_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %eq.inf = fcmp ueq half %fabs, 0xH7C00
-  %class = and i1 %lt.infinity, %eq.inf
-  ret i1 %class
-}
-
-; -> true
-define i1 @olt_infinity_or_ueq_inf(half %x) #0 {
-; CHECK-LABEL: @olt_infinity_or_ueq_inf(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @olt_infinity_or_ueq_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_INFINITY:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp ueq half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[LT_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[EQ_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[LT_INFINITY]], [[EQ_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_infinity_or_ueq_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %lt.infinity = fcmp olt half %x, 0xH7C00
-  %eq.inf = fcmp ueq half %x, 0xH7C00
-  %class = or i1 %lt.infinity, %eq.inf
-  ret i1 %class
-}
-
-; -> pnormal
-define i1 @olt_smallest_normal_or_ueq_inf(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_or_ueq_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_or_ueq_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_NORMAL:%.*]] = fcmp olt half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp ueq half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[LT_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[EQ_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[LT_NORMAL]], [[EQ_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_or_ueq_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 767)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.normal = fcmp olt half %x, 0xH0400
-  %eq.inf = fcmp ueq half %x, 0xH7C00
-  %class = or i1 %lt.normal, %eq.inf
-  ret i1 %class
-}
-
-; -> ~pinf
-define i1 @olt_smallest_normal_or_une_inf(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_or_une_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_or_une_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_NORMAL:%.*]] = fcmp olt half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp une half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[LT_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[EQ_INF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[LT_NORMAL]], [[EQ_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_or_une_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.normal = fcmp olt half %x, 0xH0400
-  %eq.inf = fcmp une half %x, 0xH7C00
-  %class = or i1 %lt.normal, %eq.inf
-  ret i1 %class
-}
-
-; -> ninf | nnormal | subnormal | zero
-define i1 @olt_smallest_normal_and_une_inf(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_and_une_inf(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_and_une_inf(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_NORMAL:%.*]] = fcmp olt half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp une half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[LT_NORMAL]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[EQ_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[LT_NORMAL]], [[EQ_INF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_and_une_inf(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.normal = fcmp olt half %x, 0xH0400
-  %eq.inf = fcmp une half %x, 0xH7C00
-  %class = and i1 %lt.normal, %eq.inf
-  ret i1 %class
-}
-
-define i1 @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_NORMAL:%.*]] = fcmp olt half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp une half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[LT_NORMAL]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[EQ_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[LT_NORMAL]], [[EQ_INF]]
-; MSAN-NEXT:    [[EQ_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[EQ_NORMAL]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = xor i1 [[CLASS]], true
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP5]], false
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 false, [[TMP6]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 false, [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[EQ_LARGEST_NORMAL:%.*]] = or i1 [[EQ_NORMAL]], [[CLASS]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_and_une_inf_or_oeq_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.normal = fcmp olt half %x, 0xH0400
-  %eq.inf = fcmp une half %x, 0xH7C00
-  %class = and i1 %lt.normal, %eq.inf
-  %eq.normal = fcmp oeq half %x, 0xH0400
-  %eq.largest.normal = or i1 %eq.normal, %class
-  ret i1 %class
-}
-
-define i1 @olt_smallest_normal_and_une_inf_or_one_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @olt_smallest_normal_and_une_inf_or_one_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @olt_smallest_normal_and_une_inf_or_one_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[LT_NORMAL:%.*]] = fcmp olt half [[X:%.*]], 0xH0400
-; MSAN-NEXT:    [[EQ_INF:%.*]] = fcmp une half [[X]], 0xH7C00
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[LT_NORMAL]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[EQ_INF]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[LT_NORMAL]], [[EQ_INF]]
-; MSAN-NEXT:    [[NE_NORMAL:%.*]] = fcmp one half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[NE_NORMAL]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = xor i1 [[CLASS]], true
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP5]], false
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 false, [[TMP6]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 false, [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[EQ_LARGEST_NORMAL:%.*]] = or i1 [[NE_NORMAL]], [[CLASS]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @olt_smallest_normal_and_une_inf_or_one_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %lt.normal = fcmp olt half %x, 0xH0400
-  %eq.inf = fcmp une half %x, 0xH7C00
-  %class = and i1 %lt.normal, %eq.inf
-  %ne.normal = fcmp one half %x, 0xH0400
-  %eq.largest.normal = or i1 %ne.normal, %class
-  ret i1 %class
-}
-
-define i1 @oge_fabs_eq_inf_and_ord(half %x) #0 {
-; CHECK-LABEL: @oge_fabs_eq_inf_and_ord(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @oge_fabs_eq_inf_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[OGE_FABS_INF:%.*]] = fcmp oge half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[OGE_FABS_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[OGE_FABS_INF]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @oge_fabs_eq_inf_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 516)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %oge.fabs.inf = fcmp oge half %fabs, 0xH7C00
-  %ord = fcmp ord half %x, 0xH0000
-  %and = and i1 %oge.fabs.inf, %ord
-  ret i1 %and
-}
-
-define i1 @oge_eq_inf_and_ord(half %x) #0 {
-; CHECK-LABEL: @oge_eq_inf_and_ord(
-; CHECK-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @oge_eq_inf_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OGE_FABS_INF:%.*]] = fcmp oge half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[OGE_FABS_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[OGE_FABS_INF]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @oge_eq_inf_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %oge.fabs.inf = fcmp oge half %x, 0xH7C00
-  %ord = fcmp ord half %x, 0xH0000
-  %and = and i1 %oge.fabs.inf, %ord
-  ret i1 %and
-}
-
-define i1 @oge_fabs_eq_inf_or_uno(half %x) #0 {
-; CHECK-LABEL: @oge_fabs_eq_inf_or_uno(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @oge_fabs_eq_inf_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[OGE_FABS_INF:%.*]] = fcmp oge half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OGE_FABS_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[OGE_FABS_INF]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @oge_fabs_eq_inf_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 519)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %oge.fabs.inf = fcmp oge half %fabs, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0000
-  %or = or i1 %oge.fabs.inf, %uno
-  ret i1 %or
-}
-
-define i1 @oge_eq_inf_or_uno(half %x) #0 {
-; CHECK-LABEL: @oge_eq_inf_or_uno(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @oge_eq_inf_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OGE_FABS_INF:%.*]] = fcmp oge half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OGE_FABS_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[OGE_FABS_INF]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @oge_eq_inf_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %oge.fabs.inf = fcmp oge half %x, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0000
-  %or = or i1 %oge.fabs.inf, %uno
-  ret i1 %or
-}
-
-define i1 @ult_fabs_eq_inf_and_ord(half %x) #0 {
-; CHECK-LABEL: @ult_fabs_eq_inf_and_ord(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[AND:%.*]] = fcmp olt half [[FABS]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @ult_fabs_eq_inf_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[ULT_FABS_INF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[ULT_FABS_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[ULT_FABS_INF]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @ult_fabs_eq_inf_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp olt half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %ult.fabs.inf = fcmp ult half %fabs, 0xH7C00
-  %ord = fcmp ord half %x, 0xH0000
-  %and = and i1 %ult.fabs.inf, %ord
-  ret i1 %and
-}
-
-define i1 @ult_eq_inf_and_ord(half %x) #0 {
-; CHECK-LABEL: @ult_eq_inf_and_ord(
-; CHECK-NEXT:    [[AND:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @ult_eq_inf_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ULT_FABS_INF:%.*]] = fcmp ult half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[ULT_FABS_INF]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[AND:%.*]] = and i1 [[ULT_FABS_INF]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @ult_eq_inf_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp olt half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %ult.fabs.inf = fcmp ult half %x, 0xH7C00
-  %ord = fcmp ord half %x, 0xH0000
-  %and = and i1 %ult.fabs.inf, %ord
-  ret i1 %and
-}
-
-define i1 @ult_fabs_eq_inf_or_uno(half %x) #0 {
-; CHECK-LABEL: @ult_fabs_eq_inf_or_uno(
-; CHECK-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @ult_fabs_eq_inf_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[ULT_FABS_INF:%.*]] = fcmp ult half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[ULT_FABS_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[ULT_FABS_INF]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @ult_fabs_eq_inf_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 507)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %ult.fabs.inf = fcmp ult half %fabs, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0000
-  %or = or i1 %ult.fabs.inf, %uno
-  ret i1 %or
-}
-
-define i1 @ult_eq_inf_or_uno(half %x) #0 {
-; CHECK-LABEL: @ult_eq_inf_or_uno(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @ult_eq_inf_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ULT_FABS_INF:%.*]] = fcmp ult half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[ULT_FABS_INF]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[ULT_FABS_INF]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @ult_eq_inf_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp une half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %ult.fabs.inf = fcmp ult half %x, 0xH7C00
-  %uno = fcmp uno half %x, 0xH0000
-  %or = or i1 %ult.fabs.inf, %uno
-  ret i1 %or
-}
-
-
-; Can't do anything with this
-define i1 @oeq_neginfinity_or_oeq_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_or_oeq_smallest_normal(
-; CHECK-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_neginfinity_or_oeq_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_or_oeq_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OEQ_NEG_INFINITY]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp oeq half %x, 0xH0400
-  %class = or i1 %oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ninf | fcZero | fcSubnormal
-define i1 @oeq_neginfinity_or_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_neginfinity_or_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_or_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 252)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ninf
-define i1 @oeq_neginfinity_and_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_neginfinity_and_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[OEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_and_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = and i1 %oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ninf | pnormal | pinf
-define i1 @oeq_neginfinity_or_oge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_or_oge_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_neginfinity_or_oge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_or_oge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 772)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp oge half %x, 0xH0400
-  %class = or i1 %oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> false
-define i1 @oeq_neginfinity_and_oge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_and_oge_smallest_normal(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @oeq_neginfinity_and_oge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[OEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_and_oge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp oge half %x, 0xH0400
-  %class = and i1 %oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ord
-define i1 @oeq_neginfinity_or_ord(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_or_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_neginfinity_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[OEQ_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %ord = fcmp ord half %x, 0.0
-  %class = or i1 %oeq.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> ninf
-define i1 @oeq_neginfinity_and_ord(half %x) #0 {
-; CHECK-LABEL: @oeq_neginfinity_and_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @oeq_neginfinity_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[OEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[OEQ_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @oeq_neginfinity_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %oeq.neg.infinity = fcmp oeq half %x, 0xHFC00
-  %ord = fcmp ord half %x, 0.0
-  %class = and i1 %oeq.neg.infinity, %ord
-  ret i1 %class
-}
-
-; can't do anything with this
-define i1 @une_neginfinity_or_oeq_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @une_neginfinity_or_oeq_smallest_normal(
-; CHECK-NEXT:    [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[UNE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @une_neginfinity_or_oeq_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[UNE_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[UNE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @une_neginfinity_or_oeq_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[UNE_NEG_INFINITY]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[UNE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %une.neg.infinity = fcmp une half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp oeq half %x, 0xH0400
-  %class = or i1 %une.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> true
-define i1 @une_neginfinity_or_ord(half %x) #0 {
-; CHECK-LABEL: @une_neginfinity_or_ord(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @une_neginfinity_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[UNE_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[UNE_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @une_neginfinity_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %une.neg.infinity = fcmp une half %x, 0xHFC00
-  %ord = fcmp ord half %x, 0.0
-  %class = or i1 %une.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> ~(nan | ninf)
-define i1 @une_neginfinity_and_ord(half %x) #0 {
-; CHECK-LABEL: @une_neginfinity_and_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @une_neginfinity_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UNE_NEG_INFINITY:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[UNE_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[UNE_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @une_neginfinity_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %une.neg.infinity = fcmp une half %x, 0xHFC00
-  %ord = fcmp ord half %x, 0.0
-  %class = and i1 %une.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> ord
-define i1 @one_neginfinity_or_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @one_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @one_neginfinity_or_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ONE_NEG_INFINITY:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[ONE_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[ONE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @one_neginfinity_or_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %one.neg.infinity = fcmp one half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %one.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ~(nan|ninf)
-define i1 @one_neginfinity_and_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @one_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 248)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @one_neginfinity_and_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ONE_NEG_INFINITY:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[ONE_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[ONE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @one_neginfinity_and_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 248)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %one.neg.infinity = fcmp one half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = and i1 %one.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ~ninf
-define i1 @one_neginfinity_or_uno(half %x) #0 {
-; CHECK-LABEL: @one_neginfinity_or_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @one_neginfinity_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ONE_NEG_INFINITY:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[ONE_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[ONE_NEG_INFINITY]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @one_neginfinity_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp une half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %one.neg.infinity = fcmp one half %x, 0xHFC00
-  %uno = fcmp uno half %x, 0.0
-  %class = or i1 %one.neg.infinity, %uno
-  ret i1 %class
-}
-
-; -> ~ninf
-define i1 @one_neginfinity_and_ord(half %x) #0 {
-; CHECK-LABEL: @one_neginfinity_and_ord(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @one_neginfinity_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ONE_NEG_INFINITY:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[ONE_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[ONE_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @one_neginfinity_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %one.neg.infinity = fcmp one half %x, 0xHFC00
-  %ord = fcmp uno half %x, 0.0
-  %class = and i1 %one.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> pnormal|pinf
-define i1 @one_neginfinity_and_uge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @one_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 768)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @one_neginfinity_and_uge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[ONE_NEG_INFINITY:%.*]] = fcmp one half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[ONE_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[ONE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @one_neginfinity_and_uge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 768)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %one.neg.infinity = fcmp one half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp uge half %x, 0xH0400
-  %class = and i1 %one.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ~(pnormal|pinf)
-define i1 @ueq_neginfinity_or_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @ueq_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 255)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_neginfinity_or_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[UEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[UEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_neginfinity_or_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 255)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %ueq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ninf
-define i1 @ueq_neginfinity_and_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @ueq_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_neginfinity_and_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[UEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[UEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_neginfinity_and_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = and i1 %ueq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> nan|ninf
-define i1 @ueq_neginfinity_or_uno(half %x) #0 {
-; CHECK-LABEL: @ueq_neginfinity_or_uno(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_neginfinity_or_uno(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[UNO:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[UEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[UNO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[UEQ_NEG_INFINITY]], [[UNO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_neginfinity_or_uno(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
-  %uno = fcmp uno half %x, 0.0
-  %class = or i1 %ueq.neg.infinity, %uno
-  ret i1 %class
-}
-
-; -> nan|ninf
-define i1 @ueq_neginfinity_and_ord(half %x) #0 {
-; CHECK-LABEL: @ueq_neginfinity_and_ord(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_neginfinity_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp uno half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[UEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[UEQ_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_neginfinity_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
-  %ord = fcmp uno half %x, 0.0
-  %class = and i1 %ueq.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> uno
-define i1 @ueq_neginfinity_and_uge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @ueq_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @ueq_neginfinity_and_uge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[UEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[UEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @ueq_neginfinity_and_uge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp uno half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %ueq.neg.infinity = fcmp ueq half %x, 0xHFC00
-  %cmp.smallest.normal = fcmp uge half %x, 0xH0400
-  %class = and i1 %ueq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ord
-define i1 @fabs_oeq_neginfinity_or_ord(half %x) #0 {
-; CHECK-LABEL: @fabs_oeq_neginfinity_or_ord(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[ORD]]
-;
-; MSAN-LABEL: @fabs_oeq_neginfinity_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[FABS_OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[FABS_OEQ_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_oeq_neginfinity_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[ORD]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.oeq.neg.infinity = fcmp oeq half %fabs, 0xHFC00
-  %ord = fcmp ord half %x, 0.0
-  %class = or i1 %fabs.oeq.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> true
-define i1 @fabs_une_neginfinity_or_ord(half %x) #0 {
-; CHECK-LABEL: @fabs_une_neginfinity_or_ord(
-; CHECK-NEXT:    ret i1 true
-;
-; MSAN-LABEL: @fabs_une_neginfinity_or_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_UNE_NEG_INFINITY:%.*]] = fcmp une half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[FABS_UNE_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[ORD]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[FABS_UNE_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_une_neginfinity_or_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 true
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.une.neg.infinity = fcmp une half %fabs, 0xHFC00
-  %ord = fcmp une half %x, 0.0
-  %class = or i1 %fabs.une.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> une
-define i1 @fabs_une_neginfinity_and_ord(half %x) #0 {
-; CHECK-LABEL: @fabs_une_neginfinity_and_ord(
-; CHECK-NEXT:    [[ORD:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[ORD]]
-;
-; MSAN-LABEL: @fabs_une_neginfinity_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_UNE_NEG_INFINITY:%.*]] = fcmp une half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp une half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[FABS_UNE_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[FABS_UNE_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_une_neginfinity_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[ORD:%.*]] = fcmp une half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[ORD]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.une.neg.infinity = fcmp une half %fabs, 0xHFC00
-  %ord = fcmp une half %x, 0.0
-  %class = and i1 %fabs.une.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> false
-define i1 @fabs_oeq_neginfinity_and_uge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @fabs_oeq_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @fabs_oeq_neginfinity_and_uge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[FABS_OEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[FABS_OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_oeq_neginfinity_and_uge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.oeq.neg.infinity = fcmp oeq half %fabs, 0xHFC00
-  %cmp.smallest.normal = fcmp oeq half %x, 0xH0400
-  %class = and i1 %fabs.oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> false
-define i1 @fabs_oeq_neginfinity_or_uge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @fabs_oeq_neginfinity_or_uge_smallest_normal(
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X:%.*]], 0xH0400
-; CHECK-NEXT:    ret i1 [[CMP_SMALLEST_NORMAL]]
-;
-; MSAN-LABEL: @fabs_oeq_neginfinity_or_uge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[FABS_OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[FABS_OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_oeq_neginfinity_or_uge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp oeq half [[X:%.*]], 0xH0400
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CMP_SMALLEST_NORMAL]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.oeq.neg.infinity = fcmp oeq half %fabs, 0xHFC00
-  %cmp.smallest.normal = fcmp oeq half %x, 0xH0400
-  %class = or i1 %fabs.oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-;- > ord
-define i1 @fabs_oeq_neginfinity_and_ord(half %x) #0 {
-; CHECK-LABEL: @fabs_oeq_neginfinity_and_ord(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @fabs_oeq_neginfinity_and_ord(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_OEQ_NEG_INFINITY:%.*]] = fcmp oeq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[ORD:%.*]] = fcmp ord half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[FABS_OEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[ORD]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[FABS_OEQ_NEG_INFINITY]], [[ORD]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_oeq_neginfinity_and_ord(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.oeq.neg.infinity = fcmp oeq half %fabs, 0xHFC00
-  %ord = fcmp ord half %x, 0.0
-  %class = and i1 %fabs.oeq.neg.infinity, %ord
-  ret i1 %class
-}
-
-; -> false
-define i1 @fabs_ueq_neginfinity_and_olt_smallest_normal(half %x) #0 { ; WRONG
-; CHECK-LABEL: @fabs_ueq_neginfinity_and_olt_smallest_normal(
-; CHECK-NEXT:    ret i1 false
-;
-; MSAN-LABEL: @fabs_ueq_neginfinity_and_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_UEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[FABS_UEQ_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[FABS_UEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_ueq_neginfinity_and_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 false
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.ueq.neg.infinity = fcmp ueq half %fabs, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = and i1 %fabs.ueq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> pinf|pnormal
-define i1 @fabs_one_neginfinity_and_uge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @fabs_one_neginfinity_and_uge_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 768)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fabs_one_neginfinity_and_uge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_ONE_NEG_INFINITY:%.*]] = fcmp one half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = and i1 [[FABS_ONE_NEG_INFINITY]], false
-; MSAN-NEXT:    [[TMP2:%.*]] = and i1 false, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP3:%.*]] = or i1 false, [[TMP1]]
-; MSAN-NEXT:    [[TMP4:%.*]] = or i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[CLASS:%.*]] = and i1 [[FABS_ONE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_one_neginfinity_and_uge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 768)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.one.neg.infinity = fcmp one half %fabs, 0xHFC00
-  %cmp.smallest.normal = fcmp uge half %x, 0xH0400
-  %class = and i1 %fabs.one.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ord
-define i1 @fabs_one_neginfinity_or_olt_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @fabs_one_neginfinity_or_olt_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fabs_one_neginfinity_or_olt_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_ONE_NEG_INFINITY:%.*]] = fcmp one half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[X]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[FABS_ONE_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[FABS_ONE_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_one_neginfinity_or_olt_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.one.neg.infinity = fcmp one half %fabs, 0xHFC00
-  %cmp.smallest.normal = fcmp olt half %x, 0xH0400
-  %class = or i1 %fabs.one.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; -> ~(zero|subnormal)
-define i1 @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(half %x) #0 {
-; CHECK-LABEL: @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[FABS_OEQ_NEG_INFINITY:%.*]] = fcmp ueq half [[FABS]], 0xHFC00
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp uge half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[FABS_OEQ_NEG_INFINITY]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[FABS_OEQ_NEG_INFINITY]], [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fabs_ueq_neginfinity_or_fabs_uge_smallest_normal(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 783)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %fabs.oeq.neg.infinity = fcmp ueq half %fabs, 0xHFC00
-  %cmp.smallest.normal = fcmp uge half %fabs, 0xH0400
-  %class = or i1 %fabs.oeq.neg.infinity, %cmp.smallest.normal
-  ret i1 %class
-}
-
-; --------------------------------------------------------------------
-; Test denormal mode handling with x == 0
-; --------------------------------------------------------------------
-
-; Base pattern !isfinite(x) || x == 0.0, with input denormals flushed to 0
-define i1 @not_isfinite_or_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_daz(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-define <2 x i1> @not_isfinite_or_zero_v2f16_daz(<2 x half> %x) #1 {
-; CHECK-LABEL: @not_isfinite_or_zero_v2f16_daz(
-; CHECK-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; CHECK-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_v2f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; MSAN-NEXT:    [[TMP1:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP2:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP3:%.*]] = and <2 x i1> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP4:%.*]] = and <2 x i1> zeroinitializer, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or <2 x i1> zeroinitializer, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or <2 x i1> [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and <2 x i1> [[TMP1]], zeroinitializer
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and <2 x i1> zeroinitializer, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or <2 x i1> zeroinitializer, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or <2 x i1> [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
-  %class = or <2 x i1> %cmpzero, %cmpinf
-  ret <2 x i1> %class
-}
-
-; Base pattern !isfinite(x) || x == 0.0, with unknown input denormal treatment
-define i1 @not_isfinite_or_zero_f16_dynamic(half %x) #2 {
-; CHECK-LABEL: @not_isfinite_or_zero_f16_dynamic(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_f16_dynamic(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMPZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_f16_dynamic(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[FABS]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMPZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp ueq half %fabs, 0xH7C00
-  %cmpzero = fcmp oeq half %x, 0xH0000
-  %class = or i1 %cmpzero, %cmpinf
-  ret i1 %class
-}
-
-define <2 x i1> @not_isfinite_or_zero_v2f16_dynamic(<2 x half> %x) #2 {
-; CHECK-LABEL: @not_isfinite_or_zero_v2f16_dynamic(
-; CHECK-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; CHECK-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; CHECK-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; MSAN-LABEL: @not_isfinite_or_zero_v2f16_dynamic(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; MSAN-NEXT:    [[TMP1:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP2:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; MSAN-NEXT:    [[TMP3:%.*]] = and <2 x i1> [[TMP1]], zeroinitializer
-; MSAN-NEXT:    [[TMP4:%.*]] = and <2 x i1> zeroinitializer, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or <2 x i1> zeroinitializer, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or <2 x i1> [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-; IC_MSAN-LABEL: @not_isfinite_or_zero_v2f16_dynamic(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call <2 x half> @llvm.fabs.v2f16(<2 x half> [[X:%.*]])
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq <2 x half> [[FABS]], <half 0xH7C00, half 0xH7C00>
-; IC_MSAN-NEXT:    [[CMPZERO:%.*]] = fcmp oeq <2 x half> [[X]], zeroinitializer
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor <2 x i1> [[CMPZERO]], <i1 true, i1 true>
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor <2 x i1> [[CMPINF]], <i1 true, i1 true>
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and <2 x i1> [[TMP1]], zeroinitializer
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and <2 x i1> zeroinitializer, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or <2 x i1> zeroinitializer, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or <2 x i1> [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or <2 x i1> [[CMPZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret <2 x i1> [[CLASS]]
-;
-  %fabs = call <2 x half> @llvm.fabs.v2f16(<2 x half> %x)
-  %cmpinf = fcmp ueq <2 x half> %fabs, <half 0xH7C00, half 0xH7C00>
-  %cmpzero = fcmp oeq <2 x half> %x, zeroinitializer
-  %class = or <2 x i1> %cmpzero, %cmpinf
-  ret <2 x i1> %class
-}
-
-define i1 @not_zero_and_subnormal_daz(half %x) #1 {
-; CHECK-LABEL: @not_zero_and_subnormal_daz(
-; CHECK-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_zero_and_subnormal_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[CMP_ZERO:%.*]] = fcmp one half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_ZERO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_zero_and_subnormal_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[OR:%.*]] = fcmp ord half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmp.zero = fcmp one half %fabs, 0.0
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %or = or i1 %cmp.smallest.normal, %cmp.zero
-  ret i1 %or
-}
-
-define i1 @not_zero_and_subnormal_dynamic(half %x) #2 {
-; CHECK-LABEL: @not_zero_and_subnormal_dynamic(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[CMP_ZERO:%.*]] = fcmp one half [[X]], 0xH0000
-; CHECK-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
-; CHECK-NEXT:    ret i1 [[OR]]
-;
-; MSAN-LABEL: @not_zero_and_subnormal_dynamic(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[CMP_ZERO:%.*]] = fcmp one half [[FABS]], 0xH0000
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_ZERO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[OR]]
-;
-; IC_MSAN-LABEL: @not_zero_and_subnormal_dynamic(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[CMP_ZERO:%.*]] = fcmp one half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMP_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[OR:%.*]] = or i1 [[CMP_SMALLEST_NORMAL]], [[CMP_ZERO]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[OR]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %cmp.zero = fcmp one half %fabs, 0.0
-  %cmp.smallest.normal = fcmp olt half %fabs, 0xH0400
-  %or = or i1 %cmp.smallest.normal, %cmp.zero
-  ret i1 %or
-}
-
-; TODO: This could fold to just fcmp olt half %fabs, 0xH0400
-define i1 @subnormal_or_zero_ieee(half %x) #0 {
-; CHECK-LABEL: @subnormal_or_zero_ieee(
-; CHECK-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @subnormal_or_zero_ieee(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_SUBNORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_ZERO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @subnormal_or_zero_ieee(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.subnormal = fcmp olt half %fabs, 0xH0400
-  %is.zero = fcmp oeq half %x, 0xH0000
-  %and = or i1 %is.subnormal, %is.zero
-  ret i1 %and
-}
-
-define i1 @subnormal_or_zero_daz(half %x) #1 {
-; CHECK-LABEL: @subnormal_or_zero_daz(
-; CHECK-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @subnormal_or_zero_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_SUBNORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_ZERO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @subnormal_or_zero_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[AND:%.*]] = fcmp oeq half [[X:%.*]], 0xH0000
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.subnormal = fcmp olt half %fabs, 0xH0400
-  %is.zero = fcmp oeq half %x, 0xH0000
-  %and = or i1 %is.subnormal, %is.zero
-  ret i1 %and
-}
-
-define i1 @subnormal_or_zero_dynamic(half %x) #2 {
-; CHECK-LABEL: @subnormal_or_zero_dynamic(
-; CHECK-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; CHECK-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; CHECK-NEXT:    [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; CHECK-NEXT:    [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
-; CHECK-NEXT:    ret i1 [[AND]]
-;
-; MSAN-LABEL: @subnormal_or_zero_dynamic(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_SUBNORMAL]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_ZERO]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[AND]]
-;
-; IC_MSAN-LABEL: @subnormal_or_zero_dynamic(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[FABS:%.*]] = call half @llvm.fabs.f16(half [[X:%.*]])
-; IC_MSAN-NEXT:    [[IS_SUBNORMAL:%.*]] = fcmp olt half [[FABS]], 0xH0400
-; IC_MSAN-NEXT:    [[IS_ZERO:%.*]] = fcmp oeq half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[IS_SUBNORMAL]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[IS_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[AND:%.*]] = or i1 [[IS_SUBNORMAL]], [[IS_ZERO]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[AND]]
-;
-  %fabs = call half @llvm.fabs.f16(half %x)
-  %is.subnormal = fcmp olt half %fabs, 0xH0400
-  %is.zero = fcmp oeq half %x, 0xH0000
-  %and = or i1 %is.subnormal, %is.zero
-  ret i1 %and
-}
-
-define i1 @issubnormal_or_inf_nnan_logical_select(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_or_inf_nnan_logical_select(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @issubnormal_or_inf_nnan_logical_select(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call nnan half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp nnan oeq half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp nnan olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = select i1 [[CMPINF]], i1 false, i1 [[TMP3]]
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 true, [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], false
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP6]], [[TMP3]]
-; MSAN-NEXT:    [[_MSPROP_SELECT:%.*]] = select i1 [[TMP2]], i1 [[TMP7]], i1 [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = select i1 [[CMPINF]], i1 true, i1 [[CMP_SMALLEST_NORMAL]]
-; MSAN-NEXT:    store i1 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @issubnormal_or_inf_nnan_logical_select(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 756)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call nnan half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp nnan oeq half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp nnan olt half %fabs, 0xH0400
-  %class = select i1 %cmpinf, i1 true, i1 %cmp.smallest.normal
-  ret i1 %class
-}
-
-define i1 @issubnormal_and_ninf_nnan_logical_select(half %x) sanitize_memory {
-; CHECK-LABEL: @issubnormal_and_ninf_nnan_logical_select(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @issubnormal_and_ninf_nnan_logical_select(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[FABS:%.*]] = call nnan half @llvm.fabs.f16(half [[X:%.*]])
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp nnan one half [[FABS]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_SMALLEST_NORMAL:%.*]] = fcmp nnan olt half [[FABS]], 0xH0400
-; MSAN-NEXT:    [[TMP4:%.*]] = select i1 [[CMPINF]], i1 [[TMP3]], i1 false
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMP_SMALLEST_NORMAL]], false
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP3]]
-; MSAN-NEXT:    [[TMP7:%.*]] = or i1 [[TMP6]], false
-; MSAN-NEXT:    [[_MSPROP_SELECT:%.*]] = select i1 [[TMP2]], i1 [[TMP7]], i1 [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = select i1 [[CMPINF]], i1 [[CMP_SMALLEST_NORMAL]], i1 false
-; MSAN-NEXT:    store i1 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @issubnormal_and_ninf_nnan_logical_select(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 240)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %fabs = call nnan half @llvm.fabs.f16(half %x)
-  %cmpinf = fcmp nnan one half %fabs, 0xH7C00
-  %cmp.smallest.normal = fcmp nnan olt half %fabs, 0xH0400
-  %class = select i1 %cmpinf, i1 %cmp.smallest.normal, i1 false
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_neginf_or_oge_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 999)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OGE_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 999)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xHFC00
-  %cmp.oge.zero = fcmp oge half %x, 0xH0000
-  %class = or i1 %cmp.oge.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_neginf_or_oge_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 996)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OGE_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 996)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xHFC00
-  %cmp.oge.zero = fcmp oge half %x, 0xH0000
-  %class = or i1 %cmp.oge.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_neginf_or_oge_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGE_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_oge_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGE_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xHFC00
-  %cmp.oge.zero = fcmp oge half %x, 0xH0000
-  %class = or i1 %cmp.oge.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_neginf_or_oge_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGE_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_oge_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_OGE_ZERO:%.*]] = fcmp oge half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGE_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGE_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xHFC00
-  %cmp.oge.zero = fcmp oge half %x, 0xH0000
-  %class = or i1 %cmp.oge.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_neginf_or_ogt_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 900)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OGT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 900)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xHFC00
-  %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
-  %class = or i1 %cmp.ogt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_neginf_or_ogt_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OGT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xHFC00
-  %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
-  %class = or i1 %cmp.ogt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_ogt_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xHFC00
-  %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
-  %class = or i1 %cmp.ogt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_neginf_or_ogt_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_ogt_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_OGT_ZERO:%.*]] = fcmp ogt half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OGT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OGT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xHFC00
-  %cmp.ogt.zero = fcmp ogt half %x, 0xH0000
-  %class = or i1 %cmp.ogt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_neginf_or_ugt_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_UGT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 903)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xHFC00
-  %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
-  %class = or i1 %cmp.ugt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_ueq_neginf_or_ugt_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_neginf_or_ugt_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_UGT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_neginf_or_ugt_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_UGT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xHFC00
-  %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
-  %class = or i1 %cmp.ugt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_neginf_or_ugt_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; CHECK-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; MSAN-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_UGT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_neginf_or_ugt_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xHFC00
-; IC_MSAN-NEXT:    [[CMP_UGT_ZERO:%.*]] = fcmp ugt half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_UGT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_UGT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xHFC00
-  %cmp.ugt.zero = fcmp ugt half %x, 0xH0000
-  %class = or i1 %cmp.ugt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_ole_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OLE_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.ole.zero = fcmp ole half %x, 0xH0000
-  %class = or i1 %cmp.ole.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_ole_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 636)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OLE_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 636)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.ole.zero = fcmp ole half %x, 0xH0000
-  %class = or i1 %cmp.ole.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_ole_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OLE_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ole_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OLE_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.ole.zero = fcmp ole half %x, 0xH0000
-  %class = or i1 %cmp.ole.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_ole_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OLE_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ole_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_OLE_ZERO:%.*]] = fcmp ole half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OLE_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLE_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.ole.zero = fcmp ole half %x, 0xH0000
-  %class = or i1 %cmp.ole.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_olt_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 540)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OLT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 540)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.olt.zero = fcmp olt half %x, 0xH0000
-  %class = or i1 %cmp.olt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_olt_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OLT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_olt_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_OLT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.olt.zero = fcmp olt half %x, 0xH0000
-  %class = or i1 %cmp.olt.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_ult_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_ULT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.ult.zero = fcmp ult half %x, 0xH0000
-  %class = or i1 %cmp.ult.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_ult_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_ULT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.ult.zero = fcmp ult half %x, 0xH0000
-  %class = or i1 %cmp.ult.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_ult_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ult_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.ult.zero = fcmp ult half %x, 0xH0000
-  %class = or i1 %cmp.ult.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_ult_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULT_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ult_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_ULT_ZERO:%.*]] = fcmp ult half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULT_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULT_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.ult.zero = fcmp ult half %x, 0xH0000
-  %class = or i1 %cmp.ult.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_ule_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_ULE_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 639)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.ule.zero = fcmp ule half %x, 0xH0000
-  %class = or i1 %cmp.ule.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_ule_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULE_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_ule_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULE_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.ule.zero = fcmp ule half %x, 0xH0000
-  %class = or i1 %cmp.ule.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_oeq_posinf_or_ule_zero_f16_daz(half %x) #1 {
-; CHECK-LABEL: @fcmp_oeq_posinf_or_ule_zero_f16_daz(
-; CHECK-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; CHECK-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; CHECK-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_oeq_posinf_or_ule_zero_f16_daz(
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULE_ZERO]], true
-; MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_oeq_posinf_or_ule_zero_f16_daz(
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[CMPINF:%.*]] = fcmp oeq half [[X:%.*]], 0xH7C00
-; IC_MSAN-NEXT:    [[CMP_ULE_ZERO:%.*]] = fcmp ule half [[X]], 0xH0000
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = xor i1 [[CMP_ULE_ZERO]], true
-; IC_MSAN-NEXT:    [[TMP2:%.*]] = xor i1 [[CMPINF]], true
-; IC_MSAN-NEXT:    [[TMP3:%.*]] = and i1 [[TMP1]], false
-; IC_MSAN-NEXT:    [[TMP4:%.*]] = and i1 false, [[TMP2]]
-; IC_MSAN-NEXT:    [[TMP5:%.*]] = or i1 false, [[TMP3]]
-; IC_MSAN-NEXT:    [[TMP6:%.*]] = or i1 [[TMP5]], [[TMP4]]
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_ULE_ZERO]], [[CMPINF]]
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp oeq half %x, 0xH7C00
-  %cmp.ule.zero = fcmp ule half %x, 0xH0000
-  %class = or i1 %cmp.ule.zero, %cmpinf
-  ret i1 %class
-}
-
-define i1 @fcmp_ueq_posinf_or_olt_zero_f16(half %x) sanitize_memory {
-; CHECK-LABEL: @fcmp_ueq_posinf_or_olt_zero_f16(
-; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; CHECK-NEXT:    ret i1 [[CLASS]]
-;
-; MSAN-LABEL: @fcmp_ueq_posinf_or_olt_zero_f16(
-; MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; MSAN-NEXT:    call void @llvm.donothing()
-; MSAN-NEXT:    [[_MSPROP:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[_MSPROP]], 0
-; MSAN-NEXT:    [[CMPINF:%.*]] = fcmp ueq half [[X:%.*]], 0xH7C00
-; MSAN-NEXT:    [[_MSPROP1:%.*]] = or i16 [[TMP1]], 0
-; MSAN-NEXT:    [[TMP3:%.*]] = icmp ne i16 [[_MSPROP1]], 0
-; MSAN-NEXT:    [[CMP_OLT_ZERO:%.*]] = fcmp olt half [[X]], 0xH0000
-; MSAN-NEXT:    [[TMP4:%.*]] = xor i1 [[CMP_OLT_ZERO]], true
-; MSAN-NEXT:    [[TMP5:%.*]] = xor i1 [[CMPINF]], true
-; MSAN-NEXT:    [[TMP6:%.*]] = and i1 [[TMP3]], [[TMP2]]
-; MSAN-NEXT:    [[TMP7:%.*]] = and i1 [[TMP4]], [[TMP2]]
-; MSAN-NEXT:    [[TMP8:%.*]] = and i1 [[TMP3]], [[TMP5]]
-; MSAN-NEXT:    [[TMP9:%.*]] = or i1 [[TMP6]], [[TMP7]]
-; MSAN-NEXT:    [[TMP10:%.*]] = or i1 [[TMP9]], [[TMP8]]
-; MSAN-NEXT:    [[CLASS:%.*]] = or i1 [[CMP_OLT_ZERO]], [[CMPINF]]
-; MSAN-NEXT:    store i1 [[TMP10]], ptr @__msan_retval_tls, align 8
-; MSAN-NEXT:    ret i1 [[CLASS]]
-;
-; IC_MSAN-LABEL: @fcmp_ueq_posinf_or_olt_zero_f16(
-; IC_MSAN-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
-; IC_MSAN-NEXT:    call void @llvm.donothing()
-; IC_MSAN-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; IC_MSAN-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0]]
-; IC_MSAN:       2:
-; IC_MSAN-NEXT:    call void @__msan_warning_noreturn() #[[ATTR7]]
-; IC_MSAN-NEXT:    unreachable
-; IC_MSAN:       3:
-; IC_MSAN-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 543)
-; IC_MSAN-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
-; IC_MSAN-NEXT:    ret i1 [[CLASS]]
-;
-  %cmpinf = fcmp ueq half %x, 0xH7C00
-  %cmp.olt.zero = fcmp olt half %x, 0xH0000
-  %class = or i1 %cmp.olt.zero, %cmpinf
-  ret i1 %class
-}
-
-declare half @llvm.fabs.f16(half) #0
-declare half @llvm.canonicalize.f16(half) #0
-declare <2 x half> @llvm.fabs.v2f16(<2 x half>) #0
-
-attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
-attributes #1 = { "denormal-fp-math"="ieee,preserve-sign" }
-attributes #2 = { "denormal-fp-math"="ieee,dynamic" }
diff --git a/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll b/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
--- a/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/is-fpclass.ll
@@ -11,14 +11,9 @@
 ; CHECK-LABEL: @not_isfinite_or_zero_f16(
 ; CHECK-NEXT:    [[TMP1:%.*]] = load i16, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[_MSCMP:%.*]] = icmp ne i16 [[TMP1]], 0
-; CHECK-NEXT:    br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF0:![0-9]+]]
-; CHECK:       2:
-; CHECK-NEXT:    call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]
-; CHECK-NEXT:    unreachable
-; CHECK:       3:
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne i16 [[TMP1]], 0
 ; CHECK-NEXT:    [[CLASS:%.*]] = call i1 @llvm.is.fpclass.f16(half [[X:%.*]], i32 615)
-; CHECK-NEXT:    store i1 false, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT:    store i1 [[TMP2]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret i1 [[CLASS]]
 ;
   %class = call i1 @llvm.is.fpclass.f16(half %x, i32 615)
@@ -30,15 +25,9 @@
 ; CHECK-LABEL: @not_isfinite_or_zero_v2f16_pos0_neg0_vec(
 ; CHECK-NEXT:    [[TMP1:%.*]] = load <2 x i16>, ptr @__msan_param_tls, align 8
 ; CHECK-NEXT:    call void @llvm.donothing()
-; CHECK-NEXT:    [[TMP2:%.*]] = bitcast <2 x i16> [[TMP1]] to i32
-; CHECK-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 0
-; CHECK-NEXT:    br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF0]]
-; CHECK:       3:
-; CHECK-NEXT:    call void @__msan_warning_noreturn() #[[ATTR4]]
-; CHECK-NEXT:    unreachable
-; CHECK:       4:
+; CHECK-NEXT:    [[TMP2:%.*]] = icmp ne <2 x i16> [[TMP1]], zeroinitializer
 ; CHECK-NEXT:    [[CLASS:%.*]] = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> [[X:%.*]], i32 615)
-; CHECK-NEXT:    store <2 x i1> zeroinitializer, ptr @__msan_retval_tls, align 8
+; CHECK-NEXT:    store <2 x i1> [[TMP2]], ptr @__msan_retval_tls, align 8
 ; CHECK-NEXT:    ret <2 x i1> [[CLASS]]
 ;
   %class = call <2 x i1> @llvm.is.fpclass.v2f16(<2 x half> %x, i32 615)