diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -15026,6 +15026,8 @@ if (isa(Inst) && isAcquireOrStronger(Ord)) return Builder.CreateFence(AtomicOrdering::Acquire); + if(isa(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) + return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent); return nullptr; } diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll --- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -803,6 +803,7 @@ ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w ; RV32IA-WMO-NEXT: sb a1, 0(a0) +; RV32IA-WMO-NEXT: fence rw, rw ; RV32IA-WMO-NEXT: ret ; ; RV32IA-TSO-LABEL: atomic_store_i8_seq_cst: @@ -824,6 +825,7 @@ ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w ; RV64IA-WMO-NEXT: sb a1, 0(a0) +; RV64IA-WMO-NEXT: fence rw, rw ; RV64IA-WMO-NEXT: ret ; ; RV64IA-TSO-LABEL: atomic_store_i8_seq_cst: @@ -963,6 +965,7 @@ ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w ; RV32IA-WMO-NEXT: sh a1, 0(a0) +; RV32IA-WMO-NEXT: fence rw, rw ; RV32IA-WMO-NEXT: ret ; ; RV32IA-TSO-LABEL: atomic_store_i16_seq_cst: @@ -984,6 +987,7 @@ ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w ; RV64IA-WMO-NEXT: sh a1, 0(a0) +; RV64IA-WMO-NEXT: fence rw, rw ; RV64IA-WMO-NEXT: ret ; ; RV64IA-TSO-LABEL: atomic_store_i16_seq_cst: @@ -1123,6 +1127,7 @@ ; RV32IA-WMO: # %bb.0: ; RV32IA-WMO-NEXT: fence rw, w ; RV32IA-WMO-NEXT: sw a1, 0(a0) +; RV32IA-WMO-NEXT: fence rw, rw ; RV32IA-WMO-NEXT: ret ; ; RV32IA-TSO-LABEL: atomic_store_i32_seq_cst: @@ -1144,6 +1149,7 @@ ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w ; RV64IA-WMO-NEXT: sw a1, 0(a0) +; RV64IA-WMO-NEXT: fence rw, rw ; RV64IA-WMO-NEXT: ret ; ; RV64IA-TSO-LABEL: atomic_store_i32_seq_cst: @@ -1312,6 +1318,7 @@ ; RV64IA-WMO: # %bb.0: ; RV64IA-WMO-NEXT: fence rw, w ; RV64IA-WMO-NEXT: sd a1, 0(a0) +; RV64IA-WMO-NEXT: fence rw, rw ; RV64IA-WMO-NEXT: ret ; ; RV64IA-TSO-LABEL: atomic_store_i64_seq_cst: diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -58,6 +58,7 @@ ; RV32-ATOMIC: # %bb.0: ; RV32-ATOMIC-NEXT: fence rw, w ; RV32-ATOMIC-NEXT: sb zero, 0(a0) +; RV32-ATOMIC-NEXT: fence rw, rw ; RV32-ATOMIC-NEXT: ret ; ; RV64-NO-ATOMIC-LABEL: store8: @@ -75,6 +76,7 @@ ; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC-NEXT: fence rw, w ; RV64-ATOMIC-NEXT: sb zero, 0(a0) +; RV64-ATOMIC-NEXT: fence rw, rw ; RV64-ATOMIC-NEXT: ret store atomic i8 0, ptr %p seq_cst, align 1 ret void @@ -237,6 +239,7 @@ ; RV32-ATOMIC: # %bb.0: ; RV32-ATOMIC-NEXT: fence rw, w ; RV32-ATOMIC-NEXT: sh zero, 0(a0) +; RV32-ATOMIC-NEXT: fence rw, rw ; RV32-ATOMIC-NEXT: ret ; ; RV64-NO-ATOMIC-LABEL: store16: @@ -254,6 +257,7 @@ ; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC-NEXT: fence rw, w ; RV64-ATOMIC-NEXT: sh zero, 0(a0) +; RV64-ATOMIC-NEXT: fence rw, rw ; RV64-ATOMIC-NEXT: ret store atomic i16 0, ptr %p seq_cst, align 2 ret void @@ -630,6 +634,7 @@ ; RV32-ATOMIC: # %bb.0: ; RV32-ATOMIC-NEXT: fence rw, w ; RV32-ATOMIC-NEXT: sw zero, 0(a0) +; RV32-ATOMIC-NEXT: fence rw, rw ; RV32-ATOMIC-NEXT: ret ; ; RV64-NO-ATOMIC-LABEL: store32_seq_cst: @@ -647,6 +652,7 @@ ; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC-NEXT: fence rw, w ; RV64-ATOMIC-NEXT: sw zero, 0(a0) +; RV64-ATOMIC-NEXT: fence rw, rw ; RV64-ATOMIC-NEXT: ret store atomic i32 0, ptr %p seq_cst, align 4 ret void @@ -2221,6 +2227,7 @@ ; RV64-ATOMIC: # %bb.0: ; RV64-ATOMIC-NEXT: fence rw, w ; RV64-ATOMIC-NEXT: sd zero, 0(a0) +; RV64-ATOMIC-NEXT: fence rw, rw ; RV64-ATOMIC-NEXT: ret store atomic i64 0, ptr %p seq_cst, align 8 ret void