diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -169,6 +169,7 @@
 * Added support for Zfa extension version 0.2.
 * Updated support experimental vector crypto extensions to version 0.5.1 of
   the specification.
+* Removed N extension (User-Level Interrupts) CSR names in the assembler.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -67,26 +67,9 @@
 }
 
 // The following CSR encodings match those given in Tables 2.2,
-// 2.3, 2.4 and  2.5 in the RISC-V Instruction Set Manual
+// 2.3, 2.4, 2.5 and 2.6 in the RISC-V Instruction Set Manual
 // Volume II: Privileged Architecture.
 
-//===----------------------------------------------------------------------===//
-// User Trap Setup
-//===----------------------------------------------------------------------===//
-def : SysReg<"ustatus", 0x000>;
-def : SysReg<"uie", 0x004>;
-def : SysReg<"utvec", 0x005>;
-
-//===----------------------------------------------------------------------===//
-// User Trap Handling
-//===----------------------------------------------------------------------===//
-def : SysReg<"uscratch", 0x040>;
-def : SysReg<"uepc", 0x041>;
-def : SysReg<"ucause", 0x042>;
-let DeprecatedName = "ubadaddr" in
-def : SysReg<"utval", 0x043>;
-def : SysReg<"uip", 0x044>;
-
 //===----------------------------------------------------------------------===//
 // User Floating-Point CSRs
 //===----------------------------------------------------------------------===//
@@ -120,8 +103,6 @@
 // Supervisor Trap Setup
 //===----------------------------------------------------------------------===//
 def : SysReg<"sstatus", 0x100>;
-def : SysReg<"sedeleg", 0x102>;
-def : SysReg<"sideleg", 0x103>;
 def : SysReg<"sie", 0x104>;
 def : SysReg<"stvec", 0x105>;
 def : SysReg<"scounteren", 0x106>;
diff --git a/llvm/test/MC/RISCV/deprecated-csr-names.s b/llvm/test/MC/RISCV/deprecated-csr-names.s
--- a/llvm/test/MC/RISCV/deprecated-csr-names.s
+++ b/llvm/test/MC/RISCV/deprecated-csr-names.s
@@ -44,22 +44,6 @@
 
 # CHECK-WARN: warning: 'mbadaddr' is a deprecated alias for 'mtval'
 
-# ubadaddr
-# name
-# CHECK-INST: csrrw zero, utval, zero
-# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
-# CHECK-INST-ALIAS: csrw utval, zero
-# uimm12
-# CHECK-INST: csrrw zero, utval, zero
-# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04]
-# CHECK-INST-ALIAS: csrw utval, zero
-# name
-csrw ubadaddr, zero
-# uimm12
-csrrw zero, 0x043, zero
-
-# CHECK-WARN: warning: 'ubadaddr' is a deprecated alias for 'utval'
-
 # sptbr
 # name
 # CHECK-INST: csrrw zero, satp, zero
diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s
--- a/llvm/test/MC/RISCV/rv32e-valid.s
+++ b/llvm/test/MC/RISCV/rv32e-valid.s
@@ -116,9 +116,9 @@
 csrrs s0, 0xc00, x0
 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5
 csrrs s0, 0x001, a5
-# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
+# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
 csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
+# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
 csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
 csrrsi t2, 0xfff, 31
diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s
--- a/llvm/test/MC/RISCV/rv32i-valid.s
+++ b/llvm/test/MC/RISCV/rv32i-valid.s
@@ -361,10 +361,10 @@
 # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5
 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00]
 csrrs s3, 0x001, s5
-# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra
+# CHECK-ASM-AND-OBJ: csrrc sp, 0, ra
 # CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00]
 csrrc sp, 0x000, ra
-# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0
+# CHECK-ASM-AND-OBJ: csrrwi a5, 0, 0
 # CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00]
 csrrwi a5, 0x000, 0
 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -28,34 +28,6 @@
 # uimm12
 csrrs t2, 0x100, zero
 
-# sedeleg
-# name
-# CHECK-INST: csrrs t1, sedeleg, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x20,0x10]
-# CHECK-INST-ALIAS: csrr t1, sedeleg
-# uimm12
-# CHECK-INST: csrrs t2, sedeleg, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x10]
-# CHECK-INST-ALIAS: csrr t2, sedeleg
-# name
-csrrs t1, sedeleg, zero
-# uimm12
-csrrs t2, 0x102, zero
-
-# sideleg
-# name
-# CHECK-INST: csrrs t1, sideleg, zero
-# CHECK-ENC: encoding: [0x73,0x23,0x30,0x10]
-# CHECK-INST-ALIAS: csrr t1, sideleg
-# uimm12
-# CHECK-INST: csrrs t2, sideleg, zero
-# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x10]
-# CHECK-INST-ALIAS: csrr t2, sideleg
-# name
-csrrs t1, sideleg, zero
-# uimm12
-csrrs t2, 0x103, zero
-
 # sie
 # name
 # CHECK-INST: csrrs t1, sie, zero
diff --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s
--- a/llvm/test/MC/RISCV/user-csr-names.s
+++ b/llvm/test/MC/RISCV/user-csr-names.s
@@ -10,125 +10,6 @@
 # RUN:     | llvm-objdump -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
 
-##################################
-# User Trap Setup
-##################################
-
-# ustatus
-# name
-# CHECK-INST: csrrs t1, ustatus, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x00]
-# CHECK-INST-ALIAS: csrr t1, ustatus
-# uimm12
-# CHECK-INST: csrrs t2, ustatus, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x00]
-# CHECK-INST-ALIAS: csrr t2, ustatus
-csrrs t1, ustatus, zero
-# uimm12
-csrrs t2, 0x000, zero
-
-# uie
-# name
-# CHECK-INST: csrrs t1, uie, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x40,0x00]
-# CHECK-INST-ALIAS: csrr t1, uie
-# uimm12
-# CHECK-INST: csrrs t2, uie, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0x00]
-# CHECK-INST-ALIAS: csrr t2, uie
-# name
-csrrs t1, uie, zero
-# uimm12
-csrrs t2, 0x004, zero
-
-# utvec
-# name
-# CHECK-INST: csrrs t1, utvec, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x50,0x00]
-# CHECK-INST-ALIAS: csrr t1, utvec
-# uimm12
-# CHECK-INST: csrrs t2, utvec, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x50,0x00]
-# CHECK-INST-ALIAS: csrr t2, utvec
-# name
-csrrs t1, utvec, zero
-# uimm12
-csrrs t2, 0x005, zero
-
-##################################
-# User Trap Handling
-##################################
-
-# uscratch
-# name
-# CHECK-INST: csrrs t1, uscratch, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x04]
-# CHECK-INST-ALIAS: csrr t1, uscratch
-# uimm12
-# CHECK-INST: csrrs t2, uscratch, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x04]
-# CHECK-INST-ALIAS: csrr t2, uscratch
-# name
-csrrs t1, uscratch, zero
-# uimm12
-csrrs t2, 0x040, zero
-
-# uepc
-# name
-# CHECK-INST: csrrs t1, uepc, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x10,0x04]
-# CHECK-INST-ALIAS: csrr t1, uepc
-# uimm12
-# CHECK-INST: csrrs t2, uepc, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x10,0x04]
-# CHECK-INST-ALIAS: csrr t2, uepc
-# name
-csrrs t1, uepc, zero
-# uimm12
-csrrs t2, 0x041, zero
-
-# ucause
-# name
-# CHECK-INST: csrrs t1, ucause, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x20,0x04]
-# CHECK-INST-ALIAS: csrr t1, ucause
-# uimm12
-# CHECK-INST: csrrs t2, ucause, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x20,0x04]
-# CHECK-INST-ALIAS: csrr t2, ucause
-# name
-csrrs t1, ucause, zero
-# uimm12
-csrrs t2, 0x042, zero
-
-# utval
-# name
-# CHECK-INST: csrrs t1, utval, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x30,0x04]
-# CHECK-INST-ALIAS: csrr t1, utval
-# uimm12
-# CHECK-INST: csrrs t2, utval, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x30,0x04]
-# CHECK-INST-ALIAS: csrr t2, utval
-# name
-csrrs t1, utval, zero
-# uimm12
-csrrs t2, 0x043, zero
-
-# uip
-# name
-# CHECK-INST: csrrs t1, uip, zero
-# CHECK-ENC:  encoding: [0x73,0x23,0x40,0x04]
-# CHECK-INST-ALIAS: csrr t1, uip
-# uimm12
-# CHECK-INST: csrrs t2, uip, zero
-# CHECK-ENC:  encoding: [0xf3,0x23,0x40,0x04]
-# CHECK-INST-ALIAS: csrr t2, uip
-#name
-csrrs t1, uip, zero
-# uimm12
-csrrs t2, 0x044, zero
-
 ##################################
 # User Floating Point CSRs
 ##################################