Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -401,9 +401,11 @@
                           (sub node:$op2, node:$op1)>;
 def AArch64add_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2),
                              [(int_aarch64_sve_add node:$pred, node:$op1, node:$op2),
+                              (vselect node:$pred, (add node:$op1, node:$op2), node:$op1),
                               (add node:$op1, (vselect node:$pred, node:$op2, (SVEDup0)))]>;
 def AArch64sub_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2),
                              [(int_aarch64_sve_sub node:$pred, node:$op1, node:$op2),
+                              (vselect node:$pred, (sub node:$op1, node:$op2), node:$op1),
                               (sub node:$op1, (vselect node:$pred, node:$op2, (SVEDup0)))]>;
 def AArch64mla_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
                              [(int_aarch64_sve_mla node:$pred, node:$op1, node:$op2, node:$op3),
Index: llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
+++ llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll
@@ -5,9 +5,8 @@
 ; CHECK-LABEL: add_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    add z1.s, z0.s, z1.s
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, #0
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
@@ -20,9 +19,8 @@
 ; CHECK-LABEL: add_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    add z1.h, z0.h, z1.h
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, #0
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
@@ -35,9 +33,8 @@
 ; CHECK-LABEL: add_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    add z1.b, z0.b, z1.b
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z2.b, #0
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
@@ -50,9 +47,8 @@
 ; CHECK-LABEL: sub_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    sub z1.s, z0.s, z1.s
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, #0
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
@@ -65,9 +61,8 @@
 ; CHECK-LABEL: sub_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    sub z1.h, z0.h, z1.h
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, #0
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
@@ -80,9 +75,8 @@
 ; CHECK-LABEL: sub_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    sub z1.b, z0.b, z1.b
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z2.b, #0
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
@@ -943,10 +937,9 @@
 ; CHECK-LABEL: addqr_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w0
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    add z1.s, z0.s, z2.s
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    mov z1.s, w0
+; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
@@ -961,10 +954,9 @@
 ; CHECK-LABEL: addqr_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w0
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #0
-; CHECK-NEXT:    add z1.h, z0.h, z2.h
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    mov z1.h, w0
+; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
@@ -979,10 +971,9 @@
 ; CHECK-LABEL: addqr_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, w0
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, #0
-; CHECK-NEXT:    add z1.b, z0.b, z2.b
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    mov z1.b, w0
+; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
@@ -997,10 +988,9 @@
 ; CHECK-LABEL: subqr_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w0
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    sub z1.s, z0.s, z2.s
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    mov z1.s, w0
+; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
@@ -1015,10 +1005,9 @@
 ; CHECK-LABEL: subqr_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w0
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #0
-; CHECK-NEXT:    sub z1.h, z0.h, z2.h
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    mov z1.h, w0
+; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
@@ -1033,10 +1022,9 @@
 ; CHECK-LABEL: subqr_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, w0
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, #0
-; CHECK-NEXT:    sub z1.b, z0.b, z2.b
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    mov z1.b, w0
+; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
@@ -1429,9 +1417,9 @@
 ; CHECK-LABEL: add_v4i32_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    add z0.s, z0.s, z1.s
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, #0
-; CHECK-NEXT:    sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT:    add z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
@@ -1444,9 +1432,9 @@
 ; CHECK-LABEL: add_v8i16_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    add z0.h, z0.h, z1.h
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, #0
-; CHECK-NEXT:    sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT:    add z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
@@ -1459,9 +1447,9 @@
 ; CHECK-LABEL: add_v16i8_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    add z0.b, z0.b, z1.b
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z2.b, #0
-; CHECK-NEXT:    sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT:    add z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
@@ -2327,10 +2315,10 @@
 ; CHECK-LABEL: addqr_v4i32_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w0
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    add z0.s, z0.s, z2.s
-; CHECK-NEXT:    sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT:    mov z1.s, w0
+; CHECK-NEXT:    add z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
@@ -2345,10 +2333,10 @@
 ; CHECK-LABEL: addqr_v8i16_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w0
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #0
-; CHECK-NEXT:    add z0.h, z0.h, z2.h
-; CHECK-NEXT:    sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT:    mov z1.h, w0
+; CHECK-NEXT:    add z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
@@ -2363,10 +2351,10 @@
 ; CHECK-LABEL: addqr_v16i8_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, w0
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, #0
-; CHECK-NEXT:    add z0.b, z0.b, z2.b
-; CHECK-NEXT:    sel z0.b, p0, z0.b, z2.b
+; CHECK-NEXT:    mov z1.b, w0
+; CHECK-NEXT:    add z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer