diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
--- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
@@ -219,6 +219,17 @@
       Opcode == PPC::LBZU8 || Opcode == PPC::LBZUX8)
     return 56;
 
+  if (Opcode == PPC::AND || Opcode == PPC::AND8)
+    return std::max(
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI),
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI));
+
+  if (Opcode == PPC::OR || Opcode == PPC::XOR8 || Opcode == PPC::XOR ||
+      Opcode == PPC::XOR8)
+    return std::min(
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI),
+        getKnownLeadingZeroCount(MI->getOperand(1).getReg(), TII, MRI));
+
   if (TII->isZeroExtended(Reg, MRI))
     return 32;
 
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
--- a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
+++ b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
@@ -639,7 +639,6 @@
 ; P8-NEXT:    mffprwz r3, f0
 ; P8-NEXT:    xor r3, r3, r30
 ; P8-NEXT:    ld r30, 112(r1) # 8-byte Folded Reload
-; P8-NEXT:    clrldi r3, r3, 32
 ; P8-NEXT:    addi r1, r1, 128
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -679,7 +678,6 @@
 ; P9-NEXT:    xscvdpsxws f0, f1
 ; P9-NEXT:    mffprwz r3, f0
 ; P9-NEXT:    xor r3, r3, r30
-; P9-NEXT:    clrldi r3, r3, 32
 ; P9-NEXT:    addi r1, r1, 48
 ; P9-NEXT:    ld r0, 16(r1)
 ; P9-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
@@ -724,7 +722,6 @@
 ; NOVSX-NEXT:    lwz r4, 44(r1)
 ; NOVSX-NEXT:    isel r3, 0, r3, 4*cr2+lt
 ; NOVSX-NEXT:    xor r3, r4, r3
-; NOVSX-NEXT:    clrldi r3, r3, 32
 ; NOVSX-NEXT:    addi r1, r1, 48
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    lwz r12, 8(r1)
diff --git a/llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll b/llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll
--- a/llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc-clear-before-return.ll
@@ -15,7 +15,6 @@
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    xor r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_xor:
@@ -43,7 +42,6 @@
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    xor r4, r5, r4
 ; 64BIT-NEXT:    xor r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_xor2:
@@ -74,7 +72,6 @@
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    or r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_or:
@@ -102,7 +99,6 @@
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    or r4, r5, r4
 ; 64BIT-NEXT:    or r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_or2:
@@ -133,7 +129,6 @@
 ; 64BIT-NEXT:    lbz r4, 0(r3)
 ; 64BIT-NEXT:    lbz r3, 1(r3)
 ; 64BIT-NEXT:    and r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_and:
@@ -161,7 +156,6 @@
 ; 64BIT-NEXT:    lbz r3, 2(r3)
 ; 64BIT-NEXT:    and r4, r5, r4
 ; 64BIT-NEXT:    and r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_and2:
@@ -196,7 +190,6 @@
 ; 64BIT-NEXT:    and r4, r5, r4
 ; 64BIT-NEXT:    xor r4, r4, r6
 ; 64BIT-NEXT:    or r3, r4, r3
-; 64BIT-NEXT:    clrldi r3, r3, 56
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_mixed:
@@ -236,7 +229,6 @@
 ; 64BIT-NEXT:    and r5, r6, r5
 ; 64BIT-NEXT:    xor r3, r5, r3
 ; 64BIT-NEXT:    or r3, r3, r4
-; 64BIT-NEXT:    clrldi r3, r3, 48
 ; 64BIT-NEXT:    blr
 ;
 ; 32BIT-LABEL: test_mixedtype: