Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -5123,6 +5123,9 @@
   SDValue FalseV = N->getOperand(2);
   MVT VT = N->getSimpleValueType(0);
   SDLoc DL(N);
+  MVT XLenVT = Subtarget.getXLenVT();
+  bool HasCondOps = DAG.getTargetLoweringInfo().getOperationAction(
+                        ISD::SELECT, XLenVT) == TargetLowering::Legal;
 
   if (!Subtarget.hasShortForwardBranchOpt()) {
     // (select c, -1, y) -> -c | y
@@ -5137,6 +5140,11 @@
       return DAG.getNode(ISD::OR, DL, VT, Neg, TrueV);
     }
 
+    // The following combines may not be profitable when condops are
+    // available. TODO: Re-enable these combines when profitable.
+    if (HasCondOps)
+      return SDValue();
+
     // (select c, 0, y) -> (c-1) & y
     if (isNullConstant(TrueV)) {
       SDValue Neg = DAG.getNode(ISD::ADD, DL, VT, CondV,
@@ -11165,15 +11173,31 @@
   if (Subtarget.hasShortForwardBranchOpt())
     return SDValue();
 
+  MVT XLenVT = Subtarget.getXLenVT();
+
   // Only support XLenVT.
-  if (N->getValueType(0) != Subtarget.getXLenVT())
+  if (N->getValueType(0) != XLenVT)
     return SDValue();
 
   SDValue TrueVal = N->getOperand(1);
   SDValue FalseVal = N->getOperand(2);
   if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false))
     return V;
-  return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true);
+  if (SDValue V =
+          tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/ true))
+    return V;
+
+  // Only attempt further combines if the condition type is XLenVT.
+  if (N->getOperand(0).getValueType() != XLenVT)
+    return SDValue();
+
+  // Attempt further combines iff condops support is enabled. TODO: explore
+  // enabling even when condops are disabled.
+  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  if (TLI.getOperationAction(ISD::SELECT, XLenVT) == TargetLowering::Legal)
+    return combineSelectToBinOp(N, DAG, Subtarget);
+
+  return SDValue();
 }
 
 // If we're concatenating a series of vector loads like
Index: llvm/test/CodeGen/RISCV/select-binop-identity.ll
===================================================================
--- llvm/test/CodeGen/RISCV/select-binop-identity.ll
+++ llvm/test/CodeGen/RISCV/select-binop-identity.ll
@@ -44,19 +44,15 @@
 ;
 ; VTCONDOPS64-LABEL: and_select_all_ones_i32:
 ; VTCONDOPS64:       # %bb.0:
-; VTCONDOPS64-NEXT:    li a3, -1
-; VTCONDOPS64-NEXT:    vt.maskcn a3, a3, a0
-; VTCONDOPS64-NEXT:    vt.maskc a0, a1, a0
-; VTCONDOPS64-NEXT:    or a0, a0, a3
+; VTCONDOPS64-NEXT:    addi a0, a0, -1
+; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a0, a2
 ; VTCONDOPS64-NEXT:    ret
 ;
 ; ZICOND-LABEL: and_select_all_ones_i32:
 ; ZICOND:       # %bb.0:
-; ZICOND-NEXT:    li a3, -1
-; ZICOND-NEXT:    czero.nez a3, a3, a0
-; ZICOND-NEXT:    czero.eqz a0, a1, a0
-; ZICOND-NEXT:    or a0, a0, a3
+; ZICOND-NEXT:    addi a0, a0, -1
+; ZICOND-NEXT:    or a0, a0, a1
 ; ZICOND-NEXT:    and a0, a0, a2
 ; ZICOND-NEXT:    ret
   %a = select i1 %c, i32 %x, i32 -1
@@ -92,30 +88,23 @@
 ;
 ; VTCONDOPS64-LABEL: and_select_all_ones_i64:
 ; VTCONDOPS64:       # %bb.0:
-; VTCONDOPS64-NEXT:    vt.maskcn a1, a1, a0
-; VTCONDOPS64-NEXT:    li a3, -1
-; VTCONDOPS64-NEXT:    vt.maskc a0, a3, a0
+; VTCONDOPS64-NEXT:    neg a0, a0
 ; VTCONDOPS64-NEXT:    or a0, a0, a1
 ; VTCONDOPS64-NEXT:    and a0, a2, a0
 ; VTCONDOPS64-NEXT:    ret
 ;
 ; ZICOND32-LABEL: and_select_all_ones_i64:
 ; ZICOND32:       # %bb.0:
-; ZICOND32-NEXT:    czero.nez a2, a2, a0
-; ZICOND32-NEXT:    li a5, -1
-; ZICOND32-NEXT:    czero.eqz a5, a5, a0
-; ZICOND32-NEXT:    or a2, a5, a2
-; ZICOND32-NEXT:    czero.nez a0, a1, a0
-; ZICOND32-NEXT:    or a0, a5, a0
+; ZICOND32-NEXT:    neg a0, a0
+; ZICOND32-NEXT:    or a2, a0, a2
+; ZICOND32-NEXT:    or a0, a0, a1
 ; ZICOND32-NEXT:    and a0, a3, a0
 ; ZICOND32-NEXT:    and a1, a4, a2
 ; ZICOND32-NEXT:    ret
 ;
 ; ZICOND64-LABEL: and_select_all_ones_i64:
 ; ZICOND64:       # %bb.0:
-; ZICOND64-NEXT:    czero.nez a1, a1, a0
-; ZICOND64-NEXT:    li a3, -1
-; ZICOND64-NEXT:    czero.eqz a0, a3, a0
+; ZICOND64-NEXT:    neg a0, a0
 ; ZICOND64-NEXT:    or a0, a0, a1
 ; ZICOND64-NEXT:    and a0, a2, a0
 ; ZICOND64-NEXT:    ret