diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -47,7 +47,7 @@ // Utilities. //===----------------------------------------------------------------------===// -class PseudoToVInst { +function PseudoToVInst(string PseudoInst): string { defvar AffixSubsts = [["Pseudo", ""], ["_E64", ""], ["_E32", ""], @@ -80,8 +80,8 @@ ["_M4", ""], ["_M8", ""] ]; - string VInst = !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst, - !subst(AffixSubst[0], AffixSubst[1], Acc)); + return !foldl(PseudoInst, AffixSubsts, Acc, AffixSubst, + !subst(AffixSubst[0], AffixSubst[1], Acc)); } // This class describes information associated to the LMUL. @@ -126,11 +126,11 @@ // Use for zext/sext.vf8 defvar MxListVF8 = [V_M1, V_M2, V_M4, V_M8]; -class MxSet { - list m = !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], - !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], - !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8], - !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]); +function MxSet(int eew): list { + return !cond(!eq(eew, 8) : [V_MF8, V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], + !eq(eew, 16) : [V_MF4, V_MF2, V_M1, V_M2, V_M4, V_M8], + !eq(eew, 32) : [V_MF2, V_M1, V_M2, V_M4, V_M8], + !eq(eew, 64) : [V_M1, V_M2, V_M4, V_M8]); } class FPR_Info mxlist, @@ -141,34 +141,34 @@ list MxListFW = mxlistfw; } -def SCALAR_F16 : FPR_Info.m, [V_MF4, V_MF2, V_M1, V_M2, V_M4]>; -def SCALAR_F32 : FPR_Info.m, [V_MF2, V_M1, V_M2, V_M4]>; -def SCALAR_F64 : FPR_Info.m, []>; +def SCALAR_F16 : FPR_Info; +def SCALAR_F32 : FPR_Info; +def SCALAR_F64 : FPR_Info; defvar FPList = [SCALAR_F16, SCALAR_F32, SCALAR_F64]; // Used for widening instructions. It excludes F64. defvar FPListW = [SCALAR_F16, SCALAR_F32]; -class NFSet { - list L = !cond(!eq(m.value, V_M8.value): [], - !eq(m.value, V_M4.value): [2], - !eq(m.value, V_M2.value): [2, 3, 4], - true: [2, 3, 4, 5, 6, 7, 8]); +function NFSet(LMULInfo m): list { + return !cond(!eq(m.value, V_M8.value): [], + !eq(m.value, V_M4.value): [2], + !eq(m.value, V_M2.value): [2, 3, 4], + true: [2, 3, 4, 5, 6, 7, 8]); } -class log2 { - int val = !if(!eq(num, 1), 0, !add(1, log2.val)); +function log2(int num): int { + return !if(!eq(num, 1), 0, !add(1, log2(!srl(num, 1)))); } -class octuple_to_str { - string ret = !cond(!eq(octuple, 1): "MF8", - !eq(octuple, 2): "MF4", - !eq(octuple, 4): "MF2", - !eq(octuple, 8): "M1", - !eq(octuple, 16): "M2", - !eq(octuple, 32): "M4", - !eq(octuple, 64): "M8"); +function octuple_to_str(int octuple): string { + return !cond(!eq(octuple, 1): "MF8", + !eq(octuple, 2): "MF4", + !eq(octuple, 4): "MF2", + !eq(octuple, 8): "M1", + !eq(octuple, 16): "M2", + !eq(octuple, 32): "M4", + !eq(octuple, 64): "M8"); } def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>; @@ -181,11 +181,11 @@ // List of EEW. defvar EEWList = [8, 16, 32, 64]; -class SegRegClass { - VReg RC = !cast("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX, - !eq(m.value, V_MF4.value): V_M1.MX, - !eq(m.value, V_MF2.value): V_M1.MX, - true: m.MX)); +function SegRegClass(LMULInfo m, int nf): VReg { + return !cast("VRN" # nf # !cond(!eq(m.value, V_MF8.value): V_M1.MX, + !eq(m.value, V_MF4.value): V_M1.MX, + !eq(m.value, V_MF2.value): V_M1.MX, + true: m.MX)); } //===----------------------------------------------------------------------===// @@ -198,7 +198,7 @@ ValueType Vector = Vec; ValueType Mask = Mas; int SEW = Sew; - int Log2SEW = log2.val; + int Log2SEW = log2(Sew); VReg RegClass = Reg; LMULInfo LMul = M; ValueType Scalar = Scal; @@ -293,14 +293,13 @@ } } -// This functor is used to obtain the int vector type that has the same SEW and +// This function is used to obtain the int vector type that has the same SEW and // multiplier as the input parameter type -class GetIntVTypeInfo -{ +function GetIntVTypeInfo(VTypeInfo vti): VTypeInfo { // Equivalent integer vector type. Eg. // VI8M1 → VI8M1 (identity) // VF64M4 → VI64M4 - VTypeInfo Vti = !cast(!subst("VF", "VI", !cast(vti))); + return !cast(!subst("VF", "VI", !cast(vti))); } class MTypeInfo { @@ -441,7 +440,7 @@ def InvalidIndex : CONST8b<0x80>; class RISCVVPseudo { Pseudo Pseudo = !cast(NAME); // Used as a key. - Instruction BaseInstr = !cast(PseudoToVInst.VInst); + Instruction BaseInstr = !cast(PseudoToVInst(NAME)); } // The actual table. @@ -637,33 +636,33 @@ // overlap the source mask register (v0), unless the destination vector register // is being written with a mask value (e.g., comparisons) or the scalar result // of a reduction. -class GetVRegNoV0 { - VReg R = !cond(!eq(VRegClass, VR) : VRNoV0, - !eq(VRegClass, VRM2) : VRM2NoV0, - !eq(VRegClass, VRM4) : VRM4NoV0, - !eq(VRegClass, VRM8) : VRM8NoV0, - !eq(VRegClass, VRN2M1) : VRN2M1NoV0, - !eq(VRegClass, VRN2M2) : VRN2M2NoV0, - !eq(VRegClass, VRN2M4) : VRN2M4NoV0, - !eq(VRegClass, VRN3M1) : VRN3M1NoV0, - !eq(VRegClass, VRN3M2) : VRN3M2NoV0, - !eq(VRegClass, VRN4M1) : VRN4M1NoV0, - !eq(VRegClass, VRN4M2) : VRN4M2NoV0, - !eq(VRegClass, VRN5M1) : VRN5M1NoV0, - !eq(VRegClass, VRN6M1) : VRN6M1NoV0, - !eq(VRegClass, VRN7M1) : VRN7M1NoV0, - !eq(VRegClass, VRN8M1) : VRN8M1NoV0, - true : VRegClass); +function GetVRegNoV0(VReg VRegClass): VReg { + return !cond(!eq(VRegClass, VR) : VRNoV0, + !eq(VRegClass, VRM2) : VRM2NoV0, + !eq(VRegClass, VRM4) : VRM4NoV0, + !eq(VRegClass, VRM8) : VRM8NoV0, + !eq(VRegClass, VRN2M1) : VRN2M1NoV0, + !eq(VRegClass, VRN2M2) : VRN2M2NoV0, + !eq(VRegClass, VRN2M4) : VRN2M4NoV0, + !eq(VRegClass, VRN3M1) : VRN3M1NoV0, + !eq(VRegClass, VRN3M2) : VRN3M2NoV0, + !eq(VRegClass, VRN4M1) : VRN4M1NoV0, + !eq(VRegClass, VRN4M2) : VRN4M2NoV0, + !eq(VRegClass, VRN5M1) : VRN5M1NoV0, + !eq(VRegClass, VRN6M1) : VRN6M1NoV0, + !eq(VRegClass, VRN7M1) : VRN7M1NoV0, + !eq(VRegClass, VRN8M1) : VRN8M1NoV0, + true : VRegClass); } // Join strings in list using separator and ignoring empty elements -class Join strings, string separator> { - string ret = !foldl(!head(strings), !tail(strings), a, b, - !cond( - !and(!empty(a), !empty(b)) : "", - !empty(a) : b, - !empty(b) : a, - 1 : a#separator#b)); +function Join(list strings, string separator): string { + return !foldl(!head(strings), !tail(strings), a, b, + !cond( + !and(!empty(a), !empty(b)) : "", + !empty(a) : b, + !empty(b) : a, + 1 : a#separator#b)); } class VPseudo : @@ -676,7 +675,7 @@ Pseudo<(outs RetClass:$rd), (ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -689,7 +688,7 @@ Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -701,12 +700,12 @@ } class VPseudoUSLoadMask : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -722,7 +721,7 @@ Pseudo<(outs RetClass:$rd, GPR:$vl), (ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -735,7 +734,7 @@ Pseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -747,12 +746,12 @@ } class VPseudoUSLoadFFMask : - Pseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd, GPR:$vl), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -768,7 +767,7 @@ Pseudo<(outs RetClass:$rd), (ins GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -781,7 +780,7 @@ Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -793,12 +792,12 @@ } class VPseudoSLoadMask: - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLE.val, VLMul> { + RISCVVLE { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -816,7 +815,7 @@ (ins GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLX.val, VLMul, LMUL> { + RISCVVLX { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -832,7 +831,7 @@ (ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLX.val, VLMul, LMUL> { + RISCVVLX { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -845,12 +844,12 @@ class VPseudoILoadMask LMUL, bit Ordered, bit EarlyClobber>: - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLX.val, VLMul, LMUL> { + RISCVVLX { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -866,7 +865,7 @@ Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSE.val, VLMul> { + RISCVVSE { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -879,7 +878,7 @@ Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSE.val, VLMul> { + RISCVVSE { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -891,7 +890,7 @@ Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSE.val, VLMul> { + RISCVVSE { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -904,7 +903,7 @@ Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSE.val, VLMul> { + RISCVVSE { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -966,8 +965,8 @@ } class VPseudoNullaryMask: - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, VMaskOp:$vm, AVL:$vl, + Pseudo<(outs GetVRegNoV0'(RegClass):$rd), + (ins GetVRegNoV0'(RegClass):$merge, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; @@ -1017,7 +1016,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasDummyMask = 1; @@ -1025,14 +1024,14 @@ } class VPseudoUnaryMask : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, OpClass:$rs2, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1040,14 +1039,14 @@ } class VPseudoUnaryMaskTA : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, OpClass:$rs2, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1056,13 +1055,13 @@ } class VPseudoUnaryMaskTA_NoExcept : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, OpClass:$rs2, VMaskOp:$vm, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1072,13 +1071,13 @@ } class VPseudoUnaryMaskTA_FRM : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, OpClass:$rs2, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, OpClass:$rs2, VMaskOp:$vm, ixlenimm:$frm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1144,7 +1143,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasDummyMask = 1; @@ -1164,7 +1163,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $rs2"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $rs2"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasDummyMask = 1; @@ -1177,7 +1176,7 @@ Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSX.val, VLMul, LMUL> { + RISCVVSX { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1191,7 +1190,7 @@ Pseudo<(outs), (ins StClass:$rd, GPRMem:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSX.val, VLMul, LMUL> { + RISCVVSX { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1203,15 +1202,15 @@ RegisterClass Op1Class, DAGOperand Op2Class, string Constraint> : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1221,15 +1220,15 @@ RegisterClass Op1Class, DAGOperand Op2Class, string Constraint> : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1241,15 +1240,15 @@ RegisterClass Op1Class, DAGOperand Op2Class, string Constraint> : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1269,7 +1268,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1282,15 +1281,15 @@ class VPseudoTiedBinaryMask : - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, Op2Class:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, RISCVVPseudo { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 0; // Merge is also rs2. @@ -1335,7 +1334,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $merge"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1355,7 +1354,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $rs3"], ","); let HasVLOp = 1; let HasSEWOp = 1; let HasMergeOp = 1; @@ -1374,7 +1373,7 @@ let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; - let Constraints = Join<[Constraint, "$rd = $rs3"], ",">.ret; + let Constraints = Join([Constraint, "$rd = $rs3"], ","); let HasVecPolicyOp = 1; let HasVLOp = 1; let HasSEWOp = 1; @@ -1386,7 +1385,7 @@ Pseudo<(outs RetClass:$rd), (ins GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1399,7 +1398,7 @@ Pseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1411,11 +1410,11 @@ } class VPseudoUSSegLoadMask NF>: - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, GPRMem:$rs1, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1431,7 +1430,7 @@ Pseudo<(outs RetClass:$rd, GPR:$vl), (ins GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1444,7 +1443,7 @@ Pseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMem:$rs1, AVL:$avl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1456,11 +1455,11 @@ } class VPseudoUSSegLoadFFMask NF>: - Pseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), - (ins GetVRegNoV0.R:$merge, GPRMem:$rs1, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd, GPR:$vl), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, VMaskOp:$vm, AVL:$avl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1476,7 +1475,7 @@ Pseudo<(outs RetClass:$rd), (ins GPRMem:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1489,7 +1488,7 @@ Pseudo<(outs RetClass:$rd), (ins RetClass:$merge, GPRMem:$rs1, GPR:$offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1501,12 +1500,12 @@ } class VPseudoSSegLoadMask NF>: - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, GPRMem:$rs1, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, GPR:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLSEG.val, VLMul> { + RISCVVLSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1523,7 +1522,7 @@ Pseudo<(outs RetClass:$rd), (ins GPRMem:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLXSEG.val, VLMul, LMUL> { + RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1540,7 +1539,7 @@ Pseudo<(outs RetClass:$rd), (ins RetClass:$merge, GPRMem:$rs1, IdxClass:$offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVLXSEG.val, VLMul, LMUL> { + RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1555,12 +1554,12 @@ class VPseudoISegLoadMask LMUL, bits<4> NF, bit Ordered>: - Pseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$merge, GPRMem:$rs1, + Pseudo<(outs GetVRegNoV0'(RetClass):$rd), + (ins GetVRegNoV0'(RetClass):$merge, GPRMem:$rs1, IdxClass:$offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),[]>, RISCVVPseudo, - RISCVVLXSEG.val, VLMul, LMUL> { + RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; let hasSideEffects = 0; @@ -1578,7 +1577,7 @@ Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSSEG.val, VLMul> { + RISCVVSSEG { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1592,7 +1591,7 @@ (ins ValClass:$rd, GPRMem:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSSEG.val, VLMul> { + RISCVVSSEG { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1604,7 +1603,7 @@ Pseudo<(outs), (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSSEG.val, VLMul> { + RISCVVSSEG { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1618,7 +1617,7 @@ (ins ValClass:$rd, GPRMem:$rs1, GPR: $offset, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSSEG.val, VLMul> { + RISCVVSSEG { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1632,7 +1631,7 @@ (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSXSEG.val, VLMul, LMUL> { + RISCVVSXSEG { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1647,7 +1646,7 @@ (ins ValClass:$rd, GPRMem:$rs1, IdxClass: $index, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew),[]>, RISCVVPseudo, - RISCVVSXSEG.val, VLMul, LMUL> { + RISCVVSXSEG { let mayLoad = 0; let mayStore = 1; let hasSideEffects = 0; @@ -1657,7 +1656,7 @@ multiclass VPseudoUSLoad { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; defvar vreg = lmul.vrclass; let VLMul = lmul.value in { @@ -1678,7 +1677,7 @@ multiclass VPseudoFFLoad { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; defvar vreg = lmul.vrclass; let VLMul = lmul.value in { @@ -1710,7 +1709,7 @@ multiclass VPseudoSLoad { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; defvar vreg = lmul.vrclass; let VLMul = lmul.value in { @@ -1730,13 +1729,13 @@ multiclass VPseudoILoad { foreach eew = EEWList in { foreach sew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(sew) in { defvar octuple_lmul = lmul.octuple; // Calculate emul = eew * lmul / sew - defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2.val); + defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2(sew)); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar DataLInfo = lmul.MX; - defvar IdxLInfo = octuple_to_str.ret; + defvar IdxLInfo = octuple_to_str(octuple_emul); defvar idx_lmul = !cast("V_" # IdxLInfo); defvar Vreg = lmul.vrclass; defvar IdxVreg = idx_lmul.vrclass; @@ -1762,7 +1761,7 @@ multiclass VPseudoUSStore { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; defvar vreg = lmul.vrclass; let VLMul = lmul.value in { @@ -1788,7 +1787,7 @@ multiclass VPseudoSStore { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; defvar vreg = lmul.vrclass; let VLMul = lmul.value in { @@ -1804,13 +1803,13 @@ multiclass VPseudoIStore { foreach eew = EEWList in { foreach sew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(sew) in { defvar octuple_lmul = lmul.octuple; // Calculate emul = eew * lmul / sew - defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2.val); + defvar octuple_emul = !srl(!mul(eew, octuple_lmul), log2(sew)); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar DataLInfo = lmul.MX; - defvar IdxLInfo = octuple_to_str.ret; + defvar IdxLInfo = octuple_to_str(octuple_emul); defvar idx_lmul = !cast("V_" # IdxLInfo); defvar Vreg = lmul.vrclass; defvar IdxVreg = idx_lmul.vrclass; @@ -1927,7 +1926,7 @@ multiclass VPseudoVCPR_V { foreach m = MxList in { defvar mx = m.MX; - defvar sews = SchedSEWSet.val; + defvar sews = SchedSEWSet(mx); let VLMul = m.value in foreach e = sews in { defvar suffix = "_" # m.MX # "_E" # e; @@ -2060,11 +2059,11 @@ foreach sew = EEWList in { defvar octuple_lmul = m.octuple; // emul = lmul * eew / sew - defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2.val); + defvar octuple_emul = !srl(!mul(octuple_lmul, eew), log2(sew)); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { - defvar emulMX = octuple_to_str.ret; + defvar emulMX = octuple_to_str(octuple_emul); defvar emul = !cast("V_" # emulMX); - defvar sews = SchedSEWSet.val; + defvar sews = SchedSEWSet(mx); foreach e = sews in { defvar WriteVRGatherVV_MX_E = !cast("WriteVRGatherVV_" # mx # "_E" # e); defvar ReadVRGatherVV_data_MX_E = !cast("ReadVRGatherVV_data_" # mx # "_E" # e); @@ -2207,7 +2206,7 @@ def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarryIn.R, m.vrclass)), + GetVRegNoV0(m.vrclass), m.vrclass)), m.vrclass, m.vrclass, m, CarryIn, Constraint>; } @@ -2216,7 +2215,7 @@ def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU" : VPseudoTiedBinaryCarryIn.R, m.vrclass)), + GetVRegNoV0(m.vrclass), m.vrclass)), m.vrclass, m.vrclass, m, CarryIn, Constraint>; } @@ -2225,7 +2224,7 @@ def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarryIn.R, m.vrclass)), + GetVRegNoV0(m.vrclass), m.vrclass)), m.vrclass, GPR, m, CarryIn, Constraint>; } @@ -2234,7 +2233,7 @@ def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU": VPseudoTiedBinaryCarryIn.R, m.vrclass)), + GetVRegNoV0(m.vrclass), m.vrclass)), m.vrclass, GPR, m, CarryIn, Constraint>; } @@ -2247,12 +2246,12 @@ defvar ReadVFMergeF_MX = !cast("ReadVFMergeF_" # mx); def "_V" # f.FX # "M_" # mx : - VPseudoBinaryCarryIn.R, + VPseudoBinaryCarryIn, Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>; // Tied version to allow codegen control over the tail elements def "_V" # f.FX # "M_" # mx # "_TU": - VPseudoTiedBinaryCarryIn.R, + VPseudoTiedBinaryCarryIn, Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>; } @@ -2264,7 +2263,7 @@ def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX : VPseudoBinaryCarryIn.R, m.vrclass)), + GetVRegNoV0(m.vrclass), m.vrclass)), m.vrclass, simm5, m, CarryIn, Constraint>; } @@ -2273,7 +2272,7 @@ def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX # "_TU": VPseudoTiedBinaryCarryIn.R, m.vrclass)), + GetVRegNoV0(m.vrclass), m.vrclass)), m.vrclass, simm5, m, CarryIn, Constraint>; } @@ -2345,7 +2344,7 @@ multiclass VPseudoVSQR_V { foreach m = MxListF in { defvar mx = m.MX; - defvar sews = SchedSEWSetF.val; + defvar sews = SchedSEWSetF(mx); let VLMul = m.value in foreach e = sews in { @@ -2496,7 +2495,7 @@ defm "" : VPseudoBinaryV_VI, Sched<[WriteVRGatherVI_MX, ReadVRGatherVI_data_MX, ReadVMask]>; - defvar sews = SchedSEWSet.val; + defvar sews = SchedSEWSet(mx); foreach e = sews in { defvar WriteVRGatherVV_MX_E = !cast("WriteVRGatherVV_" # mx # "_E" # e); defvar ReadVRGatherVV_data_MX_E = !cast("ReadVRGatherVV_data_" # mx # "_E" # e); @@ -2659,7 +2658,7 @@ multiclass VPseudoVDIV_VV_VX { foreach m = MxList in { defvar mx = m.MX; - defvar sews = SchedSEWSet.val; + defvar sews = SchedSEWSet(mx); foreach e = sews in { defvar WriteVIDivV_MX_E = !cast("WriteVIDivV_" # mx # "_E" # e); defvar WriteVIDivX_MX_E = !cast("WriteVIDivX_" # mx # "_E" # e); @@ -2700,7 +2699,7 @@ multiclass VPseudoVFDIV_VV_VF { foreach m = MxListF in { defvar mx = m.MX; - defvar sews = SchedSEWSetF.val; + defvar sews = SchedSEWSetF(mx); foreach e = sews in { defvar WriteVFDivV_MX_E = !cast("WriteVFDivV_" # mx # "_E" # e); defvar ReadVFDivV_MX_E = !cast("ReadVFDivV_" # mx # "_E" # e); @@ -2713,7 +2712,7 @@ foreach f = FPList in { foreach m = f.MxList in { defvar mx = m.MX; - defvar sews = SchedSEWSetF.val; + defvar sews = SchedSEWSetF(mx); foreach e = sews in { defvar WriteVFDivF_MX_E = !cast("WriteVFDivF_" # mx # "_E" # e); defvar ReadVFDivV_MX_E = !cast("ReadVFDivV_" # mx # "_E" # e); @@ -2730,7 +2729,7 @@ foreach f = FPList in { foreach m = f.MxList in { defvar mx = m.MX; - defvar sews = SchedSEWSetF.val; + defvar sews = SchedSEWSetF(mx); foreach e = sews in { defvar WriteVFDivF_MX_E = !cast("WriteVFDivF_" # mx # "_E" # e); defvar ReadVFDivV_MX_E = !cast("ReadVFDivV_" # mx # "_E" # e); @@ -3171,7 +3170,7 @@ bit Commutable = 0> { let VLMul = MInfo.value in { defvar mx = MInfo.MX; - defvar sews = SchedSEWSet.val; + defvar sews = SchedSEWSet(mx); foreach e = sews in { let isCommutable = Commutable in def "_" # mx # "_E" # e : VPseudoTernaryNoMaskWithPolicy; @@ -3696,11 +3695,11 @@ multiclass VPseudoUSSegLoad { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; let VLMul = lmul.value in { - foreach nf = NFSet.L in { - defvar vreg = SegRegClass.RC; + foreach nf = NFSet(lmul) in { + defvar vreg = SegRegClass(lmul, nf); def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegLoadNoMask, VLSEGSched; def nf # "E" # eew # "_V_" # LInfo # "_TU" : @@ -3715,11 +3714,11 @@ multiclass VPseudoUSSegLoadFF { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; let VLMul = lmul.value in { - foreach nf = NFSet.L in { - defvar vreg = SegRegClass.RC; + foreach nf = NFSet(lmul) in { + defvar vreg = SegRegClass(lmul, nf); def nf # "E" # eew # "FF_V_" # LInfo : VPseudoUSSegLoadFFNoMask, VLSEGFFSched; def nf # "E" # eew # "FF_V_" # LInfo # "_TU" : @@ -3734,11 +3733,11 @@ multiclass VPseudoSSegLoad { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; let VLMul = lmul.value in { - foreach nf = NFSet.L in { - defvar vreg = SegRegClass.RC; + foreach nf = NFSet(lmul) in { + defvar vreg = SegRegClass(lmul, nf); def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegLoadNoMask, VLSSEGSched; def nf # "E" # eew # "_V_" # LInfo # "_TU" : VPseudoSSegLoadNoMaskTU, @@ -3754,20 +3753,20 @@ multiclass VPseudoISegLoad { foreach idx_eew = EEWList in { foreach sew = EEWList in { - foreach val_lmul = MxSet.m in { + foreach val_lmul = MxSet(sew) in { defvar octuple_lmul = val_lmul.octuple; // Calculate emul = eew * lmul / sew - defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2.val); + defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2(sew)); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar ValLInfo = val_lmul.MX; - defvar IdxLInfo = octuple_to_str.ret; + defvar IdxLInfo = octuple_to_str(octuple_emul); defvar idx_lmul = !cast("V_" # IdxLInfo); defvar Vreg = val_lmul.vrclass; defvar IdxVreg = idx_lmul.vrclass; defvar Order = !if(Ordered, "O", "U"); let VLMul = val_lmul.value in { - foreach nf = NFSet.L in { - defvar ValVreg = SegRegClass.RC; + foreach nf = NFSet(val_lmul) in { + defvar ValVreg = SegRegClass(val_lmul, nf); def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo : VPseudoISegLoadNoMask, @@ -3790,11 +3789,11 @@ multiclass VPseudoUSSegStore { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; let VLMul = lmul.value in { - foreach nf = NFSet.L in { - defvar vreg = SegRegClass.RC; + foreach nf = NFSet(lmul) in { + defvar vreg = SegRegClass(lmul, nf); def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegStoreNoMask, VSSEGSched; def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegStoreMask, @@ -3807,11 +3806,11 @@ multiclass VPseudoSSegStore { foreach eew = EEWList in { - foreach lmul = MxSet.m in { + foreach lmul = MxSet(eew) in { defvar LInfo = lmul.MX; let VLMul = lmul.value in { - foreach nf = NFSet.L in { - defvar vreg = SegRegClass.RC; + foreach nf = NFSet(lmul) in { + defvar vreg = SegRegClass(lmul, nf); def nf # "E" # eew # "_V_" # LInfo : VPseudoSSegStoreNoMask, VSSSEGSched; def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoSSegStoreMask, @@ -3825,20 +3824,20 @@ multiclass VPseudoISegStore { foreach idx_eew = EEWList in { foreach sew = EEWList in { - foreach val_lmul = MxSet.m in { + foreach val_lmul = MxSet(sew) in { defvar octuple_lmul = val_lmul.octuple; // Calculate emul = eew * lmul / sew - defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2.val); + defvar octuple_emul = !srl(!mul(idx_eew, octuple_lmul), log2(sew)); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { defvar ValLInfo = val_lmul.MX; - defvar IdxLInfo = octuple_to_str.ret; + defvar IdxLInfo = octuple_to_str(octuple_emul); defvar idx_lmul = !cast("V_" # IdxLInfo); defvar Vreg = val_lmul.vrclass; defvar IdxVreg = idx_lmul.vrclass; defvar Order = !if(Ordered, "O", "U"); let VLMul = val_lmul.value in { - foreach nf = NFSet.L in { - defvar ValVreg = SegRegClass.RC; + foreach nf = NFSet(val_lmul) in { + defvar ValVreg = SegRegClass(val_lmul, nf); def nf # "EI" # idx_eew # "_V_" # IdxLInfo # "_" # ValLInfo : VPseudoISegStoreNoMask, @@ -4706,7 +4705,7 @@ multiclass VPatBinaryV_VV_INT_E vtilist> { foreach vti = vtilist in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(vti); defm : VPatBinaryTA.ret; + defvar emul_str = octuple_to_str(octuple_emul); defvar ivti = !cast("VI" # eew # emul_str); defvar inst = instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; defm : VPatBinaryTA.Vti; + defvar ivti = GetIntVTypeInfo(fvti); defm : VPatConversionTA.Vti; + defvar ivti = GetIntVTypeInfo(fvti); defm : VPatConversionTA.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); defm : VPatConversionTA.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); defm : VPatConversionTA; foreach lmul = MxList in { - foreach nf = NFSet.L in { - defvar vreg = SegRegClass.RC; + foreach nf = NFSet(lmul) in { + defvar vreg = SegRegClass(lmul, nf); let hasSideEffects = 0, mayLoad = 0, mayStore = 1, isCodeGenOnly = 1, Size = !mul(4, !sub(!mul(nf, 2), 1)) in { def "PseudoVSPILL" # nf # "_" # lmul.MX : diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td @@ -376,7 +376,7 @@ multiclass VPatConvertI2FPSDNode_V { foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(fvti); def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1))), (!cast(instruction_name#"_"#fvti.LMul.MX) ivti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; @@ -386,7 +386,7 @@ multiclass VPatConvertFP2ISDNode_V { foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(fvti); def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))), (!cast(instruction_name#"_"#ivti.LMul.MX) fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW)>; @@ -408,7 +408,7 @@ string instruction_name> { foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))), (!cast(instruction_name#"_"#fvti.LMul.MX) fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; @@ -419,7 +419,7 @@ string instruction_name> { foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1))), (!cast(instruction_name#"_"#fvti.LMul.MX) iwti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td @@ -976,7 +976,7 @@ multiclass VPatConvertFP2IVL_V { foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(fvti); def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), (fvti.Mask V0), VLOpFrag)), @@ -988,7 +988,7 @@ multiclass VPatConvertFP2I_RM_VL_V { foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(fvti); def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), (fvti.Mask V0), (XLenVT timm:$frm), VLOpFrag)), @@ -1001,7 +1001,7 @@ multiclass VPatConvertI2FPVL_V { foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(fvti); def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), (ivti.Mask V0), VLOpFrag)), @@ -1013,7 +1013,7 @@ multiclass VPatConvertI2FP_RM_VL_V { foreach fvti = AllFloatVectors in { - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(fvti); def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), (ivti.Mask V0), (XLenVT timm:$frm), VLOpFrag)), @@ -1028,7 +1028,7 @@ multiclass VPatWConvertFP2IVL_V { foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), (fvti.Mask V0), VLOpFrag)), @@ -1041,7 +1041,7 @@ multiclass VPatWConvertFP2I_RM_VL_V { foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1), (fvti.Mask V0), (XLenVT timm:$frm), VLOpFrag)), @@ -1113,7 +1113,7 @@ string instruction_name> { foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), (iwti.Mask V0), VLOpFrag)), @@ -1126,7 +1126,7 @@ multiclass VPatNConvertI2FP_RM_VL_W { foreach fvtiToFWti = AllWidenableFloatVectors in { defvar fvti = fvtiToFWti.Vti; - defvar iwti = GetIntVTypeInfo.Vti; + defvar iwti = GetIntVTypeInfo(fvtiToFWti.Wti); def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1), (iwti.Mask V0), (XLenVT timm:$frm), VLOpFrag)), @@ -2265,7 +2265,7 @@ defvar octuple_lmul = vlmul.octuple; defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { - defvar emul_str = octuple_to_str.ret; + defvar emul_str = octuple_to_str(octuple_emul); defvar ivti = !cast("VI16" # emul_str); defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; @@ -2303,7 +2303,7 @@ (!cast("PseudoVFMV_S_"#vti.ScalarSuffix#"_"#vti.LMul.MX) vti.RegClass:$merge, (vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>; - defvar ivti = GetIntVTypeInfo.Vti; + defvar ivti = GetIntVTypeInfo(vti); def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2, @@ -2335,7 +2335,7 @@ defvar octuple_lmul = vlmul.octuple; defvar octuple_emul = !srl(!mul(octuple_lmul, 16), vti.Log2SEW); if !and(!ge(octuple_emul, 1), !le(octuple_emul, 64)) then { - defvar emul_str = octuple_to_str.ret; + defvar emul_str = octuple_to_str(octuple_emul); defvar ivti = !cast("VI16" # emul_str); defvar inst = "PseudoVRGATHEREI16_VV_" # vti.LMul.MX # "_E" # vti.SEW # "_" # emul_str; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -18,24 +18,24 @@ // Used for widening floating-point Reduction as it doesn't contain MF8. defvar SchedMxListFWRed = SchedMxListF; -class SchedSEWSet { - list val = !cond(!eq(mx, "M1"): [8, 16, 32, 64], - !eq(mx, "M2"): [8, 16, 32, 64], - !eq(mx, "M4"): [8, 16, 32, 64], - !eq(mx, "M8"): [8, 16, 32, 64], - !eq(mx, "MF2"): [8, 16, 32], - !eq(mx, "MF4"): [8, 16], - !eq(mx, "MF8"): [8]); +function SchedSEWSet(string mx): list { + return !cond(!eq(mx, "M1"): [8, 16, 32, 64], + !eq(mx, "M2"): [8, 16, 32, 64], + !eq(mx, "M4"): [8, 16, 32, 64], + !eq(mx, "M8"): [8, 16, 32, 64], + !eq(mx, "MF2"): [8, 16, 32], + !eq(mx, "MF4"): [8, 16], + !eq(mx, "MF8"): [8]); } // For floating-point instructions, SEW won't be 8. -class SchedSEWSetF { - list val = !cond(!eq(mx, "M1"): [16, 32, 64], - !eq(mx, "M2"): [16, 32, 64], - !eq(mx, "M4"): [16, 32, 64], - !eq(mx, "M8"): [16, 32, 64], - !eq(mx, "MF2"): [16, 32], - !eq(mx, "MF4"): [16]); +function SchedSEWSetF(string mx): list { + return !cond(!eq(mx, "M1"): [16, 32, 64], + !eq(mx, "M2"): [16, 32, 64], + !eq(mx, "M4"): [16, 32, 64], + !eq(mx, "M8"): [16, 32, 64], + !eq(mx, "MF2"): [16, 32], + !eq(mx, "MF4"): [16]); } // Define multiclasses to define SchedWrite, SchedRead, WriteRes, and @@ -79,14 +79,14 @@ multiclass LMULSEWSchedWritesImpl MxList, bit isF = 0> { def name # "_WorstCase" : SchedWrite; foreach mx = MxList in { - foreach sew = !if(isF, SchedSEWSetF.val, SchedSEWSet.val) in + foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in def name # "_" # mx # "_E" # sew : SchedWrite; } } multiclass LMULSEWSchedReadsImpl MxList, bit isF = 0> { def name # "_WorstCase" : SchedRead; foreach mx = MxList in { - foreach sew = !if(isF, SchedSEWSetF.val, SchedSEWSet.val) in + foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in def name # "_" # mx # "_E" # sew : SchedRead; } } @@ -94,7 +94,7 @@ bit isF = 0> { def : WriteRes(name # "_WorstCase"), resources>; foreach mx = !if(isF, SchedMxListF, SchedMxList) in { - foreach sew = !if(isF, SchedSEWSetF.val, SchedSEWSet.val) in + foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in def : WriteRes(name # "_" # mx # "_E" # sew), resources>; } } @@ -102,7 +102,7 @@ bit isF = 0> { def : ReadAdvance(name # "_WorstCase"), val, writes>; foreach mx = !if(isF, SchedMxListF, SchedMxList) in { - foreach sew = !if(isF, SchedSEWSetF.val, SchedSEWSet.val) in + foreach sew = !if(isF, SchedSEWSetF(mx), SchedSEWSet(mx)) in def : ReadAdvance(name # "_" # mx # "_E" # sew), val, writes>; } }