Index: mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_0_permute.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/concatenate_dim_1_permute.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test.mtx" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/dense_output_f16.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/lit.local.cfg =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/lit.local.cfg +++ mlir/test/Integration/Dialect/SparseTensor/CPU/lit.local.cfg @@ -9,35 +9,7 @@ if config.mlir_run_arm_sve_tests: config.substitutions.append(('%ENABLE_VLA', 'true')) config.substitutions.append(('%VLA_ARCH_ATTR_OPTIONS', '--march=aarch64 --mattr="+sve"')) - lli_cmd = 'lli' - if config.arm_emulator_lli_executable: - lli_cmd = config.arm_emulator_lli_executable - - if config.arm_emulator_utils_lib_dir: - config.substitutions.append(('%mlir_native_utils_lib_dir', config.arm_emulator_utils_lib_dir)) - else: - config.substitutions.append(('%mlir_native_utils_lib_dir', config.mlir_lib_dir)) - - if config.arm_emulator_executable: - if not config.arm_emulator_lli_executable: - # Top-level lit config adds llvm_tools_dir to PATH but this is lost - # when running under an emulator. If the user didn't specify an lli - # executable, use absolute path %llvm_tools_dir/lli. - # TODO(c-rhodes): This logic is duplicated across several Lit files - # and needs refactoring. - lli_cmd = llvm_config.use_llvm_tool('lli', search_env='LLI', required=True, - search_paths=[config.llvm_tools_dir], - use_installed=False) - # Run test in emulator (qemu or armie). - emulation_cmd = config.arm_emulator_executable - if config.arm_emulator_options: - emulation_cmd = emulation_cmd + ' ' + config.arm_emulator_options - emulation_cmd = emulation_cmd + ' ' + lli_cmd - config.substitutions.append(('%lli', emulation_cmd)) - else: - config.substitutions.append(('%lli', lli_cmd)) else: config.substitutions.append(('%ENABLE_VLA', 'false')) config.substitutions.append(('%VLA_ARCH_ATTR_OPTIONS', '')) - config.substitutions.append(('%lli', 'lli')) config.substitutions.append(('%mlir_native_utils_lib_dir', config.mlir_lib_dir)) Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_abs.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_binary.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cast.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cast.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_cast.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_dim.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_dim.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_dim.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_foreach.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_foreach.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_codegen_foreach.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_collapse_shape.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex32.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex64.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_complex_ops.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_constant_to_sparse_tensor.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_1d_nwc_wcf.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA enable-index-reduction=true" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-index-reduction=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_2d_nhwc_hwcf.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA enable-index-reduction=true" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA enable-index-reduction=true" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conv_3d_ndhwc_dhwcf.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA enable-index-reduction=true" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_dyn.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 reassociate-fp-reductions=true enable-index-optimizations=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_element.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_element.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_element.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_ptr.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 reassociate-fp-reductions=true enable-index-optimizations=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2dense.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2dense.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2dense.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2sparse.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2sparse.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_conversion_sparse2sparse.mlir @@ -19,7 +19,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_coo_test.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dot.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand.mlir @@ -17,7 +17,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_expand_shape.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_io.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_io.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_file_io.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/wide.mtx" TENSOR1="" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_filter_conv2d.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_flatten.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_flatten.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_flatten.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test.tns" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index_dense.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index_dense.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_index_dense.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_1d.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_2d.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_insert_3d.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matmul.mlir @@ -26,7 +26,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matrix_ops.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_matvec.mlir @@ -27,7 +27,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/wide.mtx" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_mttkrp.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_mttkrp.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_mttkrp.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/mttkrp_b.tns" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_mult_elt.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_reduction.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_out_simple.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test.mtx" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_pack.mlir @@ -11,7 +11,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_quantized_matmul.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_quantized_matmul.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_quantized_matmul.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_re_im.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reduce_custom.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 reassociate-fp-reductions=true enable-index-optimizations=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reductions.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reductions.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_reductions.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_push_back.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_push_back.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_push_back.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort.mlir @@ -10,7 +10,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort_coo.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort_coo.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_rewrite_sort_coo.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_matmul.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test.mtx" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sampled_mm_fusion.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scale.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_scf_nested.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_select.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sign.mlir @@ -14,7 +14,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_storage.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test_symmetric.mtx" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_c32.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_c32.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_c32.mlir @@ -20,7 +20,7 @@ // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" // REDEFINE: %{run} = TENSOR0="%mlir_src_dir/test/Integration/data/test_symmetric_complex.mtx" \ -// REDEFINE: %lli \ +// REDEFINE: %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_f16.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_f16.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sum_f16.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tanh.mlir @@ -21,7 +21,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 reassociate-fp-reductions=true enable-index-optimizations=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_mul.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_tensor_ops.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_transpose_coo.mlir @@ -19,7 +19,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_unary.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false vl=4 enable-buffer-initialization=true reassociate-fp-reductions=true enable-index-optimizations=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir =================================================================== --- mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir +++ mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_vector_ops.mlir @@ -18,7 +18,7 @@ // Do the same run, but now with direct IR generation and, if available, VLA // vectorization. // REDEFINE: %{option} = "enable-runtime-library=false enable-buffer-initialization=true vl=4 reassociate-fp-reductions=true enable-index-optimizations=true enable-arm-sve=%ENABLE_VLA" -// REDEFINE: %{run} = %lli \ +// REDEFINE: %{run} = %lli_host_or_aarch64_cmd \ // REDEFINE: --entry-function=entry_lli \ // REDEFINE: --extra-module=%S/Inputs/main_for_lli.ll \ // REDEFINE: %VLA_ARCH_ATTR_OPTIONS \ Index: mlir/test/Integration/Dialect/Vector/CPU/ArmSME/lit.local.cfg =================================================================== --- mlir/test/Integration/Dialect/Vector/CPU/ArmSME/lit.local.cfg +++ mlir/test/Integration/Dialect/Vector/CPU/ArmSME/lit.local.cfg @@ -1,5 +1,4 @@ import sys -from lit.llvm import llvm_config # ArmSME tests must be enabled via build flag. if not config.mlir_run_arm_sme_tests: @@ -8,29 +7,3 @@ # No JIT on win32. if sys.platform == 'win32': config.unsupported = True - -lli_cmd = 'lli' -if config.arm_emulator_lli_executable: - lli_cmd = config.arm_emulator_lli_executable - -config.substitutions.append(('%mlir_native_utils_lib_dir', - config.arm_emulator_utils_lib_dir or config.mlir_lib_dir)) - -if config.arm_emulator_executable: - if not config.arm_emulator_lli_executable: - # Top-level lit config adds llvm_tools_dir to PATH but this is lost - # when running under an emulator. If the user didn't specify an lli - # executable, use absolute path %llvm_tools_dir/lli. - # TODO(c-rhodes): This logic is duplicated across several Lit files and - # needs refactoring. - lli_cmd = llvm_config.use_llvm_tool('lli', search_env='LLI', required=True, - search_paths=[config.llvm_tools_dir], - use_installed=False) - # Run test in emulator (QEMU) - emulation_cmd = config.arm_emulator_executable - if config.arm_emulator_options: - emulation_cmd = emulation_cmd + ' ' + config.arm_emulator_options - emulation_cmd = emulation_cmd + ' ' + lli_cmd - config.substitutions.append(('%lli', emulation_cmd)) -else: - config.substitutions.append(('%lli', lli_cmd)) Index: mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir =================================================================== --- mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir +++ mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-ssve.mlir @@ -1,6 +1,6 @@ // RUN: mlir-opt %s -test-lower-to-llvm | \ // RUN: mlir-translate -mlir-to-llvmir | \ -// RUN: %lli --march=aarch64 --mattr="+sve,+sme" \ +// RUN: %lli_aarch64_cmd --march=aarch64 --mattr="+sve,+sme" \ // RUN: -force-streaming-compatible-sve \ // RUN: --entry-function=entry \ // RUN: --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \ Index: mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg =================================================================== --- mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg +++ mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/lit.local.cfg @@ -1,5 +1,4 @@ import sys -from lit.llvm import llvm_config # ArmSVE tests must be enabled via build flag. if not config.mlir_run_arm_sve_tests: @@ -8,29 +7,3 @@ # No JIT on win32. if sys.platform == 'win32': config.unsupported = True - -lli_cmd = 'lli' -if config.arm_emulator_lli_executable: - lli_cmd = config.arm_emulator_lli_executable - -config.substitutions.append(('%mlir_native_utils_lib_dir', - config.arm_emulator_utils_lib_dir or config.mlir_lib_dir)) - -if config.arm_emulator_executable: - if not config.arm_emulator_lli_executable: - # Top-level lit config adds llvm_tools_dir to PATH but this is lost - # when running under an emulator. If the user didn't specify an lli - # executable, use absolute path %llvm_tools_dir/lli. - # TODO(c-rhodes): This logic is duplicated across several Lit files and - # needs refactoring. - lli_cmd = llvm_config.use_llvm_tool('lli', search_env='LLI', required=True, - search_paths=[config.llvm_tools_dir], - use_installed=False) - # Run test in emulator (qemu or armie) - emulation_cmd = config.arm_emulator_executable - if config.arm_emulator_options: - emulation_cmd = emulation_cmd + ' ' + config.arm_emulator_options - emulation_cmd = emulation_cmd + ' ' + lli_cmd - config.substitutions.append(('%lli', emulation_cmd)) -else: - config.substitutions.append(('%lli', lli_cmd)) Index: mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir =================================================================== --- mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir +++ mlir/test/Integration/Dialect/Vector/CPU/ArmSVE/test-sve.mlir @@ -1,6 +1,6 @@ // RUN: mlir-opt %s -lower-affine -convert-scf-to-cf -convert-vector-to-llvm="enable-arm-sve" -finalize-memref-to-llvm -convert-func-to-llvm -convert-arith-to-llvm -canonicalize | \ // RUN: mlir-translate -mlir-to-llvmir | \ -// RUN: %lli --entry-function=entry --march=aarch64 --mattr="+sve" --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \ +// RUN: %lli_aarch64_cmd --entry-function=entry --march=aarch64 --mattr="+sve" --dlopen=%mlir_native_utils_lib_dir/libmlir_c_runner_utils%shlibext | \ // RUN: FileCheck %s // Note: To run this test, your CPU must support SVE Index: mlir/test/Integration/lit.local.cfg =================================================================== --- mlir/test/Integration/lit.local.cfg +++ mlir/test/Integration/lit.local.cfg @@ -1,2 +1,44 @@ +from lit.llvm import llvm_config + if not config.mlir_include_integration_tests: config.unsupported = True + +def configure_aarch64_lli_cmd(): + lli_cmd = 'lli' + + # NOTE: If the SVE tests are disabled and the SME tests are enabled to run + # under emulation, the SVE specific RUN lines in the SparseTensor tests + # will run under emulation. + if not (config.mlir_run_arm_sve_tests or config.mlir_run_arm_sme_tests): + return lli_cmd + + config.substitutions.append(('%mlir_native_utils_lib_dir', + config.arm_emulator_utils_lib_dir or config.mlir_lib_dir)) + + if config.arm_emulator_executable: + if config.arm_emulator_lli_executable: + lli_cmd = config.arm_emulator_lli_executable + else: + # Top-level lit config adds llvm_tools_dir to PATH but this is lost + # when running under an emulator. If the user didn't specify an lli + # executable, use absolute path %llvm_tools_dir/lli. + lli_cmd = llvm_config.use_llvm_tool( + 'lli', search_env='LLI', required=True, + search_paths=[config.llvm_tools_dir], use_installed=False + ) + + # Run test in emulator (qemu or armie) + emulation_cmd = f'{config.arm_emulator_executable} {config.arm_emulator_options}' + lli_cmd = f'{emulation_cmd} {lli_cmd}' + + return lli_cmd + +aarch64_lli_cmd = configure_aarch64_lli_cmd() + +# These two substitutions are equivalent but '%lli_aarch64_cmd' should +# be used for integration tests that run exclusively on AArch64 +# (ArmSVE, ArmSME), and '%lli_host_or_aarch64_cmd' should be used for +# tests that may run on the host OR AArch64, such as the SparseTensor +# tests which have target-specific (SVE) and target-agnostic codepaths. +config.substitutions.append(('%lli_aarch64_cmd', aarch64_lli_cmd)) +config.substitutions.append(('%lli_host_or_aarch64_cmd', aarch64_lli_cmd))