diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -913,35 +913,28 @@ return Error::success(); } -static const char *ImpliedExtsF[] = {"zicsr"}; static const char *ImpliedExtsD[] = {"f"}; +static const char *ImpliedExtsF[] = {"zicsr"}; static const char *ImpliedExtsV[] = {"zvl128b", "zve64d", "f", "d"}; -static const char *ImpliedExtsZfhmin[] = {"f"}; +static const char *ImpliedExtsXTHeadVdot[] = {"v"}; +static const char *ImpliedExtsXsfvcp[] = {"zve32x"}; +static const char *ImpliedExtsZcb[] = {"zca"}; +static const char *ImpliedExtsZdinx[] = {"zfinx"}; +static const char *ImpliedExtsZfa[] = {"f"}; static const char *ImpliedExtsZfh[] = {"f"}; +static const char *ImpliedExtsZfhmin[] = {"f"}; static const char *ImpliedExtsZfinx[] = {"zicsr"}; -static const char *ImpliedExtsZdinx[] = {"zfinx"}; -static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; static const char *ImpliedExtsZhinx[] = {"zfinx"}; -static const char *ImpliedExtsZve64d[] = {"zve64f"}; -static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; -static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; -static const char *ImpliedExtsZve32f[] = {"zve32x"}; -static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"}; -static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"}; -static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"}; -static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"}; -static const char *ImpliedExtsZvl8192b[] = {"zvl4096b"}; -static const char *ImpliedExtsZvl4096b[] = {"zvl2048b"}; -static const char *ImpliedExtsZvl2048b[] = {"zvl1024b"}; -static const char *ImpliedExtsZvl1024b[] = {"zvl512b"}; -static const char *ImpliedExtsZvl512b[] = {"zvl256b"}; -static const char *ImpliedExtsZvl256b[] = {"zvl128b"}; -static const char *ImpliedExtsZvl128b[] = {"zvl64b"}; -static const char *ImpliedExtsZvl64b[] = {"zvl32b"}; +static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"}; static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"}; static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; +static const char *ImpliedExtsZve32f[] = {"zve32x"}; +static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"}; +static const char *ImpliedExtsZve64d[] = {"zve64f"}; +static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; +static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb", "zvkt"}; @@ -950,10 +943,17 @@ static const char *ImpliedExtsZvks[] = {"zvbb", "zvbc", "zvksed", "zvksh", "zvkt"}; static const char *ImpliedExtsZvksg[] = {"zvks", "zvkg"}; -static const char *ImpliedExtsXsfvcp[] = {"zve32x"}; -static const char *ImpliedExtsXTHeadVdot[] = {"v"}; -static const char *ImpliedExtsZcb[] = {"zca"}; -static const char *ImpliedExtsZfa[] = {"f"}; +static const char *ImpliedExtsZvl1024b[] = {"zvl512b"}; +static const char *ImpliedExtsZvl128b[] = {"zvl64b"}; +static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"}; +static const char *ImpliedExtsZvl2048b[] = {"zvl1024b"}; +static const char *ImpliedExtsZvl256b[] = {"zvl128b"}; +static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"}; +static const char *ImpliedExtsZvl4096b[] = {"zvl2048b"}; +static const char *ImpliedExtsZvl512b[] = {"zvl256b"}; +static const char *ImpliedExtsZvl64b[] = {"zvl32b"}; +static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"}; +static const char *ImpliedExtsZvl8192b[] = {"zvl4096b"}; struct ImpliedExtsEntry { StringLiteral Name; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -497,10 +497,10 @@ def FeatureStdExtZvkg : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true", - "'Zvkg' (Vector GCM instructions for Cryptography.)">; + "'Zvkg' (Vector GCM instructions for Cryptography)">; def HasStdExtZvkg : Predicate<"Subtarget->hasStdExtZvkg()">, AssemblerPredicate<(all_of FeatureStdExtZvkg), - "'Zvkg' (Vector GCM instructions for Cryptography.)">; + "'Zvkg' (Vector GCM instructions for Cryptography)">; def FeatureStdExtZvkn : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true", @@ -521,15 +521,15 @@ def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", - "'Zvknha' (Vector SHA-2. (SHA-256 only))">; + "'Zvknha' (Vector SHA-2 (SHA-256 only))">; def FeatureStdExtZvknhb : SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true", - "'Zvknhb' (Vector SHA-2. (SHA-256 and SHA-512))", + "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", [FeatureStdExtZvknha]>; def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, AssemblerPredicate<(all_of FeatureStdExtZvknha), - "'Zvknha' (Vector SHA-2. (SHA-256 only))">; + "'Zvknha' (Vector SHA-2 (SHA-256 only))">; def FeatureStdExtZvks : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true", @@ -538,10 +538,10 @@ def FeatureStdExtZvksed : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true", - "'Zvksed' (SM4 Block Cipher Instructions.)">; + "'Zvksed' (SM4 Block Cipher Instructions)">; def HasStdExtZvksed : Predicate<"Subtarget->hasStdExtZvksed()">, AssemblerPredicate<(all_of FeatureStdExtZvksed), - "'Zvksed' (SM4 Block Cipher Instructions.)">; + "'Zvksed' (SM4 Block Cipher Instructions)">; def FeatureStdExtZvksg : SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true", @@ -550,14 +550,14 @@ def FeatureStdExtZvksh : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true", - "'Zvksh' (SM3 Hash Function Instructions.)">; + "'Zvksh' (SM3 Hash Function Instructions)">; def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, AssemblerPredicate<(all_of FeatureStdExtZvksh), - "'Zvksh' (SM3 Hash Function Instructions.)">; + "'Zvksh' (SM3 Hash Function Instructions)">; def FeatureStdExtZvkt : SubtargetFeature<"experimental-zvkt", "HasStdExtZvkt", "true", - "'Zvkt' (Vector Data-Independent Execution Latency )">; + "'Zvkt' (Vector Data-Independent Execution Latency)">; def FeatureStdExtZicond : SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true", diff --git a/llvm/test/MC/RISCV/rvv/zvkg.s b/llvm/test/MC/RISCV/rvv/zvkg.s --- a/llvm/test/MC/RISCV/rvv/zvkg.s +++ b/llvm/test/MC/RISCV/rvv/zvkg.s @@ -11,11 +11,11 @@ vghsh.vv v10, v9, v8 # CHECK-INST: vghsh.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xb2] -# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography){{$}} # CHECK-UNKNOWN: 77 25 94 b2 vgmul.vv v10, v9 # CHECK-INST: vgmul.vv v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x98,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography){{$}} # CHECK-UNKNOWN: 77 a5 98 a2 diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s --- a/llvm/test/MC/RISCV/rvv/zvknh.s +++ b/llvm/test/MC/RISCV/rvv/zvknh.s @@ -19,16 +19,16 @@ # CHECK-INST: vsha2ms.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xb6] # CHECK-UNKNOWN: 77 25 94 b6 -# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2 (SHA-256 only)){{$}} vsha2ch.vv v10, v9, v8 # CHECK-INST: vsha2ch.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xba] # CHECK-UNKNOWN: 77 25 94 ba -# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2 (SHA-256 only)){{$}} vsha2cl.vv v10, v9, v8 # CHECK-INST: vsha2cl.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xbe] # CHECK-UNKNOWN: 77 25 94 be -# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2. (SHA-256 only)){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2 (SHA-256 only)){{$}} diff --git a/llvm/test/MC/RISCV/rvv/zvksed.s b/llvm/test/MC/RISCV/rvv/zvksed.s --- a/llvm/test/MC/RISCV/rvv/zvksed.s +++ b/llvm/test/MC/RISCV/rvv/zvksed.s @@ -11,17 +11,17 @@ vsm4k.vi v10, v9, 7 # CHECK-INST: vsm4k.vi v10, v9, 7 # CHECK-ENCODING: [0x77,0xa5,0x93,0x86] -# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} # CHECK-UNKNOWN: 77 a5 93 86 vsm4r.vv v10, v9 # CHECK-INST: vsm4r.vv v10, v9 # CHECK-ENCODING: [0x77,0x25,0x98,0xa2] -# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} # CHECK-UNKNOWN: 77 25 98 a2 vsm4r.vs v10, v9 # CHECK-INST: vsm4r.vs v10, v9 # CHECK-ENCODING: [0x77,0x25,0x98,0xa6] -# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} # CHECK-UNKNOWN: 77 25 98 a6 diff --git a/llvm/test/MC/RISCV/rvv/zvksh.s b/llvm/test/MC/RISCV/rvv/zvksh.s --- a/llvm/test/MC/RISCV/rvv/zvksh.s +++ b/llvm/test/MC/RISCV/rvv/zvksh.s @@ -11,11 +11,11 @@ vsm3c.vi v10, v9, 7 # CHECK-INST: vsm3c.vi v10, v9, 7 # CHECK-ENCODING: [0x77,0xa5,0x93,0xae] -# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions){{$}} # CHECK-UNKNOWN: 77 a5 93 ae vsm3me.vv v10, v9, v8 # CHECK-INST: vsm3me.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0x82] -# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions){{$}} # CHECK-UNKNOWN: 77 25 94 82