diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -85,6 +85,18 @@ } } +static bool isVSlideInstr(const MachineInstr &MI) { + switch (getRVVMCOpcode(MI.getOpcode())) { + default: + return false; + case RISCV::VSLIDEDOWN_VX: + case RISCV::VSLIDEDOWN_VI: + case RISCV::VSLIDEUP_VX: + case RISCV::VSLIDEUP_VI: + return true; + } +} + /// Get the EEW for a load or store instruction. Return std::nullopt if MI is /// not a load or store which ignores SEW. static std::optional getEEWForLoadStore(const MachineInstr &MI) { @@ -818,6 +830,11 @@ .addImm(Info.encodeVTYPE()); } +static bool isLMUL1OrSmaller(RISCVII::VLMUL LMUL) { + auto [LMul, Fractional] = RISCVVType::decodeVLMUL(LMUL); + return Fractional || LMul == 1; +} + /// Return true if a VSETVLI is required to transition from CurInfo to Require /// before MI. bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI, @@ -845,6 +862,27 @@ } } + // A slidedown/slideup with a VL of 1 whose destination is an IMPLICIT_DEF + // can use any VL/SEW combination which writes at least the first element. + // Notes: + // * VL=1 is special only because we have existing support for zero vs + // non-zero VL. We could generalize this if we had a VL > C predicate. + // * The LMUL1 restriction is for machines whose latency may depend on VL. + // * As above, this is only legal for IMPLICIT_DEF, not TA. + if (isVSlideInstr(MI) && Require.hasAVLImm() && Require.getAVLImm() == 1 && + isLMUL1OrSmaller(CurInfo.getVLMUL())) { + auto *VRegDef = MRI->getVRegDef(MI.getOperand(1).getReg()); + if (VRegDef && VRegDef->isImplicitDef() && + CurInfo.getSEW() >= Require.getSEW()) { + Used.VLAny = false; + Used.VLZeroness = true; + Used.SEW = false; + Used.LMUL = false; + Used.SEWLMULRatio = false; + Used.TailPolicy = false; + } + } + if (CurInfo.isCompatible(Used, Require)) return false; diff --git a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll --- a/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll @@ -10,7 +10,6 @@ ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -28,7 +27,6 @@ ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -46,7 +44,6 @@ ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -64,7 +61,6 @@ ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-reverse.ll @@ -16,10 +16,8 @@ ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-NEXT: vmv.x.s a0, v8 -; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vfirst.m a1, v0 ; CHECK-NEXT: seqz a1, a1 ; CHECK-NEXT: vmv.v.x v8, a1 @@ -41,9 +39,9 @@ ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-NEXT: addi a0, sp, 14 +; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; CHECK-NEXT: vse8.v v9, (a0) ; CHECK-NEXT: vslidedown.vi v9, v8, 2 ; CHECK-NEXT: addi a0, sp, 13 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll @@ -59,9 +59,9 @@ ; LMULMAX1-RV64-NEXT: vmax.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x i16>, ptr %x diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll @@ -30,7 +30,6 @@ ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -48,7 +47,6 @@ ; CHECK-NEXT: vmseq.vi v0, v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll @@ -248,7 +248,6 @@ ; LMULMAX1: # %bb.0: ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vlm.v v8, (a0) -; LMULMAX1-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX1-NEXT: vslidedown.vi v8, v8, 1 ; LMULMAX1-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; LMULMAX1-NEXT: vsm.v v8, (a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll @@ -9,7 +9,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -23,7 +22,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -37,7 +35,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -74,7 +71,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret @@ -88,7 +84,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret @@ -252,7 +247,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -266,7 +260,6 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -281,7 +274,6 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vadd.vv v8, v8, v8 -; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret @@ -297,10 +289,10 @@ ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vadd.vv v8, v8, v8 -; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vslidedown.vx v8, v8, a1 ; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a1, 32 +; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: ret @@ -310,7 +302,6 @@ ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vadd.vv v8, v8, v8 -; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vslidedown.vx v8, v8, a1 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret @@ -326,7 +317,6 @@ ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret @@ -342,7 +332,6 @@ ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret @@ -358,7 +347,6 @@ ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a1 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret @@ -529,8 +517,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vle8.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vse8.v v8, (a1) ; CHECK-NEXT: ret %a = load <16 x i8>, ptr %x @@ -544,8 +532,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vle16.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 7 +; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: vse16.v v8, (a1) ; CHECK-NEXT: ret %a = load <8 x i16>, ptr %x @@ -559,8 +547,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 2 +; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: ret %a = load <4 x i32>, ptr %x @@ -575,9 +563,9 @@ ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vle64.v v8, (a0) -; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: li a0, 32 +; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsrl.vx v9, v8, a0 ; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: vmv.x.s a2, v8 @@ -589,8 +577,8 @@ ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vle64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 1 +; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: ret %a = load <2 x i64>, ptr %x @@ -604,8 +592,8 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vle64.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 1 +; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: ret %a = load <2 x double>, ptr %x @@ -627,7 +615,6 @@ ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vadd.vi v8, v8, 13 -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret @@ -650,7 +637,6 @@ ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vrsub.vi v8, v8, 13 -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret @@ -665,7 +651,6 @@ ; RV32NOM-NEXT: li a0, 13 ; RV32NOM-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32NOM-NEXT: vmul.vx v8, v8, a0 -; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32NOM-NEXT: vslidedown.vi v8, v8, 2 ; RV32NOM-NEXT: vmv.x.s a0, v8 ; RV32NOM-NEXT: ret @@ -684,7 +669,6 @@ ; RV64-NEXT: li a0, 13 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vmul.vx v8, v8, a0 -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret @@ -712,7 +696,6 @@ ; RV32NOM-NEXT: vsra.vv v9, v8, v11 ; RV32NOM-NEXT: vsrl.vi v8, v8, 31 ; RV32NOM-NEXT: vadd.vv v8, v9, v8 -; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32NOM-NEXT: vslidedown.vi v8, v8, 2 ; RV32NOM-NEXT: vmv.x.s a0, v8 ; RV32NOM-NEXT: ret @@ -748,7 +731,6 @@ ; RV64-NEXT: vsra.vv v8, v8, v11 ; RV64-NEXT: vsrl.vi v9, v8, 31 ; RV64-NEXT: vadd.vv v8, v8, v9 -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret @@ -765,7 +747,6 @@ ; RV32NOM-NEXT: lui a0, 322639 ; RV32NOM-NEXT: addi a0, a0, -945 ; RV32NOM-NEXT: vmulhu.vx v8, v8, a0 -; RV32NOM-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32NOM-NEXT: vslidedown.vi v8, v8, 2 ; RV32NOM-NEXT: vmv.x.s a0, v8 ; RV32NOM-NEXT: srli a0, a0, 2 @@ -790,7 +771,6 @@ ; RV64-NEXT: addiw a0, a0, -945 ; RV64-NEXT: vmulhu.vx v8, v8, a0 ; RV64-NEXT: vsrl.vi v8, v8, 2 -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll @@ -47,9 +47,9 @@ ; LMULMAX1-RV64-NEXT: vfadd.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -130,9 +130,9 @@ ; LMULMAX1-RV64-NEXT: vfsub.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -213,9 +213,9 @@ ; LMULMAX1-RV64-NEXT: vfmul.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -296,9 +296,9 @@ ; LMULMAX1-RV64-NEXT: vfdiv.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -375,9 +375,9 @@ ; LMULMAX1-RV64-NEXT: vfneg.v v8, v8 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -450,9 +450,9 @@ ; LMULMAX1-RV64-NEXT: vfabs.v v8, v8 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -532,9 +532,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -616,9 +616,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnj.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -701,9 +701,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnjn.vv v8, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -776,9 +776,9 @@ ; LMULMAX1-RV32-NEXT: vle16.v v9, (a0) ; LMULMAX1-RV32-NEXT: vfncvt.f.f.w v10, v8 ; LMULMAX1-RV32-NEXT: vfsgnjn.vv v8, v9, v10 -; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1-RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1-RV32-NEXT: addi a1, a0, 4 +; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1-RV32-NEXT: vse16.v v9, (a1) ; LMULMAX1-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) @@ -792,9 +792,9 @@ ; LMULMAX1-RV64-NEXT: vle32.v v9, (a1) ; LMULMAX1-RV64-NEXT: vfncvt.f.f.w v10, v9 ; LMULMAX1-RV64-NEXT: vfsgnjn.vv v8, v8, v10 -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1-RV64-NEXT: addi a1, a0, 4 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1-RV64-NEXT: vse16.v v9, (a1) ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) @@ -865,9 +865,9 @@ ; LMULMAX1-RV64-NEXT: vfsqrt.v v8, v8 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -951,9 +951,9 @@ ; LMULMAX1-RV64-NEXT: vfmacc.vv v10, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -1047,9 +1047,9 @@ ; LMULMAX1-RV64-NEXT: vfmsac.vv v10, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -1878,9 +1878,9 @@ ; LMULMAX1-RV64-NEXT: vfadd.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -1960,9 +1960,9 @@ ; LMULMAX1-RV64-NEXT: vfadd.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2042,9 +2042,9 @@ ; LMULMAX1-RV64-NEXT: vfsub.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2124,9 +2124,9 @@ ; LMULMAX1-RV64-NEXT: vfrsub.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2206,9 +2206,9 @@ ; LMULMAX1-RV64-NEXT: vfmul.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2288,9 +2288,9 @@ ; LMULMAX1-RV64-NEXT: vfmul.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2370,9 +2370,9 @@ ; LMULMAX1-RV64-NEXT: vfdiv.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2452,9 +2452,9 @@ ; LMULMAX1-RV64-NEXT: vfrdiv.vf v8, v8, fa0 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2538,9 +2538,9 @@ ; LMULMAX1-RV64-NEXT: vfmacc.vf v9, fa0, v8 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2629,9 +2629,9 @@ ; LMULMAX1-RV64-NEXT: vfmacc.vf v9, fa0, v8 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2721,9 +2721,9 @@ ; LMULMAX1-RV64-NEXT: vfmsac.vf v9, fa0, v8 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v9, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2871,9 +2871,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -2990,9 +2990,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -3113,9 +3113,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -3236,9 +3236,9 @@ ; LMULMAX1-RV64-NEXT: vfsgnj.vv v8, v9, v8, v0.t ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v8, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -3478,9 +3478,9 @@ ; LMULMAX1-RV64-NEXT: vfmacc.vv v10, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x @@ -3574,9 +3574,9 @@ ; LMULMAX1-RV64-NEXT: vfmsac.vv v10, v8, v9 ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse64.v v10, (a0) -; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vslidedown.vi v8, v10, 2 ; LMULMAX1-RV64-NEXT: addi a0, a0, 8 +; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV64-NEXT: ret %a = load <6 x half>, ptr %x diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll @@ -202,7 +202,6 @@ ; RV32-NEXT: fmin.d fa5, fa5, fa3 ; RV32-NEXT: fcvt.w.d a2, fa5, rtz ; RV32-NEXT: and a0, a0, a2 -; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa5, v8 ; RV32-NEXT: feq.d a2, fa5, fa5 @@ -211,7 +210,7 @@ ; RV32-NEXT: fmin.d fa5, fa5, fa3 ; RV32-NEXT: fcvt.w.d a3, fa5, rtz ; RV32-NEXT: and a2, a2, a3 -; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma ; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, tu, ma ; RV32-NEXT: vmv.s.x v8, a0 @@ -233,7 +232,6 @@ ; RV64-NEXT: fmin.d fa5, fa5, fa3 ; RV64-NEXT: fcvt.l.d a2, fa5, rtz ; RV64-NEXT: and a0, a0, a2 -; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 1 ; RV64-NEXT: vfmv.f.s fa5, v8 ; RV64-NEXT: feq.d a2, fa5, fa5 @@ -242,7 +240,7 @@ ; RV64-NEXT: fmin.d fa5, fa5, fa3 ; RV64-NEXT: fcvt.l.d a3, fa5, rtz ; RV64-NEXT: and a2, a2, a3 -; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma ; RV64-NEXT: vmv.v.x v8, a2 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, tu, ma ; RV64-NEXT: vmv.s.x v8, a0 @@ -267,13 +265,12 @@ ; RV32-NEXT: fmax.d fa4, fa4, fa3 ; RV32-NEXT: fmin.d fa4, fa4, fa5 ; RV32-NEXT: fcvt.wu.d a0, fa4, rtz -; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vslidedown.vi v8, v8, 1 ; RV32-NEXT: vfmv.f.s fa4, v8 ; RV32-NEXT: fmax.d fa4, fa4, fa3 ; RV32-NEXT: fmin.d fa5, fa4, fa5 ; RV32-NEXT: fcvt.wu.d a2, fa5, rtz -; RV32-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma ; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vsetvli zero, zero, e8, mf8, tu, ma ; RV32-NEXT: vmv.s.x v8, a0 @@ -291,13 +288,12 @@ ; RV64-NEXT: fmax.d fa4, fa4, fa3 ; RV64-NEXT: fmin.d fa4, fa4, fa5 ; RV64-NEXT: fcvt.lu.d a0, fa4, rtz -; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 1 ; RV64-NEXT: vfmv.f.s fa4, v8 ; RV64-NEXT: fmax.d fa4, fa4, fa3 ; RV64-NEXT: fmin.d fa5, fa4, fa5 ; RV64-NEXT: fcvt.lu.d a2, fa5, rtz -; RV64-NEXT: vsetivli zero, 2, e8, mf8, ta, ma +; RV64-NEXT: vsetvli zero, zero, e8, mf8, ta, ma ; RV64-NEXT: vmv.v.x v8, a2 ; RV64-NEXT: vsetvli zero, zero, e8, mf8, tu, ma ; RV64-NEXT: vmv.s.x v8, a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll @@ -84,9 +84,9 @@ ; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vle32.v v8, (a0) ; LMULMAX8RV32-NEXT: vfcvt.rtz.x.f.v v8, v8 -; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV32-NEXT: addi a0, a1, 8 +; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v9, (a0) ; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v8, (a1) @@ -97,9 +97,9 @@ ; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vle32.v v8, (a0) ; LMULMAX8RV64-NEXT: vfcvt.rtz.x.f.v v8, v8 -; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV64-NEXT: addi a0, a1, 8 +; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vse32.v v9, (a0) ; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX8RV64-NEXT: vse64.v v8, (a1) @@ -110,9 +110,9 @@ ; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1RV32-NEXT: vfcvt.rtz.x.f.v v8, v8 -; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV32-NEXT: addi a0, a1, 8 +; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v8, (a1) @@ -123,9 +123,9 @@ ; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1RV64-NEXT: vfcvt.rtz.x.f.v v8, v8 -; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV64-NEXT: addi a0, a1, 8 +; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1RV64-NEXT: vse64.v v8, (a1) @@ -142,9 +142,9 @@ ; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vle32.v v8, (a0) ; LMULMAX8RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8 -; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV32-NEXT: addi a0, a1, 8 +; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v9, (a0) ; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v8, (a1) @@ -155,9 +155,9 @@ ; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vle32.v v8, (a0) ; LMULMAX8RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8 -; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV64-NEXT: addi a0, a1, 8 +; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vse32.v v9, (a0) ; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX8RV64-NEXT: vse64.v v8, (a1) @@ -168,9 +168,9 @@ ; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1RV32-NEXT: vfcvt.rtz.xu.f.v v8, v8 -; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV32-NEXT: addi a0, a1, 8 +; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v8, (a1) @@ -181,9 +181,9 @@ ; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1RV64-NEXT: vfcvt.rtz.xu.f.v v8, v8 -; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV64-NEXT: addi a0, a1, 8 +; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1RV64-NEXT: vse64.v v8, (a1) @@ -212,7 +212,6 @@ ; LMULMAX8RV32: # %bb.0: ; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8 -; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX8RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX8RV32-NEXT: slli a2, a1, 17 @@ -240,7 +239,6 @@ ; LMULMAX8RV64-NEXT: lui a2, 8 ; LMULMAX8RV64-NEXT: addiw a2, a2, -1 ; LMULMAX8RV64-NEXT: and a1, a1, a2 -; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1 ; LMULMAX8RV64-NEXT: vmv.x.s a3, v8 ; LMULMAX8RV64-NEXT: and a2, a3, a2 @@ -260,7 +258,6 @@ ; LMULMAX1RV32: # %bb.0: ; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8 -; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX1RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1RV32-NEXT: slli a2, a1, 17 @@ -288,7 +285,6 @@ ; LMULMAX1RV64-NEXT: lui a2, 8 ; LMULMAX1RV64-NEXT: addiw a2, a2, -1 ; LMULMAX1RV64-NEXT: and a1, a1, a2 -; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1 ; LMULMAX1RV64-NEXT: vmv.x.s a3, v8 ; LMULMAX1RV64-NEXT: and a2, a3, a2 @@ -313,7 +309,6 @@ ; LMULMAX8RV32: # %bb.0: ; LMULMAX8RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX8RV32-NEXT: vfncvt.rtz.x.f.w v9, v8 -; LMULMAX8RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX8RV32-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX8RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX8RV32-NEXT: slli a2, a1, 17 @@ -341,7 +336,6 @@ ; LMULMAX8RV64-NEXT: lui a2, 16 ; LMULMAX8RV64-NEXT: addiw a2, a2, -1 ; LMULMAX8RV64-NEXT: and a1, a1, a2 -; LMULMAX8RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX8RV64-NEXT: vslidedown.vi v8, v9, 1 ; LMULMAX8RV64-NEXT: vmv.x.s a3, v8 ; LMULMAX8RV64-NEXT: and a2, a3, a2 @@ -361,7 +355,6 @@ ; LMULMAX1RV32: # %bb.0: ; LMULMAX1RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; LMULMAX1RV32-NEXT: vfncvt.rtz.x.f.w v9, v8 -; LMULMAX1RV32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1RV32-NEXT: vslidedown.vi v8, v9, 2 ; LMULMAX1RV32-NEXT: vmv.x.s a1, v8 ; LMULMAX1RV32-NEXT: slli a2, a1, 17 @@ -389,7 +382,6 @@ ; LMULMAX1RV64-NEXT: lui a2, 16 ; LMULMAX1RV64-NEXT: addiw a2, a2, -1 ; LMULMAX1RV64-NEXT: and a1, a1, a2 -; LMULMAX1RV64-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; LMULMAX1RV64-NEXT: vslidedown.vi v8, v9, 1 ; LMULMAX1RV64-NEXT: vmv.x.s a3, v8 ; LMULMAX1RV64-NEXT: and a2, a3, a2 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll @@ -90,9 +90,9 @@ ; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vle32.v v8, (a0) ; LMULMAX8RV32-NEXT: vfcvt.f.x.v v8, v8 -; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV32-NEXT: addi a0, a1, 8 +; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v9, (a0) ; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v8, (a1) @@ -103,9 +103,9 @@ ; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vle32.v v8, (a0) ; LMULMAX8RV64-NEXT: vfcvt.f.x.v v8, v8 -; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV64-NEXT: addi a0, a1, 8 +; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vse32.v v9, (a0) ; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX8RV64-NEXT: vse64.v v8, (a1) @@ -116,9 +116,9 @@ ; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1RV32-NEXT: vfcvt.f.x.v v8, v8 -; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV32-NEXT: addi a0, a1, 8 +; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v8, (a1) @@ -129,9 +129,9 @@ ; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1RV64-NEXT: vfcvt.f.x.v v8, v8 -; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV64-NEXT: addi a0, a1, 8 +; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1RV64-NEXT: vse64.v v8, (a1) @@ -148,9 +148,9 @@ ; LMULMAX8RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vle32.v v8, (a0) ; LMULMAX8RV32-NEXT: vfcvt.f.xu.v v8, v8 -; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV32-NEXT: addi a0, a1, 8 +; LMULMAX8RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v9, (a0) ; LMULMAX8RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX8RV32-NEXT: vse32.v v8, (a1) @@ -161,9 +161,9 @@ ; LMULMAX8RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vle32.v v8, (a0) ; LMULMAX8RV64-NEXT: vfcvt.f.xu.v v8, v8 -; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX8RV64-NEXT: addi a0, a1, 8 +; LMULMAX8RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX8RV64-NEXT: vse32.v v9, (a0) ; LMULMAX8RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX8RV64-NEXT: vse64.v v8, (a1) @@ -174,9 +174,9 @@ ; LMULMAX1RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vle32.v v8, (a0) ; LMULMAX1RV32-NEXT: vfcvt.f.xu.v v8, v8 -; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV32-NEXT: addi a0, a1, 8 +; LMULMAX1RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX1RV32-NEXT: vse32.v v8, (a1) @@ -187,9 +187,9 @@ ; LMULMAX1RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vle32.v v8, (a0) ; LMULMAX1RV64-NEXT: vfcvt.f.xu.v v8, v8 -; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vslidedown.vi v9, v8, 2 ; LMULMAX1RV64-NEXT: addi a0, a1, 8 +; LMULMAX1RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; LMULMAX1RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; LMULMAX1RV64-NEXT: vse64.v v8, (a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll @@ -61,9 +61,9 @@ ; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -160,9 +160,9 @@ ; RV64-NEXT: vsub.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -259,9 +259,9 @@ ; RV64-NEXT: vmul.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -358,9 +358,9 @@ ; RV64-NEXT: vand.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -457,9 +457,9 @@ ; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -556,9 +556,9 @@ ; RV64-NEXT: vxor.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -655,9 +655,9 @@ ; RV64-NEXT: vsrl.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -754,9 +754,9 @@ ; RV64-NEXT: vsra.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -853,9 +853,9 @@ ; RV64-NEXT: vsll.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -967,9 +967,9 @@ ; RV64-NEXT: vslideup.vi v8, v10, 4 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -1081,9 +1081,9 @@ ; RV64-NEXT: vslideup.vi v8, v10, 4 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -1195,9 +1195,9 @@ ; RV64-NEXT: vslideup.vi v8, v10, 4 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -1309,9 +1309,9 @@ ; RV64-NEXT: vslideup.vi v8, v10, 4 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -1536,9 +1536,9 @@ ; RV64-NEXT: vslideup.vi v9, v8, 4 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v9, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v9, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -1763,9 +1763,9 @@ ; RV64-NEXT: vslideup.vi v8, v9, 4 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -1933,9 +1933,9 @@ ; RV64-NEXT: vmin.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2035,9 +2035,9 @@ ; RV64-NEXT: vmin.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2119,9 +2119,9 @@ ; RV64-NEXT: vmin.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2205,9 +2205,9 @@ ; RV64-NEXT: vmax.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2307,9 +2307,9 @@ ; RV64-NEXT: vmax.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2391,9 +2391,9 @@ ; RV64-NEXT: vmax.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2477,9 +2477,9 @@ ; RV64-NEXT: vminu.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2579,9 +2579,9 @@ ; RV64-NEXT: vminu.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2663,9 +2663,9 @@ ; RV64-NEXT: vminu.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2749,9 +2749,9 @@ ; RV64-NEXT: vmaxu.vv v8, v8, v9 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2851,9 +2851,9 @@ ; RV64-NEXT: vmaxu.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x @@ -2935,9 +2935,9 @@ ; RV64-NEXT: vmaxu.vx v8, v8, a1 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %a = load <6 x i16>, ptr %x diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-load.ll @@ -35,12 +35,12 @@ ; RV32-NEXT: or a1, a3, a1 ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32-NEXT: vmv.s.x v8, a1 -; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV32-NEXT: vslidedown.vi v9, v8, 1 ; RV32-NEXT: vslidedown.vi v10, v8, 2 ; RV32-NEXT: vslidedown.vi v11, v8, 3 ; RV32-NEXT: lb a0, 4(a0) ; RV32-NEXT: addi a1, sp, 8 +; RV32-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV32-NEXT: vse8.v v8, (a1) ; RV32-NEXT: addi a2, sp, 11 ; RV32-NEXT: vse8.v v11, (a2) @@ -70,12 +70,12 @@ ; RV64-NEXT: or a1, a3, a1 ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV64-NEXT: vmv.s.x v8, a1 -; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64-NEXT: vslidedown.vi v9, v8, 1 ; RV64-NEXT: vslidedown.vi v10, v8, 2 ; RV64-NEXT: vslidedown.vi v11, v8, 3 ; RV64-NEXT: lb a0, 4(a0) ; RV64-NEXT: addi a1, sp, 8 +; RV64-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64-NEXT: vse8.v v8, (a1) ; RV64-NEXT: addi a2, sp, 11 ; RV64-NEXT: vse8.v v11, (a2) @@ -148,9 +148,9 @@ ; RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; RV64-NEXT: vmv.s.x v8, a2 ; RV64-NEXT: sd a2, 0(a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret %x = load <6 x half>, ptr %p diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -330,7 +330,6 @@ ; RV32ZVE32F: # %bb.0: ; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t -; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: srai a2, a1, 31 @@ -392,7 +391,6 @@ ; RV32ZVE32F: # %bb.0: ; RV32ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, mu ; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t -; RV32ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: andi a1, a1, 255 @@ -798,13 +796,12 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB12_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lbu a2, 0(a2) ; RV64ZVE32F-NEXT: vmv.s.x v10, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e8, mf2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB12_8 @@ -1061,7 +1058,6 @@ ; RV32ZVE32F: # %bb.0: ; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu ; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t -; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: srai a2, a1, 31 @@ -1123,7 +1119,6 @@ ; RV32ZVE32F: # %bb.0: ; RV32ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, mu ; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t -; RV32ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: lui a2, 16 @@ -1542,15 +1537,14 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB23_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lh a2, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v10, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB23_8 @@ -1691,15 +1685,14 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB24_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lh a2, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v10, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB24_8 @@ -1845,16 +1838,15 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB25_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: andi a2, a2, 255 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lh a2, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v10, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB25_8 @@ -1997,14 +1989,13 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB26_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lh a2, 0(a2) ; RV64ZVE32F-NEXT: vmv.s.x v10, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB26_8 @@ -2158,12 +2149,12 @@ ; RV32ZVE32F: # %bb.0: ; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1 ; RV32ZVE32F-NEXT: vmv.x.s a1, v8 ; RV32ZVE32F-NEXT: srai a1, a1, 31 ; RV32ZVE32F-NEXT: vmv.x.s a2, v9 ; RV32ZVE32F-NEXT: srai a2, a2, 31 +; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ZVE32F-NEXT: vse32.v v9, (a0) ; RV32ZVE32F-NEXT: addi a3, a0, 8 ; RV32ZVE32F-NEXT: vse32.v v8, (a3) @@ -2221,10 +2212,10 @@ ; RV32ZVE32F: # %bb.0: ; RV32ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, mu ; RV32ZVE32F-NEXT: vluxei32.v v9, (zero), v8, v0.t -; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ZVE32F-NEXT: vslidedown.vi v8, v9, 1 ; RV32ZVE32F-NEXT: sw zero, 12(a0) ; RV32ZVE32F-NEXT: sw zero, 4(a0) +; RV32ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ZVE32F-NEXT: vse32.v v9, (a0) ; RV32ZVE32F-NEXT: addi a0, a0, 8 ; RV32ZVE32F-NEXT: vse32.v v8, (a0) @@ -2633,13 +2624,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB35_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -2782,13 +2772,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB36_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -2936,14 +2925,13 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB37_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: andi a2, a2, 255 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -3091,13 +3079,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB38_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -3241,13 +3228,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB39_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: lw a2, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v12, a2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -3398,14 +3384,13 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB40_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: and a3, a3, a1 ; RV64ZVE32F-NEXT: slli a3, a3, 2 ; RV64ZVE32F-NEXT: add a3, a0, a3 ; RV64ZVE32F-NEXT: lw a3, 0(a3) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.s.x v12, a3 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -4469,7 +4454,6 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4 ; RV64ZVE32F-NEXT: beqz a7, .LBB48_12 ; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v9 ; RV64ZVE32F-NEXT: slli a7, a7, 3 @@ -4489,7 +4473,6 @@ ; RV64ZVE32F-NEXT: andi t0, a6, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB48_10 ; RV64ZVE32F-NEXT: .LBB48_13: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v8 ; RV64ZVE32F-NEXT: slli t0, t0, 3 ; RV64ZVE32F-NEXT: add t0, a1, t0 @@ -4497,7 +4480,6 @@ ; RV64ZVE32F-NEXT: andi t1, a6, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB48_11 ; RV64ZVE32F-NEXT: .LBB48_14: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v9 ; RV64ZVE32F-NEXT: slli t1, t1, 3 @@ -4523,7 +4505,6 @@ ; RV64ZVE32F-NEXT: andi a6, a6, -128 ; RV64ZVE32F-NEXT: beqz a6, .LBB48_17 ; RV64ZVE32F-NEXT: .LBB48_19: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -4748,7 +4729,6 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4 ; RV64ZVE32F-NEXT: beqz a7, .LBB49_12 ; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v9 ; RV64ZVE32F-NEXT: slli a7, a7, 3 @@ -4768,7 +4748,6 @@ ; RV64ZVE32F-NEXT: andi t0, a6, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB49_10 ; RV64ZVE32F-NEXT: .LBB49_13: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v8 ; RV64ZVE32F-NEXT: slli t0, t0, 3 ; RV64ZVE32F-NEXT: add t0, a1, t0 @@ -4776,7 +4755,6 @@ ; RV64ZVE32F-NEXT: andi t1, a6, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB49_11 ; RV64ZVE32F-NEXT: .LBB49_14: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v9 ; RV64ZVE32F-NEXT: slli t1, t1, 3 @@ -4802,7 +4780,6 @@ ; RV64ZVE32F-NEXT: andi a6, a6, -128 ; RV64ZVE32F-NEXT: beqz a6, .LBB49_17 ; RV64ZVE32F-NEXT: .LBB49_19: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -5031,7 +5008,6 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4 ; RV64ZVE32F-NEXT: beqz a7, .LBB50_12 ; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v9 ; RV64ZVE32F-NEXT: andi a7, a7, 255 @@ -5052,7 +5028,6 @@ ; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB50_10 ; RV64ZVE32F-NEXT: .LBB50_13: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v8 ; RV64ZVE32F-NEXT: andi t0, t0, 255 ; RV64ZVE32F-NEXT: slli t0, t0, 3 @@ -5061,7 +5036,6 @@ ; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB50_11 ; RV64ZVE32F-NEXT: .LBB50_14: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v9 ; RV64ZVE32F-NEXT: andi t1, t1, 255 @@ -5089,7 +5063,6 @@ ; RV64ZVE32F-NEXT: andi a5, a5, -128 ; RV64ZVE32F-NEXT: beqz a5, .LBB50_17 ; RV64ZVE32F-NEXT: .LBB50_19: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -5273,8 +5246,8 @@ ; RV64ZVE32F-LABEL: mgather_baseidx_v8i16_v8i64: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma -; RV64ZVE32F-NEXT: vmv.x.s a6, v0 -; RV64ZVE32F-NEXT: andi a3, a6, 1 +; RV64ZVE32F-NEXT: vmv.x.s a5, v0 +; RV64ZVE32F-NEXT: andi a3, a5, 1 ; RV64ZVE32F-NEXT: beqz a3, .LBB51_3 ; RV64ZVE32F-NEXT: # %bb.1: # %cond.load ; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma @@ -5282,14 +5255,14 @@ ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 ; RV64ZVE32F-NEXT: ld a3, 0(a3) -; RV64ZVE32F-NEXT: andi a4, a6, 2 +; RV64ZVE32F-NEXT: andi a4, a5, 2 ; RV64ZVE32F-NEXT: bnez a4, .LBB51_4 ; RV64ZVE32F-NEXT: .LBB51_2: ; RV64ZVE32F-NEXT: ld a4, 8(a2) ; RV64ZVE32F-NEXT: j .LBB51_5 ; RV64ZVE32F-NEXT: .LBB51_3: ; RV64ZVE32F-NEXT: ld a3, 0(a2) -; RV64ZVE32F-NEXT: andi a4, a6, 2 +; RV64ZVE32F-NEXT: andi a4, a5, 2 ; RV64ZVE32F-NEXT: beqz a4, .LBB51_2 ; RV64ZVE32F-NEXT: .LBB51_4: # %cond.load1 ; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma @@ -5300,52 +5273,49 @@ ; RV64ZVE32F-NEXT: ld a4, 0(a4) ; RV64ZVE32F-NEXT: .LBB51_5: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: andi a5, a6, 4 +; RV64ZVE32F-NEXT: andi a6, a5, 4 ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: beqz a5, .LBB51_7 +; RV64ZVE32F-NEXT: beqz a6, .LBB51_7 ; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4 -; RV64ZVE32F-NEXT: vmv.x.s a5, v9 -; RV64ZVE32F-NEXT: slli a5, a5, 3 -; RV64ZVE32F-NEXT: add a5, a1, a5 -; RV64ZVE32F-NEXT: ld a5, 0(a5) +; RV64ZVE32F-NEXT: vmv.x.s a6, v9 +; RV64ZVE32F-NEXT: slli a6, a6, 3 +; RV64ZVE32F-NEXT: add a6, a1, a6 +; RV64ZVE32F-NEXT: ld a6, 0(a6) ; RV64ZVE32F-NEXT: j .LBB51_8 ; RV64ZVE32F-NEXT: .LBB51_7: -; RV64ZVE32F-NEXT: ld a5, 16(a2) +; RV64ZVE32F-NEXT: ld a6, 16(a2) ; RV64ZVE32F-NEXT: .LBB51_8: # %else5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma -; RV64ZVE32F-NEXT: andi a7, a6, 8 +; RV64ZVE32F-NEXT: andi a7, a5, 8 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4 ; RV64ZVE32F-NEXT: beqz a7, .LBB51_12 ; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v9 ; RV64ZVE32F-NEXT: slli a7, a7, 3 ; RV64ZVE32F-NEXT: add a7, a1, a7 ; RV64ZVE32F-NEXT: ld a7, 0(a7) -; RV64ZVE32F-NEXT: andi t0, a6, 16 +; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: bnez t0, .LBB51_13 ; RV64ZVE32F-NEXT: .LBB51_10: ; RV64ZVE32F-NEXT: ld t0, 32(a2) -; RV64ZVE32F-NEXT: andi t1, a6, 32 +; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: bnez t1, .LBB51_14 ; RV64ZVE32F-NEXT: .LBB51_11: ; RV64ZVE32F-NEXT: ld t1, 40(a2) ; RV64ZVE32F-NEXT: j .LBB51_15 ; RV64ZVE32F-NEXT: .LBB51_12: ; RV64ZVE32F-NEXT: ld a7, 24(a2) -; RV64ZVE32F-NEXT: andi t0, a6, 16 +; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB51_10 ; RV64ZVE32F-NEXT: .LBB51_13: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v8 ; RV64ZVE32F-NEXT: slli t0, t0, 3 ; RV64ZVE32F-NEXT: add t0, a1, t0 ; RV64ZVE32F-NEXT: ld t0, 0(t0) -; RV64ZVE32F-NEXT: andi t1, a6, 32 +; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB51_11 ; RV64ZVE32F-NEXT: .LBB51_14: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v9 ; RV64ZVE32F-NEXT: slli t1, t1, 3 @@ -5353,7 +5323,7 @@ ; RV64ZVE32F-NEXT: ld t1, 0(t1) ; RV64ZVE32F-NEXT: .LBB51_15: # %else14 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: andi t2, a6, 64 +; RV64ZVE32F-NEXT: andi t2, a5, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2 ; RV64ZVE32F-NEXT: beqz t2, .LBB51_18 ; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16 @@ -5361,17 +5331,16 @@ ; RV64ZVE32F-NEXT: slli t2, t2, 3 ; RV64ZVE32F-NEXT: add t2, a1, t2 ; RV64ZVE32F-NEXT: ld t2, 0(t2) -; RV64ZVE32F-NEXT: andi a6, a6, -128 -; RV64ZVE32F-NEXT: bnez a6, .LBB51_19 +; RV64ZVE32F-NEXT: andi a5, a5, -128 +; RV64ZVE32F-NEXT: bnez a5, .LBB51_19 ; RV64ZVE32F-NEXT: .LBB51_17: ; RV64ZVE32F-NEXT: ld a1, 56(a2) ; RV64ZVE32F-NEXT: j .LBB51_20 ; RV64ZVE32F-NEXT: .LBB51_18: ; RV64ZVE32F-NEXT: ld t2, 48(a2) -; RV64ZVE32F-NEXT: andi a6, a6, -128 -; RV64ZVE32F-NEXT: beqz a6, .LBB51_17 +; RV64ZVE32F-NEXT: andi a5, a5, -128 +; RV64ZVE32F-NEXT: beqz a5, .LBB51_17 ; RV64ZVE32F-NEXT: .LBB51_19: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -5380,7 +5349,7 @@ ; RV64ZVE32F-NEXT: .LBB51_20: # %else20 ; RV64ZVE32F-NEXT: sd a3, 0(a0) ; RV64ZVE32F-NEXT: sd a4, 8(a0) -; RV64ZVE32F-NEXT: sd a5, 16(a0) +; RV64ZVE32F-NEXT: sd a6, 16(a0) ; RV64ZVE32F-NEXT: sd a7, 24(a0) ; RV64ZVE32F-NEXT: sd t0, 32(a0) ; RV64ZVE32F-NEXT: sd t1, 40(a0) @@ -5553,8 +5522,8 @@ ; RV64ZVE32F-LABEL: mgather_baseidx_sext_v8i16_v8i64: ; RV64ZVE32F: # %bb.0: ; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma -; RV64ZVE32F-NEXT: vmv.x.s a6, v0 -; RV64ZVE32F-NEXT: andi a3, a6, 1 +; RV64ZVE32F-NEXT: vmv.x.s a5, v0 +; RV64ZVE32F-NEXT: andi a3, a5, 1 ; RV64ZVE32F-NEXT: beqz a3, .LBB52_3 ; RV64ZVE32F-NEXT: # %bb.1: # %cond.load ; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, mf2, ta, ma @@ -5562,14 +5531,14 @@ ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 ; RV64ZVE32F-NEXT: ld a3, 0(a3) -; RV64ZVE32F-NEXT: andi a4, a6, 2 +; RV64ZVE32F-NEXT: andi a4, a5, 2 ; RV64ZVE32F-NEXT: bnez a4, .LBB52_4 ; RV64ZVE32F-NEXT: .LBB52_2: ; RV64ZVE32F-NEXT: ld a4, 8(a2) ; RV64ZVE32F-NEXT: j .LBB52_5 ; RV64ZVE32F-NEXT: .LBB52_3: ; RV64ZVE32F-NEXT: ld a3, 0(a2) -; RV64ZVE32F-NEXT: andi a4, a6, 2 +; RV64ZVE32F-NEXT: andi a4, a5, 2 ; RV64ZVE32F-NEXT: beqz a4, .LBB52_2 ; RV64ZVE32F-NEXT: .LBB52_4: # %cond.load1 ; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma @@ -5580,52 +5549,49 @@ ; RV64ZVE32F-NEXT: ld a4, 0(a4) ; RV64ZVE32F-NEXT: .LBB52_5: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: andi a5, a6, 4 +; RV64ZVE32F-NEXT: andi a6, a5, 4 ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 2 -; RV64ZVE32F-NEXT: beqz a5, .LBB52_7 +; RV64ZVE32F-NEXT: beqz a6, .LBB52_7 ; RV64ZVE32F-NEXT: # %bb.6: # %cond.load4 -; RV64ZVE32F-NEXT: vmv.x.s a5, v9 -; RV64ZVE32F-NEXT: slli a5, a5, 3 -; RV64ZVE32F-NEXT: add a5, a1, a5 -; RV64ZVE32F-NEXT: ld a5, 0(a5) +; RV64ZVE32F-NEXT: vmv.x.s a6, v9 +; RV64ZVE32F-NEXT: slli a6, a6, 3 +; RV64ZVE32F-NEXT: add a6, a1, a6 +; RV64ZVE32F-NEXT: ld a6, 0(a6) ; RV64ZVE32F-NEXT: j .LBB52_8 ; RV64ZVE32F-NEXT: .LBB52_7: -; RV64ZVE32F-NEXT: ld a5, 16(a2) +; RV64ZVE32F-NEXT: ld a6, 16(a2) ; RV64ZVE32F-NEXT: .LBB52_8: # %else5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma -; RV64ZVE32F-NEXT: andi a7, a6, 8 +; RV64ZVE32F-NEXT: andi a7, a5, 8 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4 ; RV64ZVE32F-NEXT: beqz a7, .LBB52_12 ; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v9 ; RV64ZVE32F-NEXT: slli a7, a7, 3 ; RV64ZVE32F-NEXT: add a7, a1, a7 ; RV64ZVE32F-NEXT: ld a7, 0(a7) -; RV64ZVE32F-NEXT: andi t0, a6, 16 +; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: bnez t0, .LBB52_13 ; RV64ZVE32F-NEXT: .LBB52_10: ; RV64ZVE32F-NEXT: ld t0, 32(a2) -; RV64ZVE32F-NEXT: andi t1, a6, 32 +; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: bnez t1, .LBB52_14 ; RV64ZVE32F-NEXT: .LBB52_11: ; RV64ZVE32F-NEXT: ld t1, 40(a2) ; RV64ZVE32F-NEXT: j .LBB52_15 ; RV64ZVE32F-NEXT: .LBB52_12: ; RV64ZVE32F-NEXT: ld a7, 24(a2) -; RV64ZVE32F-NEXT: andi t0, a6, 16 +; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB52_10 ; RV64ZVE32F-NEXT: .LBB52_13: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v8 ; RV64ZVE32F-NEXT: slli t0, t0, 3 ; RV64ZVE32F-NEXT: add t0, a1, t0 ; RV64ZVE32F-NEXT: ld t0, 0(t0) -; RV64ZVE32F-NEXT: andi t1, a6, 32 +; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB52_11 ; RV64ZVE32F-NEXT: .LBB52_14: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v9 ; RV64ZVE32F-NEXT: slli t1, t1, 3 @@ -5633,7 +5599,7 @@ ; RV64ZVE32F-NEXT: ld t1, 0(t1) ; RV64ZVE32F-NEXT: .LBB52_15: # %else14 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma -; RV64ZVE32F-NEXT: andi t2, a6, 64 +; RV64ZVE32F-NEXT: andi t2, a5, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 2 ; RV64ZVE32F-NEXT: beqz t2, .LBB52_18 ; RV64ZVE32F-NEXT: # %bb.16: # %cond.load16 @@ -5641,17 +5607,16 @@ ; RV64ZVE32F-NEXT: slli t2, t2, 3 ; RV64ZVE32F-NEXT: add t2, a1, t2 ; RV64ZVE32F-NEXT: ld t2, 0(t2) -; RV64ZVE32F-NEXT: andi a6, a6, -128 -; RV64ZVE32F-NEXT: bnez a6, .LBB52_19 +; RV64ZVE32F-NEXT: andi a5, a5, -128 +; RV64ZVE32F-NEXT: bnez a5, .LBB52_19 ; RV64ZVE32F-NEXT: .LBB52_17: ; RV64ZVE32F-NEXT: ld a1, 56(a2) ; RV64ZVE32F-NEXT: j .LBB52_20 ; RV64ZVE32F-NEXT: .LBB52_18: ; RV64ZVE32F-NEXT: ld t2, 48(a2) -; RV64ZVE32F-NEXT: andi a6, a6, -128 -; RV64ZVE32F-NEXT: beqz a6, .LBB52_17 +; RV64ZVE32F-NEXT: andi a5, a5, -128 +; RV64ZVE32F-NEXT: beqz a5, .LBB52_17 ; RV64ZVE32F-NEXT: .LBB52_19: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -5660,7 +5625,7 @@ ; RV64ZVE32F-NEXT: .LBB52_20: # %else20 ; RV64ZVE32F-NEXT: sd a3, 0(a0) ; RV64ZVE32F-NEXT: sd a4, 8(a0) -; RV64ZVE32F-NEXT: sd a5, 16(a0) +; RV64ZVE32F-NEXT: sd a6, 16(a0) ; RV64ZVE32F-NEXT: sd a7, 24(a0) ; RV64ZVE32F-NEXT: sd t0, 32(a0) ; RV64ZVE32F-NEXT: sd t1, 40(a0) @@ -5883,7 +5848,6 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 4 ; RV64ZVE32F-NEXT: beqz t0, .LBB53_12 ; RV64ZVE32F-NEXT: # %bb.9: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s t0, v9 ; RV64ZVE32F-NEXT: and t0, t0, a5 @@ -5904,7 +5868,6 @@ ; RV64ZVE32F-NEXT: andi t1, a6, 16 ; RV64ZVE32F-NEXT: beqz t1, .LBB53_10 ; RV64ZVE32F-NEXT: .LBB53_13: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t1, v8 ; RV64ZVE32F-NEXT: and t1, t1, a5 ; RV64ZVE32F-NEXT: slli t1, t1, 3 @@ -5913,7 +5876,6 @@ ; RV64ZVE32F-NEXT: andi t2, a6, 32 ; RV64ZVE32F-NEXT: beqz t2, .LBB53_11 ; RV64ZVE32F-NEXT: .LBB53_14: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s t2, v9 ; RV64ZVE32F-NEXT: and t2, t2, a5 @@ -5941,7 +5903,6 @@ ; RV64ZVE32F-NEXT: andi a6, a6, -128 ; RV64ZVE32F-NEXT: beqz a6, .LBB53_17 ; RV64ZVE32F-NEXT: .LBB53_19: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: and a2, a2, a5 @@ -6178,7 +6139,6 @@ ; RV64ZVE32F-NEXT: andi a7, a5, 8 ; RV64ZVE32F-NEXT: beqz a7, .LBB54_7 ; RV64ZVE32F-NEXT: .LBB54_11: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v8 ; RV64ZVE32F-NEXT: slli a7, a7, 3 @@ -6187,7 +6147,6 @@ ; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB54_8 ; RV64ZVE32F-NEXT: .LBB54_12: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v10 ; RV64ZVE32F-NEXT: slli t0, t0, 3 ; RV64ZVE32F-NEXT: add t0, a1, t0 @@ -6195,14 +6154,12 @@ ; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB54_9 ; RV64ZVE32F-NEXT: .LBB54_13: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v8 ; RV64ZVE32F-NEXT: slli t1, t1, 3 ; RV64ZVE32F-NEXT: add t1, a1, t1 ; RV64ZVE32F-NEXT: ld t1, 0(t1) ; RV64ZVE32F-NEXT: .LBB54_14: # %else14 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi t2, a5, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: beqz t2, .LBB54_17 @@ -6221,7 +6178,6 @@ ; RV64ZVE32F-NEXT: andi a5, a5, -128 ; RV64ZVE32F-NEXT: beqz a5, .LBB54_16 ; RV64ZVE32F-NEXT: .LBB54_18: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -6456,7 +6412,6 @@ ; RV64ZVE32F-NEXT: andi a7, a5, 8 ; RV64ZVE32F-NEXT: beqz a7, .LBB55_7 ; RV64ZVE32F-NEXT: .LBB55_11: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v8 ; RV64ZVE32F-NEXT: slli a7, a7, 3 @@ -6465,7 +6420,6 @@ ; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB55_8 ; RV64ZVE32F-NEXT: .LBB55_12: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v10 ; RV64ZVE32F-NEXT: slli t0, t0, 3 ; RV64ZVE32F-NEXT: add t0, a1, t0 @@ -6473,14 +6427,12 @@ ; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB55_9 ; RV64ZVE32F-NEXT: .LBB55_13: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v8 ; RV64ZVE32F-NEXT: slli t1, t1, 3 ; RV64ZVE32F-NEXT: add t1, a1, t1 ; RV64ZVE32F-NEXT: ld t1, 0(t1) ; RV64ZVE32F-NEXT: .LBB55_14: # %else14 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi t2, a5, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: beqz t2, .LBB55_17 @@ -6499,7 +6451,6 @@ ; RV64ZVE32F-NEXT: andi a5, a5, -128 ; RV64ZVE32F-NEXT: beqz a5, .LBB55_16 ; RV64ZVE32F-NEXT: .LBB55_18: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -6738,7 +6689,6 @@ ; RV64ZVE32F-NEXT: andi a7, a5, 8 ; RV64ZVE32F-NEXT: beqz a7, .LBB56_7 ; RV64ZVE32F-NEXT: .LBB56_11: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a7, v8 ; RV64ZVE32F-NEXT: slli a7, a7, 32 @@ -6748,7 +6698,6 @@ ; RV64ZVE32F-NEXT: andi t0, a5, 16 ; RV64ZVE32F-NEXT: beqz t0, .LBB56_8 ; RV64ZVE32F-NEXT: .LBB56_12: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s t0, v10 ; RV64ZVE32F-NEXT: slli t0, t0, 32 ; RV64ZVE32F-NEXT: srli t0, t0, 29 @@ -6757,7 +6706,6 @@ ; RV64ZVE32F-NEXT: andi t1, a5, 32 ; RV64ZVE32F-NEXT: beqz t1, .LBB56_9 ; RV64ZVE32F-NEXT: .LBB56_13: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s t1, v8 ; RV64ZVE32F-NEXT: slli t1, t1, 32 @@ -6765,7 +6713,6 @@ ; RV64ZVE32F-NEXT: add t1, a1, t1 ; RV64ZVE32F-NEXT: ld t1, 0(t1) ; RV64ZVE32F-NEXT: .LBB56_14: # %else14 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi t2, a5, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: beqz t2, .LBB56_17 @@ -6785,7 +6732,6 @@ ; RV64ZVE32F-NEXT: andi a5, a5, -128 ; RV64ZVE32F-NEXT: beqz a5, .LBB56_16 ; RV64ZVE32F-NEXT: .LBB56_18: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 32 @@ -7582,15 +7528,14 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB64_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flh fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB64_8 @@ -7731,15 +7676,14 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB65_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flh fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB65_8 @@ -7885,16 +7829,15 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB66_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: andi a2, a2, 255 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flh fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetivli zero, 8, e16, m1, ta, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB66_8 @@ -8037,14 +7980,13 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB67_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flh fa5, 0(a2) ; RV64ZVE32F-NEXT: vfmv.s.f v10, fa5 -; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, tu, ma +; RV64ZVE32F-NEXT: vsetvli zero, zero, e16, m1, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v9, v10, 3 ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB67_8 @@ -8547,13 +8489,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB74_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -8696,13 +8637,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB75_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -8850,14 +8790,13 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB76_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: andi a2, a2, 255 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -9005,13 +8944,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB77_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -9155,13 +9093,12 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB78_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: flw fa5, 0(a2) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -9312,14 +9249,13 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB79_13: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: and a3, a3, a1 ; RV64ZVE32F-NEXT: slli a3, a3, 2 ; RV64ZVE32F-NEXT: add a3, a0, a3 ; RV64ZVE32F-NEXT: flw fa5, 0(a3) -; RV64ZVE32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma +; RV64ZVE32F-NEXT: vsetivli zero, 8, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vfmv.s.f v12, fa5 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, tu, ma ; RV64ZVE32F-NEXT: vslideup.vi v10, v12, 3 @@ -10215,7 +10151,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB87_10 ; RV64ZVE32F-NEXT: .LBB87_9: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10235,7 +10170,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB87_14 ; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -10252,7 +10186,6 @@ ; RV64ZVE32F-NEXT: fsd fa7, 56(a0) ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB87_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10261,7 +10194,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB87_8 ; RV64ZVE32F-NEXT: .LBB87_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 @@ -10433,7 +10365,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB88_10 ; RV64ZVE32F-NEXT: .LBB88_9: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10453,7 +10384,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB88_14 ; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -10470,7 +10400,6 @@ ; RV64ZVE32F-NEXT: fsd fa7, 56(a0) ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB88_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10479,7 +10408,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB88_8 ; RV64ZVE32F-NEXT: .LBB88_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 @@ -10655,7 +10583,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB89_10 ; RV64ZVE32F-NEXT: .LBB89_9: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: andi a3, a3, 255 @@ -10677,7 +10604,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB89_14 ; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -10695,7 +10621,6 @@ ; RV64ZVE32F-NEXT: fsd fa7, 56(a0) ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB89_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: andi a3, a3, 255 @@ -10705,7 +10630,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB89_8 ; RV64ZVE32F-NEXT: .LBB89_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: andi a3, a3, 255 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10880,7 +10804,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB90_10 ; RV64ZVE32F-NEXT: .LBB90_9: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10900,7 +10823,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB90_14 ; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -10917,7 +10839,6 @@ ; RV64ZVE32F-NEXT: fsd fa7, 56(a0) ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB90_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -10926,7 +10847,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB90_8 ; RV64ZVE32F-NEXT: .LBB90_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 @@ -11099,7 +11019,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB91_10 ; RV64ZVE32F-NEXT: .LBB91_9: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -11119,7 +11038,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB91_14 ; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -11136,7 +11054,6 @@ ; RV64ZVE32F-NEXT: fsd fa7, 56(a0) ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB91_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -11145,7 +11062,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB91_8 ; RV64ZVE32F-NEXT: .LBB91_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 @@ -11324,7 +11240,6 @@ ; RV64ZVE32F-NEXT: andi a4, a3, 32 ; RV64ZVE32F-NEXT: beqz a4, .LBB92_10 ; RV64ZVE32F-NEXT: .LBB92_9: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a4, v9 ; RV64ZVE32F-NEXT: and a4, a4, a2 @@ -11346,7 +11261,6 @@ ; RV64ZVE32F-NEXT: andi a3, a3, -128 ; RV64ZVE32F-NEXT: beqz a3, .LBB92_14 ; RV64ZVE32F-NEXT: # %bb.13: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: and a2, a3, a2 @@ -11364,7 +11278,6 @@ ; RV64ZVE32F-NEXT: fsd fa7, 56(a0) ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB92_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a4, v9 ; RV64ZVE32F-NEXT: and a4, a4, a2 @@ -11374,7 +11287,6 @@ ; RV64ZVE32F-NEXT: andi a4, a3, 16 ; RV64ZVE32F-NEXT: beqz a4, .LBB92_8 ; RV64ZVE32F-NEXT: .LBB92_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a4, v8 ; RV64ZVE32F-NEXT: and a4, a4, a2 ; RV64ZVE32F-NEXT: slli a4, a4, 3 @@ -11542,14 +11454,12 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB93_9 ; RV64ZVE32F-NEXT: .LBB93_8: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 ; RV64ZVE32F-NEXT: fld fa5, 0(a3) ; RV64ZVE32F-NEXT: .LBB93_9: # %else14 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a3, a2, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: beqz a3, .LBB93_11 @@ -11562,7 +11472,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB93_13 ; RV64ZVE32F-NEXT: # %bb.12: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -11586,7 +11495,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 8 ; RV64ZVE32F-NEXT: beqz a3, .LBB93_6 ; RV64ZVE32F-NEXT: .LBB93_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -11595,7 +11503,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB93_7 ; RV64ZVE32F-NEXT: .LBB93_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v10 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 @@ -11761,14 +11668,12 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB94_9 ; RV64ZVE32F-NEXT: .LBB94_8: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 ; RV64ZVE32F-NEXT: fld fa5, 0(a3) ; RV64ZVE32F-NEXT: .LBB94_9: # %else14 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a3, a2, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: beqz a3, .LBB94_11 @@ -11781,7 +11686,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB94_13 ; RV64ZVE32F-NEXT: # %bb.12: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -11805,7 +11709,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 8 ; RV64ZVE32F-NEXT: beqz a3, .LBB94_6 ; RV64ZVE32F-NEXT: .LBB94_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -11814,7 +11717,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB94_7 ; RV64ZVE32F-NEXT: .LBB94_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v10 ; RV64ZVE32F-NEXT: slli a3, a3, 3 ; RV64ZVE32F-NEXT: add a3, a1, a3 @@ -11983,7 +11885,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB95_9 ; RV64ZVE32F-NEXT: .LBB95_8: # %cond.load13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 32 @@ -11991,7 +11892,6 @@ ; RV64ZVE32F-NEXT: add a3, a1, a3 ; RV64ZVE32F-NEXT: fld fa5, 0(a3) ; RV64ZVE32F-NEXT: .LBB95_9: # %else14 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a3, a2, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: beqz a3, .LBB95_11 @@ -12005,7 +11905,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB95_13 ; RV64ZVE32F-NEXT: # %bb.12: # %cond.load19 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 32 @@ -12031,7 +11930,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 8 ; RV64ZVE32F-NEXT: beqz a3, .LBB95_6 ; RV64ZVE32F-NEXT: .LBB95_15: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: slli a3, a3, 32 @@ -12041,7 +11939,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB95_7 ; RV64ZVE32F-NEXT: .LBB95_16: # %cond.load10 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v10 ; RV64ZVE32F-NEXT: slli a3, a3, 32 ; RV64ZVE32F-NEXT: srli a3, a3, 29 @@ -12462,7 +12359,6 @@ ; RV64ZVE32F-NEXT: vmv1r.v v8, v9 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB97_26: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -12517,7 +12413,6 @@ ; RV64ZVE32F-NEXT: bnez a2, .LBB97_14 ; RV64ZVE32F-NEXT: j .LBB97_15 ; RV64ZVE32F-NEXT: .LBB97_31: # %cond.load31 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -12690,7 +12585,6 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 4 ; RV64ZVE32F-NEXT: bgez a2, .LBB98_19 ; RV64ZVE32F-NEXT: # %bb.18: # %cond.load31 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -12885,7 +12779,6 @@ ; RV64ZVE32F-NEXT: vmv2r.v v8, v10 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB98_50: # %cond.load7 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -12985,7 +12878,6 @@ ; RV64ZVE32F-NEXT: bltz a2, .LBB98_27 ; RV64ZVE32F-NEXT: j .LBB98_28 ; RV64ZVE32F-NEXT: .LBB98_58: # %cond.load55 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -13048,7 +12940,6 @@ ; RV64ZVE32F-NEXT: bltz a2, .LBB98_38 ; RV64ZVE32F-NEXT: j .LBB98_39 ; RV64ZVE32F-NEXT: .LBB98_63: # %cond.load79 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll @@ -528,8 +528,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB9_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -539,8 +539,8 @@ ; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v11, (a2) ; RV64ZVE32F-NEXT: .LBB9_6: # %else4 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -558,8 +558,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB9_10: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -572,12 +572,11 @@ ; RV64ZVE32F-NEXT: .LBB9_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB9_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB9_8 @@ -594,8 +593,8 @@ ; RV64ZVE32F-NEXT: .LBB9_15: # %cond.store11 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB9_12 @@ -604,8 +603,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v9 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v8, (a0) ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i8, ptr %base, <8 x i8> %idxs @@ -1124,7 +1123,6 @@ ; RV64ZVE32F-NEXT: .LBB18_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB18_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 @@ -1255,7 +1253,6 @@ ; RV64ZVE32F-NEXT: .LBB19_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB19_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 @@ -1391,7 +1388,6 @@ ; RV64ZVE32F-NEXT: .LBB20_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB20_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -1482,8 +1478,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB21_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma @@ -1494,8 +1490,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v11, (a2) ; RV64ZVE32F-NEXT: .LBB21_6: # %else4 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma @@ -1514,8 +1510,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB21_10: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma @@ -1528,13 +1524,12 @@ ; RV64ZVE32F-NEXT: .LBB21_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB21_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB21_8 @@ -1553,8 +1548,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB21_12 @@ -1564,8 +1559,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a1, v9 ; RV64ZVE32F-NEXT: slli a1, a1, 1 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v8, (a0) ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i16> %idxs @@ -2029,7 +2024,6 @@ ; RV64ZVE32F-NEXT: .LBB29_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB29_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -2159,7 +2153,6 @@ ; RV64ZVE32F-NEXT: .LBB30_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB30_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -2294,7 +2287,6 @@ ; RV64ZVE32F-NEXT: .LBB31_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB31_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -2430,7 +2422,6 @@ ; RV64ZVE32F-NEXT: .LBB32_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB32_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -2561,7 +2552,6 @@ ; RV64ZVE32F-NEXT: .LBB33_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB33_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -2699,7 +2689,6 @@ ; RV64ZVE32F-NEXT: .LBB34_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB34_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v11 ; RV64ZVE32F-NEXT: and a3, a3, a1 @@ -2788,8 +2777,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB35_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma @@ -2813,8 +2802,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB35_9: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma @@ -2830,8 +2819,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v14, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 8 ; RV64ZVE32F-NEXT: beqz a2, .LBB35_6 @@ -2841,8 +2830,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v10, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB35_7 @@ -2861,8 +2850,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v12, (a2) ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB35_11 @@ -2872,8 +2861,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a1, v10 ; RV64ZVE32F-NEXT: slli a1, a1, 2 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v8, (a0) ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i32, ptr %base, <8 x i32> %idxs @@ -3647,7 +3636,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB42_10 ; RV64ZVE32F-NEXT: .LBB42_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -3664,7 +3652,6 @@ ; RV64ZVE32F-NEXT: .LBB42_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB42_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -3673,7 +3660,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB42_8 ; RV64ZVE32F-NEXT: .LBB42_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 @@ -3689,7 +3675,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB42_12 ; RV64ZVE32F-NEXT: .LBB42_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -3894,7 +3879,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB43_10 ; RV64ZVE32F-NEXT: .LBB43_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -3911,7 +3895,6 @@ ; RV64ZVE32F-NEXT: .LBB43_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB43_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -3920,7 +3903,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB43_8 ; RV64ZVE32F-NEXT: .LBB43_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 @@ -3936,7 +3918,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB43_12 ; RV64ZVE32F-NEXT: .LBB43_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4145,7 +4126,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB44_10 ; RV64ZVE32F-NEXT: .LBB44_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: andi a0, a0, 255 @@ -4163,7 +4143,6 @@ ; RV64ZVE32F-NEXT: .LBB44_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB44_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: andi a0, a0, 255 @@ -4173,7 +4152,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB44_8 ; RV64ZVE32F-NEXT: .LBB44_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: andi a0, a0, 255 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4191,7 +4169,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB44_12 ; RV64ZVE32F-NEXT: .LBB44_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: andi a0, a0, 255 @@ -4399,7 +4376,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB45_10 ; RV64ZVE32F-NEXT: .LBB45_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4416,7 +4392,6 @@ ; RV64ZVE32F-NEXT: .LBB45_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB45_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4425,7 +4400,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB45_8 ; RV64ZVE32F-NEXT: .LBB45_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 @@ -4441,7 +4415,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB45_12 ; RV64ZVE32F-NEXT: .LBB45_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4647,7 +4620,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB46_10 ; RV64ZVE32F-NEXT: .LBB46_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4664,7 +4636,6 @@ ; RV64ZVE32F-NEXT: .LBB46_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB46_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4673,7 +4644,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB46_8 ; RV64ZVE32F-NEXT: .LBB46_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 @@ -4689,7 +4659,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB46_12 ; RV64ZVE32F-NEXT: .LBB46_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4901,7 +4870,6 @@ ; RV64ZVE32F-NEXT: andi a0, a5, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB47_10 ; RV64ZVE32F-NEXT: .LBB47_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: and a0, a0, a4 @@ -4919,7 +4887,6 @@ ; RV64ZVE32F-NEXT: .LBB47_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB47_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v9 ; RV64ZVE32F-NEXT: and a0, a0, a4 @@ -4929,7 +4896,6 @@ ; RV64ZVE32F-NEXT: andi a0, a5, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB47_8 ; RV64ZVE32F-NEXT: .LBB47_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: and a0, a0, a4 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -4947,7 +4913,6 @@ ; RV64ZVE32F-NEXT: andi a0, a5, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB47_12 ; RV64ZVE32F-NEXT: .LBB47_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: and a0, a0, a4 @@ -5148,14 +5113,12 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB48_9 ; RV64ZVE32F-NEXT: .LBB48_8: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 ; RV64ZVE32F-NEXT: sd a5, 0(a0) ; RV64ZVE32F-NEXT: .LBB48_9: # %else10 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a0, a4, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: bnez a0, .LBB48_15 @@ -5172,7 +5135,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 8 ; RV64ZVE32F-NEXT: beqz a0, .LBB48_6 ; RV64ZVE32F-NEXT: .LBB48_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -5181,7 +5143,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB48_7 ; RV64ZVE32F-NEXT: .LBB48_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v10 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 @@ -5197,7 +5158,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB48_11 ; RV64ZVE32F-NEXT: .LBB48_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -5396,14 +5356,12 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB49_9 ; RV64ZVE32F-NEXT: .LBB49_8: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 ; RV64ZVE32F-NEXT: sd a5, 0(a0) ; RV64ZVE32F-NEXT: .LBB49_9: # %else10 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a0, a4, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: bnez a0, .LBB49_15 @@ -5420,7 +5378,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 8 ; RV64ZVE32F-NEXT: beqz a0, .LBB49_6 ; RV64ZVE32F-NEXT: .LBB49_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -5429,7 +5386,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB49_7 ; RV64ZVE32F-NEXT: .LBB49_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v10 ; RV64ZVE32F-NEXT: slli a0, a0, 3 ; RV64ZVE32F-NEXT: add a0, a1, a0 @@ -5445,7 +5401,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB49_11 ; RV64ZVE32F-NEXT: .LBB49_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 3 @@ -5647,7 +5602,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 32 ; RV64ZVE32F-NEXT: beqz a0, .LBB50_9 ; RV64ZVE32F-NEXT: .LBB50_8: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 32 @@ -5655,7 +5609,6 @@ ; RV64ZVE32F-NEXT: add a0, a1, a0 ; RV64ZVE32F-NEXT: sd a5, 0(a0) ; RV64ZVE32F-NEXT: .LBB50_9: # %else10 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a0, a4, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: bnez a0, .LBB50_15 @@ -5673,7 +5626,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 8 ; RV64ZVE32F-NEXT: beqz a0, .LBB50_6 ; RV64ZVE32F-NEXT: .LBB50_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 32 @@ -5683,7 +5635,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, 16 ; RV64ZVE32F-NEXT: beqz a0, .LBB50_7 ; RV64ZVE32F-NEXT: .LBB50_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a0, v10 ; RV64ZVE32F-NEXT: slli a0, a0, 32 ; RV64ZVE32F-NEXT: srli a0, a0, 29 @@ -5701,7 +5652,6 @@ ; RV64ZVE32F-NEXT: andi a0, a4, -128 ; RV64ZVE32F-NEXT: beqz a0, .LBB50_11 ; RV64ZVE32F-NEXT: .LBB50_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: slli a0, a0, 32 @@ -6417,7 +6367,6 @@ ; RV64ZVE32F-NEXT: .LBB58_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB58_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 @@ -6548,7 +6497,6 @@ ; RV64ZVE32F-NEXT: .LBB59_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB59_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 @@ -6684,7 +6632,6 @@ ; RV64ZVE32F-NEXT: .LBB60_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB60_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -6775,8 +6722,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB61_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma @@ -6787,8 +6734,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v11, (a2) ; RV64ZVE32F-NEXT: .LBB61_6: # %else4 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e16, m1, ta, ma @@ -6807,8 +6754,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB61_10: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma @@ -6821,13 +6768,12 @@ ; RV64ZVE32F-NEXT: .LBB61_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB61_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB61_8 @@ -6846,8 +6792,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 1 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v10, (a2) ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB61_12 @@ -6857,8 +6803,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a1, v9 ; RV64ZVE32F-NEXT: slli a1, a1, 1 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; RV64ZVE32F-NEXT: vse16.v v8, (a0) ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds half, ptr %base, <8 x i16> %idxs @@ -7266,7 +7212,6 @@ ; RV64ZVE32F-NEXT: .LBB68_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB68_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -7396,7 +7341,6 @@ ; RV64ZVE32F-NEXT: .LBB69_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB69_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -7531,7 +7475,6 @@ ; RV64ZVE32F-NEXT: .LBB70_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB70_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -7667,7 +7610,6 @@ ; RV64ZVE32F-NEXT: .LBB71_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB71_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -7798,7 +7740,6 @@ ; RV64ZVE32F-NEXT: .LBB72_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB72_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: slli a2, a2, 2 @@ -7936,7 +7877,6 @@ ; RV64ZVE32F-NEXT: .LBB73_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB73_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v11 ; RV64ZVE32F-NEXT: and a3, a3, a1 @@ -8025,8 +7965,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB74_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m2, ta, ma @@ -8050,8 +7990,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB74_9: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma @@ -8067,8 +8007,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v14, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 8 ; RV64ZVE32F-NEXT: beqz a2, .LBB74_6 @@ -8078,8 +8018,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v10, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB74_7 @@ -8098,8 +8038,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 2 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v12, (a2) ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB74_11 @@ -8109,8 +8049,8 @@ ; RV64ZVE32F-NEXT: vmv.x.s a1, v10 ; RV64ZVE32F-NEXT: slli a1, a1, 2 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m2, ta, ma ; RV64ZVE32F-NEXT: vse32.v v8, (a0) ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds float, ptr %base, <8 x i32> %idxs @@ -8745,7 +8685,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB81_10 ; RV64ZVE32F-NEXT: .LBB81_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -8762,7 +8701,6 @@ ; RV64ZVE32F-NEXT: .LBB81_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB81_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -8771,7 +8709,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB81_8 ; RV64ZVE32F-NEXT: .LBB81_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -8787,7 +8724,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB81_12 ; RV64ZVE32F-NEXT: .LBB81_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 3 @@ -8948,7 +8884,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB82_10 ; RV64ZVE32F-NEXT: .LBB82_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -8965,7 +8900,6 @@ ; RV64ZVE32F-NEXT: .LBB82_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB82_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -8974,7 +8908,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB82_8 ; RV64ZVE32F-NEXT: .LBB82_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -8990,7 +8923,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB82_12 ; RV64ZVE32F-NEXT: .LBB82_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 3 @@ -9155,7 +9087,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB83_10 ; RV64ZVE32F-NEXT: .LBB83_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -9173,7 +9104,6 @@ ; RV64ZVE32F-NEXT: .LBB83_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB83_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: andi a2, a2, 255 @@ -9183,7 +9113,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB83_8 ; RV64ZVE32F-NEXT: .LBB83_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: andi a2, a2, 255 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -9201,7 +9130,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB83_12 ; RV64ZVE32F-NEXT: .LBB83_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: andi a1, a1, 255 @@ -9365,7 +9293,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB84_10 ; RV64ZVE32F-NEXT: .LBB84_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -9382,7 +9309,6 @@ ; RV64ZVE32F-NEXT: .LBB84_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB84_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -9391,7 +9317,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB84_8 ; RV64ZVE32F-NEXT: .LBB84_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -9407,7 +9332,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB84_12 ; RV64ZVE32F-NEXT: .LBB84_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 3 @@ -9569,7 +9493,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB85_10 ; RV64ZVE32F-NEXT: .LBB85_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -9586,7 +9509,6 @@ ; RV64ZVE32F-NEXT: .LBB85_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB85_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -9595,7 +9517,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB85_8 ; RV64ZVE32F-NEXT: .LBB85_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -9611,7 +9532,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB85_12 ; RV64ZVE32F-NEXT: .LBB85_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 3 @@ -9779,7 +9699,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 32 ; RV64ZVE32F-NEXT: beqz a3, .LBB86_10 ; RV64ZVE32F-NEXT: .LBB86_9: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: and a3, a3, a1 @@ -9797,7 +9716,6 @@ ; RV64ZVE32F-NEXT: .LBB86_12: # %else14 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB86_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a3, v9 ; RV64ZVE32F-NEXT: and a3, a3, a1 @@ -9807,7 +9725,6 @@ ; RV64ZVE32F-NEXT: andi a3, a2, 16 ; RV64ZVE32F-NEXT: beqz a3, .LBB86_8 ; RV64ZVE32F-NEXT: .LBB86_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a3, v8 ; RV64ZVE32F-NEXT: and a3, a3, a1 ; RV64ZVE32F-NEXT: slli a3, a3, 3 @@ -9825,7 +9742,6 @@ ; RV64ZVE32F-NEXT: andi a2, a2, -128 ; RV64ZVE32F-NEXT: beqz a2, .LBB86_12 ; RV64ZVE32F-NEXT: .LBB86_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: and a1, a2, a1 @@ -9982,14 +9898,12 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB87_9 ; RV64ZVE32F-NEXT: .LBB87_8: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: fsd fa5, 0(a2) ; RV64ZVE32F-NEXT: .LBB87_9: # %else10 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a2, a1, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: bnez a2, .LBB87_15 @@ -10006,7 +9920,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 8 ; RV64ZVE32F-NEXT: beqz a2, .LBB87_6 ; RV64ZVE32F-NEXT: .LBB87_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -10015,7 +9928,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB87_7 ; RV64ZVE32F-NEXT: .LBB87_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -10031,7 +9943,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB87_11 ; RV64ZVE32F-NEXT: .LBB87_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 3 @@ -10186,14 +10097,12 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB88_9 ; RV64ZVE32F-NEXT: .LBB88_8: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: fsd fa5, 0(a2) ; RV64ZVE32F-NEXT: .LBB88_9: # %else10 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a2, a1, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: bnez a2, .LBB88_15 @@ -10210,7 +10119,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 8 ; RV64ZVE32F-NEXT: beqz a2, .LBB88_6 ; RV64ZVE32F-NEXT: .LBB88_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 3 @@ -10219,7 +10127,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB88_7 ; RV64ZVE32F-NEXT: .LBB88_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 3 ; RV64ZVE32F-NEXT: add a2, a0, a2 @@ -10235,7 +10142,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB88_11 ; RV64ZVE32F-NEXT: .LBB88_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 3 @@ -10393,7 +10299,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 32 ; RV64ZVE32F-NEXT: beqz a2, .LBB89_9 ; RV64ZVE32F-NEXT: .LBB89_8: # %cond.store9 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 32 @@ -10401,7 +10306,6 @@ ; RV64ZVE32F-NEXT: add a2, a0, a2 ; RV64ZVE32F-NEXT: fsd fa5, 0(a2) ; RV64ZVE32F-NEXT: .LBB89_9: # %else10 -; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: andi a2, a1, 64 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 2 ; RV64ZVE32F-NEXT: bnez a2, .LBB89_15 @@ -10419,7 +10323,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 8 ; RV64ZVE32F-NEXT: beqz a2, .LBB89_6 ; RV64ZVE32F-NEXT: .LBB89_13: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v8 ; RV64ZVE32F-NEXT: slli a2, a2, 32 @@ -10429,7 +10332,6 @@ ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB89_7 ; RV64ZVE32F-NEXT: .LBB89_14: # %cond.store7 -; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: slli a2, a2, 32 ; RV64ZVE32F-NEXT: srli a2, a2, 29 @@ -10447,7 +10349,6 @@ ; RV64ZVE32F-NEXT: andi a1, a1, -128 ; RV64ZVE32F-NEXT: beqz a1, .LBB89_11 ; RV64ZVE32F-NEXT: .LBB89_16: # %cond.store13 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v8 ; RV64ZVE32F-NEXT: slli a1, a1, 32 @@ -10724,8 +10625,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB91_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -10735,8 +10636,8 @@ ; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB91_6: # %else4 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -10754,8 +10655,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v11, (a2) ; RV64ZVE32F-NEXT: .LBB91_10: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma @@ -10778,8 +10679,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 9 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB91_15: # %else18 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -10789,8 +10690,8 @@ ; RV64ZVE32F-NEXT: # %bb.16: # %cond.store19 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 10 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v11, (a2) ; RV64ZVE32F-NEXT: .LBB91_17: # %else20 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -10808,8 +10709,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 13 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB91_21: # %else26 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -10819,8 +10720,8 @@ ; RV64ZVE32F-NEXT: # %bb.22: # %cond.store27 ; RV64ZVE32F-NEXT: vmv.x.s a2, v9 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 14 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: .LBB91_23: # %else28 ; RV64ZVE32F-NEXT: lui a2, 1048568 @@ -10831,18 +10732,17 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v9, v9, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v9 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 15 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v8, (a0) ; RV64ZVE32F-NEXT: .LBB91_25: # %else30 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB91_26: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v11, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB91_8 @@ -10859,8 +10759,8 @@ ; RV64ZVE32F-NEXT: .LBB91_28: # %cond.store11 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v11, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 128 ; RV64ZVE32F-NEXT: beqz a2, .LBB91_12 @@ -10869,8 +10769,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 256 ; RV64ZVE32F-NEXT: beqz a2, .LBB91_13 @@ -10885,12 +10785,11 @@ ; RV64ZVE32F-NEXT: bnez a2, .LBB91_14 ; RV64ZVE32F-NEXT: j .LBB91_15 ; RV64ZVE32F-NEXT: .LBB91_31: # %cond.store21 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v10, v8, 11 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; RV64ZVE32F-NEXT: vse8.v v10, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 51 ; RV64ZVE32F-NEXT: bgez a2, .LBB91_19 @@ -10958,8 +10857,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v12, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 1 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_4: # %else2 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -10969,8 +10868,8 @@ ; RV64ZVE32F-NEXT: # %bb.5: # %cond.store3 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 2 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_6: # %else4 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -10988,8 +10887,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v12, v13, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 5 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_10: # %else10 ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma @@ -11012,8 +10911,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v13, v12, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 9 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_15: # %else18 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -11023,8 +10922,8 @@ ; RV64ZVE32F-NEXT: # %bb.16: # %cond.store19 ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 10 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_17: # %else20 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -11032,12 +10931,11 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 4 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_19 ; RV64ZVE32F-NEXT: # %bb.18: # %cond.store21 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 11 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_19: # %else22 ; RV64ZVE32F-NEXT: vsetivli zero, 16, e8, m2, ta, ma @@ -11058,8 +10956,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v12, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 13 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_23: # %else26 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -11080,8 +10978,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 17 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_28: # %else34 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -11091,8 +10989,8 @@ ; RV64ZVE32F-NEXT: # %bb.29: # %cond.store35 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 18 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: .LBB92_30: # %else36 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -11110,8 +11008,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v12, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 21 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_34: # %else42 ; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, m1, ta, ma @@ -11134,8 +11032,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 25 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_39: # %else50 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -11145,8 +11043,8 @@ ; RV64ZVE32F-NEXT: # %bb.40: # %cond.store51 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 26 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_41: # %else52 ; RV64ZVE32F-NEXT: vsetivli zero, 4, e8, mf2, ta, ma @@ -11164,8 +11062,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 29 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_45: # %else58 ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma @@ -11175,8 +11073,8 @@ ; RV64ZVE32F-NEXT: # %bb.46: # %cond.store59 ; RV64ZVE32F-NEXT: vmv.x.s a2, v10 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 30 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: .LBB92_47: # %else60 ; RV64ZVE32F-NEXT: lui a2, 524288 @@ -11187,18 +11085,17 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v10, v10, 1 ; RV64ZVE32F-NEXT: vmv.x.s a1, v10 ; RV64ZVE32F-NEXT: add a0, a0, a1 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 31 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v8, (a0) ; RV64ZVE32F-NEXT: .LBB92_49: # %else62 ; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: .LBB92_50: # %cond.store5 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 3 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 16 ; RV64ZVE32F-NEXT: beqz a2, .LBB92_8 @@ -11215,8 +11112,8 @@ ; RV64ZVE32F-NEXT: .LBB92_52: # %cond.store11 ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 6 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 128 ; RV64ZVE32F-NEXT: beqz a2, .LBB92_12 @@ -11225,8 +11122,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v13, v13, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v13 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v14, v8, 7 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v14, (a2) ; RV64ZVE32F-NEXT: andi a2, a1, 256 ; RV64ZVE32F-NEXT: beqz a2, .LBB92_13 @@ -11243,8 +11140,8 @@ ; RV64ZVE32F-NEXT: .LBB92_55: # %cond.store27 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 14 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 48 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_25 @@ -11253,8 +11150,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 15 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 47 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_26 @@ -11269,12 +11166,11 @@ ; RV64ZVE32F-NEXT: bltz a2, .LBB92_27 ; RV64ZVE32F-NEXT: j .LBB92_28 ; RV64ZVE32F-NEXT: .LBB92_58: # %cond.store37 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v12, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v12 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 19 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 43 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_32 @@ -11291,8 +11187,8 @@ ; RV64ZVE32F-NEXT: .LBB92_60: # %cond.store43 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 22 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 40 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_36 @@ -11301,8 +11197,8 @@ ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 23 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 39 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_37 @@ -11317,12 +11213,11 @@ ; RV64ZVE32F-NEXT: bltz a2, .LBB92_38 ; RV64ZVE32F-NEXT: j .LBB92_39 ; RV64ZVE32F-NEXT: .LBB92_63: # %cond.store53 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v11, v11, 1 ; RV64ZVE32F-NEXT: vmv.x.s a2, v11 ; RV64ZVE32F-NEXT: add a2, a0, a2 -; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vslidedown.vi v12, v8, 27 +; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, m2, ta, ma ; RV64ZVE32F-NEXT: vse8.v v12, (a2) ; RV64ZVE32F-NEXT: slli a2, a1, 35 ; RV64ZVE32F-NEXT: bgez a2, .LBB92_43 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll @@ -43,9 +43,9 @@ ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-NEXT: vse32.v v8, (a0) -; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: addi a0, a0, 4 +; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: ret store <6 x i8> %v, ptr %p @@ -67,9 +67,9 @@ ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret store <12 x i8> %v, ptr %p @@ -91,9 +91,9 @@ ; RV64: # %bb.0: ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret store <6 x i16> %v, ptr %p @@ -160,9 +160,9 @@ ; RV64-NEXT: vmv.s.x v8, a2 ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vse64.v v8, (a0) -; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vslidedown.vi v8, v8, 2 ; RV64-NEXT: addi a0, a0, 8 +; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: ret store <6 x half> %v, ptr %p diff --git a/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll b/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll --- a/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fold-vector-cmp.ll @@ -22,7 +22,6 @@ ; CHECK-V-NEXT: vmslt.vx v0, v8, a1 ; CHECK-V-NEXT: vmv.v.i v8, 0 ; CHECK-V-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vmv.x.s a0, v8 ; CHECK-V-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll --- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll @@ -22,9 +22,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 @@ -172,9 +170,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 @@ -321,9 +317,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 @@ -471,9 +465,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 @@ -560,9 +552,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 @@ -683,9 +673,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 @@ -776,9 +764,7 @@ ; CHECK-NEXT: vslidedown.vi v10, v8, 1 ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v10, v8, 1 -; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vslidedown.vi v8, v9, 1 -; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 2 diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll --- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll @@ -15,9 +15,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vslidedown.vx v10, v10, a0 -; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 ; CHECK-NEXT: vslideup.vi v10, v8, 1 @@ -61,9 +59,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v10, v10, a0 -; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 ; CHECK-NEXT: vslideup.vi v10, v8, 1 @@ -107,9 +103,7 @@ ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v10, v10, a0 -; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 ; CHECK-NEXT: vslideup.vi v10, v8, 1 @@ -152,9 +146,7 @@ ; CHECK-NEXT: vmerge.vim v10, v9, 1, v0 ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a0, -1 -; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma ; CHECK-NEXT: vslidedown.vx v10, v10, a0 -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v8, v9, 1, v0 ; CHECK-NEXT: vslideup.vi v10, v8, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll --- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll @@ -198,11 +198,9 @@ ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 -; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma ; CHECK-NEXT: vslidedown.vx v8, v8, a0 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.x v8, a0 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll --- a/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll +++ b/llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll @@ -566,7 +566,6 @@ ; RV32MV-NEXT: vand.vx v8, v8, a1 ; RV32MV-NEXT: vmsltu.vv v0, v12, v8 ; RV32MV-NEXT: vmerge.vim v8, v10, -1, v0 -; RV32MV-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV32MV-NEXT: vslidedown.vi v9, v8, 2 ; RV32MV-NEXT: vmv.x.s a1, v9 ; RV32MV-NEXT: slli a2, a1, 21 @@ -633,7 +632,6 @@ ; RV64MV-NEXT: vmerge.vim v8, v10, -1, v0 ; RV64MV-NEXT: vmv.x.s a1, v8 ; RV64MV-NEXT: andi a1, a1, 2047 -; RV64MV-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64MV-NEXT: vslidedown.vi v9, v8, 1 ; RV64MV-NEXT: vmv.x.s a2, v9 ; RV64MV-NEXT: andi a2, a2, 2047