diff --git a/llvm/include/llvm/CodeGen/AccelTable.h b/llvm/include/llvm/CodeGen/AccelTable.h --- a/llvm/include/llvm/CodeGen/AccelTable.h +++ b/llvm/include/llvm/CodeGen/AccelTable.h @@ -161,8 +161,8 @@ StringEntries Entries; HashFn *Hash; - uint32_t BucketCount; - uint32_t UniqueHashCount; + uint32_t BucketCount = 0; + uint32_t UniqueHashCount = 0; HashList Hashes; BucketList Buckets; diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h --- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h +++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h @@ -95,7 +95,7 @@ /// \{ /// The current call site index being processed, if any. 0 if none. - unsigned CurCallSite; + unsigned CurCallSite = 0; /// \} @@ -106,11 +106,11 @@ // go into .eh_frame only, while others go into .debug_frame only. /// True if debugging information is available in this module. - bool DbgInfoAvailable; + bool DbgInfoAvailable = false; /// True if this module is being built for windows/msvc, and uses floating /// point. This is used to emit an undefined reference to _fltused. - bool UsesMSVCFloatingPoint; + bool UsesMSVCFloatingPoint = false; /// Maps IR Functions to their corresponding MachineFunctions. DenseMap> MachineFunctions; diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -168,7 +168,7 @@ SmallVector, 16> AdjK; // Node to Index from ScheduleDAGTopologicalSort std::vector *Node2Idx; - unsigned NumPaths; + unsigned NumPaths = 0u; static unsigned MaxPaths; public: @@ -464,7 +464,7 @@ /// processor resource masks. There is exactly one element per each processor /// resource declared by the scheduling model. llvm::SmallVector ProcResourceMasks; - int InitiationInterval; + int InitiationInterval = 0; /// The number of micro operations that can be scheduled at a cycle. int IssueWidth; diff --git a/llvm/include/llvm/CodeGen/RegisterPressure.h b/llvm/include/llvm/CodeGen/RegisterPressure.h --- a/llvm/include/llvm/CodeGen/RegisterPressure.h +++ b/llvm/include/llvm/CodeGen/RegisterPressure.h @@ -272,7 +272,7 @@ using RegSet = SparseSet; RegSet Regs; - unsigned NumRegUnits; + unsigned NumRegUnits = 0u; unsigned getSparseIndexFromReg(Register Reg) const { if (Reg.isVirtual()) diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h --- a/llvm/include/llvm/CodeGen/ScheduleDAG.h +++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h @@ -93,7 +93,7 @@ /// The time associated with this edge. Often this is just the value of the /// Latency field of the predecessor, however advanced models may provide /// additional information about specific edges. - unsigned Latency; + unsigned Latency = 0u; public: /// Constructs a null SDep. This is only for use by container classes which diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -470,7 +470,7 @@ /// We do not place that under `#if LLVM_ENABLE_ABI_BREAKING_CHECKS` /// intentionally because it adds unneeded complexity without noticeable /// benefits (see discussion with @thakis in D120714). - uint16_t PersistentId; + uint16_t PersistentId = 0xffff; protected: // We define a set of mini-helper classes to help us interpret the bits in our diff --git a/llvm/include/llvm/CodeGen/TileShapeInfo.h b/llvm/include/llvm/CodeGen/TileShapeInfo.h --- a/llvm/include/llvm/CodeGen/TileShapeInfo.h +++ b/llvm/include/llvm/CodeGen/TileShapeInfo.h @@ -87,8 +87,8 @@ static constexpr int64_t InvalidImmShape = -1; MachineOperand *Row; MachineOperand *Col; - int64_t RowImm; - int64_t ColImm; + int64_t RowImm = -1; + int64_t ColImm = -1; }; } // namespace llvm diff --git a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp --- a/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AccelTable.cpp @@ -194,8 +194,8 @@ uint32_t CompUnitCount; uint32_t LocalTypeUnitCount = 0; uint32_t ForeignTypeUnitCount = 0; - uint32_t BucketCount; - uint32_t NameCount; + uint32_t BucketCount = 0; + uint32_t NameCount = 0; uint32_t AbbrevTableSize = 0; uint32_t AugmentationStringSize = sizeof(AugmentationString); char AugmentationString[8] = {'L', 'L', 'V', 'M', '0', '7', '0', '0'}; diff --git a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp --- a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp +++ b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp @@ -137,7 +137,8 @@ Instruction *Real; Instruction *Imag; - ComplexDeinterleavingRotation Rotation; + ComplexDeinterleavingRotation Rotation = + ComplexDeinterleavingRotation::Rotation_0; SmallVector Operands; Value *ReplacementNode = nullptr; diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp --- a/llvm/lib/CodeGen/GlobalMerge.cpp +++ b/llvm/lib/CodeGen/GlobalMerge.cpp @@ -156,7 +156,7 @@ /// Whether we should merge global variables that have external linkage. bool MergeExternalGlobals = false; - bool IsMachO; + bool IsMachO = false; bool doMerge(SmallVectorImpl &Globals, Module &M, bool isConst, unsigned AddrSpace) const; diff --git a/llvm/lib/CodeGen/InterleavedAccessPass.cpp b/llvm/lib/CodeGen/InterleavedAccessPass.cpp --- a/llvm/lib/CodeGen/InterleavedAccessPass.cpp +++ b/llvm/lib/CodeGen/InterleavedAccessPass.cpp @@ -103,7 +103,7 @@ const TargetLowering *TLI = nullptr; /// The maximum supported interleave factor. - unsigned MaxFactor; + unsigned MaxFactor = 0u; /// Transform an interleaved load into target specific intrinsics. bool lowerInterleavedLoad(LoadInst *LI, diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -69,7 +69,7 @@ /// LiveRegDefs - A set of physical registers and their definition /// that are "live". These nodes must be scheduled before any other nodes that /// modifies the registers can be scheduled. - unsigned NumLiveRegs; + unsigned NumLiveRegs = 0u; std::vector LiveRegDefs; std::vector LiveRegCycles; diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -156,16 +156,16 @@ unsigned CurCycle = 0; /// MinAvailableCycle - Cycle of the soonest available instruction. - unsigned MinAvailableCycle; + unsigned MinAvailableCycle = ~0u; /// IssueCount - Count instructions issued in this cycle /// Currently valid only for bottom-up scheduling. - unsigned IssueCount; + unsigned IssueCount = 0u; /// LiveRegDefs - A set of physical registers and their definition /// that are "live". These nodes must be scheduled before any other nodes that /// modifies the registers can be scheduled. - unsigned NumLiveRegs; + unsigned NumLiveRegs = 0u; std::unique_ptr LiveRegDefs; std::unique_ptr LiveRegGens; diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/lib/CodeGen/SplitKit.h --- a/llvm/lib/CodeGen/SplitKit.h +++ b/llvm/lib/CodeGen/SplitKit.h @@ -151,13 +151,13 @@ /// NumGapBlocks - Number of duplicate entries in UseBlocks for blocks where /// the live range has a gap. - unsigned NumGapBlocks; + unsigned NumGapBlocks = 0u; /// ThroughBlocks - Block numbers where CurLI is live through without uses. BitVector ThroughBlocks; /// NumThroughBlocks - Number of live-through blocks. - unsigned NumThroughBlocks; + unsigned NumThroughBlocks = 0u; // Sumarize statistics by counting instructions using CurLI. void analyzeUses();