Index: libc/cmake/modules/LLVMLibCArchitectures.cmake
===================================================================
--- libc/cmake/modules/LLVMLibCArchitectures.cmake
+++ libc/cmake/modules/LLVMLibCArchitectures.cmake
@@ -150,10 +150,12 @@
   set(LIBC_TARGET_ARCHITECTURE_IS_AARCH64 TRUE)
 elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "x86_64")
   set(LIBC_TARGET_ARCHITECTURE_IS_X86 TRUE)
-elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv32")
-  set(LIBC_TARGET_ARCHITECTURE_IS_RISCV32 TRUE)
 elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv64")
   set(LIBC_TARGET_ARCHITECTURE_IS_RISCV64 TRUE)
+  set(LIBC_TARGET_ARCHITECTURE "riscv")
+elseif(LIBC_TARGET_ARCHITECTURE STREQUAL "riscv32")
+  set(LIBC_TARGET_ARCHITECTURE_IS_RISCV32 TRUE)
+  set(LIBC_TARGET_ARCHITECTURE "riscv")
 else()
   message(FATAL_ERROR
           "Unsupported libc target architecture ${LIBC_TARGET_ARCHITECTURE}")
Index: libc/cmake/modules/LLVMLibCTestRules.cmake
===================================================================
--- libc/cmake/modules/LLVMLibCTestRules.cmake
+++ libc/cmake/modules/LLVMLibCTestRules.cmake
@@ -164,6 +164,7 @@
       PRIVATE ${LIBC_UNITTEST_COMPILE_OPTIONS}
     )
   endif()
+  target_link_options(${fq_build_target_name} PRIVATE -static)
   if(NOT LIBC_UNITTEST_CXX_STANDARD)
     set(LIBC_UNITTEST_CXX_STANDARD ${CMAKE_CXX_STANDARD})
   endif()
Index: libc/config/linux/app.h
===================================================================
--- libc/config/linux/app.h
+++ libc/config/linux/app.h
@@ -37,7 +37,7 @@
 
 #if defined(LIBC_TARGET_ARCH_IS_X86_64) ||                                     \
     defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                    \
-    defined(LIBC_TARGET_ARCH_IS_RISCV64)
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 // At the language level, argc is an int. But we use uint64_t as the x86_64
 // ABI specifies it as an 8 byte value. Likewise, in the ARM64 ABI, arguments
 // are usually passed in registers.  x0 is a doubleword register, so this is
Index: libc/src/__support/FPUtil/FEnvImpl.h
===================================================================
--- libc/src/__support/FPUtil/FEnvImpl.h
+++ libc/src/__support/FPUtil/FEnvImpl.h
@@ -30,10 +30,8 @@
 #include "x86_64/FEnvImpl.h"
 #elif defined(LIBC_TARGET_ARCH_IS_ARM)
 #include "arm/FEnvImpl.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV32)
-#include "riscv32/FEnvImpl.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/FEnvImpl.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/FEnvImpl.h"
 #else
 
 namespace __llvm_libc::fputil {
Index: libc/src/__support/FPUtil/FMA.h
===================================================================
--- libc/src/__support/FPUtil/FMA.h
+++ libc/src/__support/FPUtil/FMA.h
@@ -18,8 +18,8 @@
 #include "x86_64/FMA.h"
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
 #include "aarch64/FMA.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/FMA.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/FMA.h"
 #elif defined(LIBC_TARGET_ARCH_IS_GPU)
 #include "gpu/FMA.h"
 #endif
Index: libc/src/__support/FPUtil/riscv/FEnvImpl.h
===================================================================
--- libc/src/__support/FPUtil/riscv/FEnvImpl.h
+++ libc/src/__support/FPUtil/riscv/FEnvImpl.h
@@ -1,4 +1,4 @@
-//===-- riscv64 floating point env manipulation functions -------*- C++ -*-===//
+//===-- riscv floating point env manipulation functions ---------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
-#define LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
+#ifndef LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_FENVIMPL_H
+#define LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_FENVIMPL_H
 
 #include "src/__support/FPUtil/FPBits.h"
 #include "src/__support/macros/attributes.h" // For LIBC_INLINE_ASM
@@ -177,4 +177,4 @@
 } // namespace fputil
 } // namespace __llvm_libc
 
-#endif // LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_FENVIMPL_H
+#endif // LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_FENVIMPL_H
Index: libc/src/__support/FPUtil/riscv/FMA.h
===================================================================
--- libc/src/__support/FPUtil/riscv/FMA.h
+++ libc/src/__support/FPUtil/riscv/FMA.h
@@ -1,4 +1,4 @@
-//===-- RISCV64 implementations of the fma function -------------*- C++ -*-===//
+//===-- RISCV implementations of the fma function ---------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,14 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_FMA_H
-#define LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_FMA_H
+#ifndef LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_FMA_H
+#define LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_FMA_H
 
 #include "src/__support/macros/attributes.h" // LIBC_INLINE
 #include "src/__support/macros/properties/architectures.h"
 #include "src/__support/macros/properties/cpu_features.h" // LIBC_TARGET_CPU_HAS_FMA
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid include"
 #endif
 
@@ -47,4 +47,4 @@
 } // namespace fputil
 } // namespace __llvm_libc
 
-#endif // LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_FMA_H
+#endif // LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_FMA_H
Index: libc/src/__support/FPUtil/riscv/sqrt.h
===================================================================
--- libc/src/__support/FPUtil/riscv/sqrt.h
+++ libc/src/__support/FPUtil/riscv/sqrt.h
@@ -6,13 +6,13 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_SQRT_H
-#define LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_SQRT_H
+#ifndef LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_SQRT_H
+#define LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_SQRT_H
 
 #include "src/__support/common.h"
 #include "src/__support/macros/properties/architectures.h"
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid include"
 #endif
 
@@ -36,4 +36,4 @@
 } // namespace fputil
 } // namespace __llvm_libc
 
-#endif // LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV64_SQRT_H
+#endif // LLVM_LIBC_SRC_SUPPORT_FPUTIL_RISCV_SQRT_H
Index: libc/src/__support/FPUtil/sqrt.h
===================================================================
--- libc/src/__support/FPUtil/sqrt.h
+++ libc/src/__support/FPUtil/sqrt.h
@@ -15,8 +15,8 @@
 #include "x86_64/sqrt.h"
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64)
 #include "aarch64/sqrt.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/sqrt.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/sqrt.h"
 #else
 #include "generic/sqrt.h"
 
Index: libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
===================================================================
--- libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
+++ libc/src/__support/OSUtil/linux/riscv/CMakeLists.txt
@@ -1,5 +1,5 @@
 add_header_library(
-  linux_riscv64_util
+  linux_riscv_util
   HDRS
     syscall.h
   DEPENDS
Index: libc/src/__support/OSUtil/linux/riscv/syscall.h
===================================================================
--- libc/src/__support/OSUtil/linux/riscv/syscall.h
+++ libc/src/__support/OSUtil/linux/riscv/syscall.h
@@ -1,4 +1,4 @@
-//===--------- inline implementation of riscv64 syscalls ----------* C++ *-===//
+//===--------- inline implementation of riscv syscalls ------------* C++ *-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_LIBC_SRC_SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
-#define LLVM_LIBC_SRC_SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
+#ifndef LLVM_LIBC_SRC_SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
+#define LLVM_LIBC_SRC_SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
 
 #include "src/__support/common.h"
 
@@ -107,4 +107,4 @@
 #undef REGISTER_CONSTRAINT_5
 #undef REGISTER_CONSTRAINT_6
 
-#endif // LLVM_LIBC_SRC_SUPPORT_OSUTIL_LINUX_RISCV64_SYSCALL_H
+#endif // LLVM_LIBC_SRC_SUPPORT_OSUTIL_LINUX_RISCV_SYSCALL_H
Index: libc/src/__support/OSUtil/linux/syscall.h
===================================================================
--- libc/src/__support/OSUtil/linux/syscall.h
+++ libc/src/__support/OSUtil/linux/syscall.h
@@ -19,8 +19,8 @@
 #include "aarch64/syscall.h"
 #elif defined(LIBC_TARGET_ARCH_IS_ARM)
 #include "arm/syscall.h"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
-#include "riscv64/syscall.h"
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
+#include "riscv/syscall.h"
 #endif
 
 namespace __llvm_libc {
Index: libc/src/__support/macros/properties/architectures.h
===================================================================
--- libc/src/__support/macros/properties/architectures.h
+++ libc/src/__support/macros/properties/architectures.h
@@ -45,7 +45,7 @@
 #define LIBC_TARGET_ARCH_IS_AARCH64
 #endif
 
-#if (defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_ARM))
+#if defined(LIBC_TARGET_ARCH_IS_AARCH64) || defined(LIBC_TARGET_ARCH_IS_ARM)
 #define LIBC_TARGET_ARCH_IS_ANY_ARM
 #endif
 
@@ -57,8 +57,7 @@
 #define LIBC_TARGET_ARCH_IS_RISCV32
 #endif
 
-#if (defined(LIBC_TARGET_ARCH_IS_RISCV64) ||                                   \
-     defined(LIBC_TARGET_ARCH_IS_RISCV32))
+#if defined(LIBC_TARGET_ARCH_IS_RISCV64) || defined(LIBC_TARGET_ARCH_IS_RISCV32)
 #define LIBC_TARGET_ARCH_IS_ANY_RISCV
 #endif
 
Index: libc/src/__support/threads/linux/thread.cpp
===================================================================
--- libc/src/__support/threads/linux/thread.cpp
+++ libc/src/__support/threads/linux/thread.cpp
@@ -57,7 +57,7 @@
 
 #ifdef LIBC_TARGET_ARCH_IS_AARCH64
 #define CLONE_RESULT_REGISTER "x0"
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #define CLONE_RESULT_REGISTER "t0"
 #elif defined(LIBC_TARGET_ARCH_IS_X86_64)
 #define CLONE_RESULT_REGISTER "rax"
@@ -169,7 +169,7 @@
   // is set to the stack pointer where start args are stored. So, we fetch
   // from there.
   return reinterpret_cast<uintptr_t>(__builtin_frame_address(1));
-#elif defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // The current frame pointer is the previous stack pointer where the start
   // args are stored.
   return reinterpret_cast<uintptr_t>(__builtin_frame_address(0));
@@ -306,7 +306,7 @@
       tls.tp           // The thread pointer value for the new thread.
   );
 #elif defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                  \
-    defined(LIBC_TARGET_ARCH_IS_RISCV64)
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   long register clone_result asm(CLONE_RESULT_REGISTER);
   clone_result = __llvm_libc::syscall_impl<long>(
       SYS_clone, CLONE_SYSCALL_FLAGS, adjusted_stack,
Index: libc/src/__support/threads/thread.h
===================================================================
--- libc/src/__support/threads/thread.h
+++ libc/src/__support/threads/thread.h
@@ -41,7 +41,7 @@
 
 #if (defined(LIBC_TARGET_ARCH_IS_AARCH64) ||                                   \
      defined(LIBC_TARGET_ARCH_IS_X86_64) ||                                    \
-     defined(LIBC_TARGET_ARCH_IS_RISCV64))
+     defined(LIBC_TARGET_ARCH_IS_ANY_RISCV))
 constexpr unsigned int STACK_ALIGNMENT = 16;
 #endif
 // TODO: Provide stack alignment requirements for other architectures.
Index: libc/src/setjmp/riscv/longjmp.cpp
===================================================================
--- libc/src/setjmp/riscv/longjmp.cpp
+++ libc/src/setjmp/riscv/longjmp.cpp
@@ -12,7 +12,7 @@
 
 #include <setjmp.h>
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid file include"
 #endif
 
Index: libc/src/setjmp/riscv/setjmp.cpp
===================================================================
--- libc/src/setjmp/riscv/setjmp.cpp
+++ libc/src/setjmp/riscv/setjmp.cpp
@@ -11,7 +11,7 @@
 
 #include <setjmp.h>
 
-#if !defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if !defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
 #error "Invalid file include"
 #endif
 
Index: libc/test/src/fenv/enabled_exceptions_test.cpp
===================================================================
--- libc/test/src/fenv/enabled_exceptions_test.cpp
+++ libc/test/src/fenv/enabled_exceptions_test.cpp
@@ -21,7 +21,8 @@
 // This test enables an exception and verifies that raising that exception
 // triggers SIGFPE.
 TEST(LlvmLibcExceptionStatusTest, RaiseAndCrash) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) ||                                    \
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // Few Arm HW implementations do not trap exceptions. We skip this test
   // completely on such HW.
   //
Index: libc/test/src/fenv/feenableexcept_test.cpp
===================================================================
--- libc/test/src/fenv/feenableexcept_test.cpp
+++ libc/test/src/fenv/feenableexcept_test.cpp
@@ -16,7 +16,8 @@
 #include <fenv.h>
 
 TEST(LlvmLibcFEnvTest, EnableTest) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) ||                                    \
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // Few Arm HW implementations do not trap exceptions. We skip this test
   // completely on such HW.
   //
Index: libc/test/src/fenv/feholdexcept_test.cpp
===================================================================
--- libc/test/src/fenv/feholdexcept_test.cpp
+++ libc/test/src/fenv/feholdexcept_test.cpp
@@ -16,7 +16,8 @@
 #include <fenv.h>
 
 TEST(LlvmLibcFEnvTest, RaiseAndCrash) {
-#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || defined(LIBC_TARGET_ARCH_IS_RISCV64)
+#if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) ||                                    \
+    defined(LIBC_TARGET_ARCH_IS_ANY_RISCV)
   // Few Arm HW implementations do not trap exceptions. We skip this test
   // completely on such HW.
   //