Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -221,6 +221,9 @@
   bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
+  bool expandTrunc(MCInst &Inst, bool is64Bit, SMLoc IDLoc,
+                   SmallVectorImpl<MCInst> &Instructions);
+
   bool expandUlw(MCInst &Inst, SMLoc IDLoc,
                  SmallVectorImpl<MCInst> &Instructions);
 
@@ -2070,6 +2073,13 @@
   case Mips::DUDivMacro:
     return expandDiv(Inst, IDLoc, Instructions, true, false) ? MER_Fail
                                                              : MER_Success;
+  case Mips::TruncWordSingle:
+    return expandTrunc(Inst, false, IDLoc, Instructions) ? MER_Fail
+                                                         : MER_Success;
+  case Mips::TruncWordDouble:
+    return expandTrunc(Inst, true, IDLoc, Instructions) ? MER_Fail
+                                                        : MER_Success;
+
   case Mips::Ulh:
     return expandUlh(Inst, true, IDLoc, Instructions) ? MER_Fail : MER_Success;
   case Mips::Ulhu:
@@ -3060,6 +3070,22 @@
   return false;
 }
 
+bool MipsAsmParser::expandTrunc(MCInst &Inst, bool is64Bit, SMLoc IDLoc,
+                                SmallVectorImpl<MCInst> &Instructions) {
+
+  assert(Inst.getNumOperands() == 3 && "Invalid operand count");
+  assert(Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg() &&
+         Inst.getOperand(2).isReg() && "Invalid instruction operand.");
+
+  unsigned FirstReg = Inst.getOperand(0).getReg();
+  unsigned SecondReg = Inst.getOperand(1).getReg();
+
+  emitRR(is64Bit ? Mips::TRUNC_W_D32 : Mips::TRUNC_W_S, FirstReg, SecondReg,
+         IDLoc, Instructions);
+
+  return false;
+}
+
 bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc,
                               SmallVectorImpl<MCInst> &Instructions) {
   if (hasMips32r6() || hasMips64r6()) {
Index: lib/Target/Mips/MipsInstrFPU.td
===================================================================
--- lib/Target/Mips/MipsInstrFPU.td
+++ lib/Target/Mips/MipsInstrFPU.td
@@ -553,6 +553,17 @@
 def ExtractElementF64 : ExtractElementF64Base<AFGR64Opnd>, FGR_32, HARDFLOAT;
 def ExtractElementF64_64 : ExtractElementF64Base<FGR64Opnd>, FGR_64, HARDFLOAT;
 
+def TruncWordSingle : MipsAsmPseudoInst<(outs), (ins FGR32Opnd
+                                                 : $fd, FGR32Opnd
+                                                 : $fs, GPR32Opnd
+                                                 : $rs),
+                                        "trunc.w.s\t$fd, $fs, $rs">;
+def TruncWordDouble : MipsAsmPseudoInst<(outs), (ins FGR32Opnd
+                                                 : $fd, AFGR64Opnd
+                                                 : $fs, GPR32Opnd
+                                                 : $rs),
+                                        "trunc.w.d\t$fd, $fs, $rs">;
+
 //===----------------------------------------------------------------------===//
 // InstAliases.
 //===----------------------------------------------------------------------===//
Index: test/MC/Mips/mips32/valid.s
===================================================================
--- test/MC/Mips/mips32/valid.s
+++ test/MC/Mips/mips32/valid.s
@@ -199,6 +199,8 @@
         tnei      $12,-29647
         trunc.w.d $f22,$f15
         trunc.w.s $f28,$f30
+        trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
+        trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: 
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]
 
Index: test/MC/Mips/mips64/valid.s
===================================================================
--- test/MC/Mips/mips64/valid.s
+++ test/MC/Mips/mips64/valid.s
@@ -283,8 +283,10 @@
         tnei      $12,-29647
         trunc.l.d $f23,$f23
         trunc.l.s $f28,$f31
-        trunc.w.d $f22,$f15
-        trunc.w.s $f28,$f30
+        trunc.w.d $f22,$f15            
+        trunc.w.s $f28,$f30            
+        trunc.w.d $f4,$f6,$4           # CHECK: trunc.w.d $f4, $f6     # encoding: [0x46,0x20,0x31,0x0d]
+        trunc.w.s $f4,$f6,$4           # CHECK: trunc.w.s $f4, $f6     # encoding: [0x46,0x00,0x31,0x0d]
         xor       $s2,$a0,$s8
         xor       $2, 4                # CHECK: xori $2, $2, 4         # encoding: [0x38,0x42,0x00,0x04]