Index: llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -86,7 +86,7 @@
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def FLI_S : FPUnaryOp_imm<0b1111000, 0b00001, 0b000, OPC_OP_FP, (outs FPR32:$rd),
             (ins loadfpimm:$imm), "fli.s", "$rd, $imm">,
-            Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
+            Sched<[WriteFMovI32ToF32]>;
 
 let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {
 def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, /*Commutable*/ 1>;
@@ -94,9 +94,9 @@
 }
 
 def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">,
-               Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
+               Sched<[WriteFCvtF32ToF32, ReadFCvtF32ToF32]>;
 def FROUNDNX_S : FPUnaryOp_r_frm<0b0100000, 0b00101, FPR32, FPR32, "froundnx.s">,
-                 Sched<[WriteFCvtF64ToF32, ReadFCvtF64ToF32]>;
+                 Sched<[WriteFCvtF32ToF32, ReadFCvtF32ToF32]>;
 
 let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in {
 def FLTQ_S : FPCmp_rr<0b1010000, 0b101, "fltq.s", FPR32>;
@@ -108,7 +108,7 @@
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def FLI_D : FPUnaryOp_imm<0b1111001, 0b00001, 0b000, OPC_OP_FP, (outs FPR64:$rd),
             (ins loadfpimm:$imm), "fli.d", "$rd, $imm">,
-            Sched<[WriteFMovI64ToF64, ReadFMovI64ToF64]>;
+            Sched<[WriteFMovI64ToF64]>;
 
 let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
 def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, /*Commutable*/ 1>;
@@ -116,9 +116,9 @@
 }
 
 def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,
-               Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
+               Sched<[WriteFCvtF64ToF64, ReadFCvtF64ToF64]>;
 def FROUNDNX_D : FPUnaryOp_r_frm<0b0100001, 0b00101, FPR64, FPR64, "froundnx.d">,
-                 Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
+                 Sched<[WriteFCvtF64ToF64, ReadFCvtF64ToF64]>;
 
 def FCVTMOD_W_D
     : FPUnaryOp_r_rtz<0b1100001, 0b01000, GPR, FPR64, "fcvtmod.w.d">,
@@ -148,7 +148,7 @@
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
 def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, OPC_OP_FP, (outs FPR16:$rd),
             (ins loadfpimm:$imm), "fli.h", "$rd, $imm">,
-            Sched<[WriteFMovI16ToF16, ReadFMovI16ToF16]>;
+            Sched<[WriteFMovI16ToF16]>;
 
 let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
 let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {
@@ -157,9 +157,9 @@
 }
 
 def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">,
-               Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+               Sched<[WriteFCvtF16ToF16, ReadFCvtF16ToF16]>;
 def FROUNDNX_H : FPUnaryOp_r_frm<0b0100010, 0b00101, FPR16, FPR16, "froundnx.h">,
-                 Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+                 Sched<[WriteFCvtF16ToF16, ReadFCvtF16ToF16]>;
 
 let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {
 def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16>;
Index: llvm/lib/Target/RISCV/RISCVSchedRocket.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -244,6 +244,7 @@
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfh;
 defm : UnsupportedSchedSFB;
 }
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -239,5 +239,6 @@
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfh;
 }
Index: llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
+++ llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td
@@ -203,5 +203,6 @@
 defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
+defm : UnsupportedSchedZfa;
 defm : UnsupportedSchedZfh;
 }
Index: llvm/lib/Target/RISCV/RISCVSchedule.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedule.td
+++ llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -76,6 +76,9 @@
 def WriteFCvtF32ToF16  : SchedWrite;
 def WriteFCvtF16ToF64  : SchedWrite;
 def WriteFCvtF64ToF16  : SchedWrite;
+def WriteFCvtF32ToF32  : SchedWrite;
+def WriteFCvtF64ToF64  : SchedWrite;
+def WriteFCvtF16ToF16  : SchedWrite;
 
 def WriteFClass16   : SchedWrite;    // 16-bit floating point classify
 def WriteFClass32   : SchedWrite;    // 32-bit floating point classify
@@ -182,6 +185,9 @@
 def ReadFCvtF32ToF16     : SchedRead;
 def ReadFCvtF16ToF64     : SchedRead;
 def ReadFCvtF64ToF16     : SchedRead;
+def ReadFCvtF32ToF32     : SchedRead;
+def ReadFCvtF64ToF64     : SchedRead;
+def ReadFCvtF16ToF16     : SchedRead;
 def ReadFClass16         : SchedRead;
 def ReadFClass32         : SchedRead;
 def ReadFClass64         : SchedRead;
@@ -240,6 +246,18 @@
 } // Unsupported = true
 }
 
+multiclass UnsupportedSchedZfa {
+let Unsupported = true in {
+def : WriteRes<WriteFCvtF32ToF32, []>;
+def : WriteRes<WriteFCvtF64ToF64, []>;
+def : WriteRes<WriteFCvtF16ToF16, []>;
+
+def : ReadAdvance<ReadFCvtF32ToF32, 0>;
+def : ReadAdvance<ReadFCvtF64ToF64, 0>;
+def : ReadAdvance<ReadFCvtF16ToF16, 0>;
+} // Unsupported = true
+}
+
 // Include the scheduler resources for other instruction extensions.
 include "RISCVScheduleZb.td"
 include "RISCVScheduleV.td"