diff --git a/llvm/lib/CodeGen/MachineLICM.cpp b/llvm/lib/CodeGen/MachineLICM.cpp --- a/llvm/lib/CodeGen/MachineLICM.cpp +++ b/llvm/lib/CodeGen/MachineLICM.cpp @@ -59,49 +59,44 @@ #define DEBUG_TYPE "machinelicm" static cl::opt -AvoidSpeculation("avoid-speculation", - cl::desc("MachineLICM should avoid speculation"), - cl::init(true), cl::Hidden); - -static cl::opt -HoistCheapInsts("hoist-cheap-insts", - cl::desc("MachineLICM should hoist even cheap instructions"), - cl::init(false), cl::Hidden); - -static cl::opt -HoistConstStores("hoist-const-stores", - cl::desc("Hoist invariant stores"), - cl::init(true), cl::Hidden); + AvoidSpeculation("avoid-speculation", + cl::desc("MachineLICM should avoid speculation"), + cl::init(true), cl::Hidden); + +static cl::opt HoistCheapInsts( + "hoist-cheap-insts", + cl::desc("MachineLICM should hoist even cheap instructions"), + cl::init(false), cl::Hidden); + +static cl::opt HoistConstStores("hoist-const-stores", + cl::desc("Hoist invariant stores"), + cl::init(true), cl::Hidden); // The default threshold of 100 (i.e. if target block is 100 times hotter) // is based on empirical data on a single target and is subject to tuning. -static cl::opt -BlockFrequencyRatioThreshold("block-freq-ratio-threshold", - cl::desc("Do not hoist instructions if target" - "block is N times hotter than the source."), - cl::init(100), cl::Hidden); +static cl::opt BlockFrequencyRatioThreshold( + "block-freq-ratio-threshold", + cl::desc("Do not hoist instructions if target" + "block is N times hotter than the source."), + cl::init(100), cl::Hidden); enum class UseBFI { None, PGO, All }; -static cl::opt -DisableHoistingToHotterBlocks("disable-hoisting-to-hotter-blocks", - cl::desc("Disable hoisting instructions to" - " hotter blocks"), - cl::init(UseBFI::PGO), cl::Hidden, - cl::values(clEnumValN(UseBFI::None, "none", - "disable the feature"), - clEnumValN(UseBFI::PGO, "pgo", - "enable the feature when using profile data"), - clEnumValN(UseBFI::All, "all", - "enable the feature with/wo profile data"))); - -STATISTIC(NumHoisted, - "Number of machine instructions hoisted out of loops"); +static cl::opt DisableHoistingToHotterBlocks( + "disable-hoisting-to-hotter-blocks", + cl::desc("Disable hoisting instructions to" + " hotter blocks"), + cl::init(UseBFI::PGO), cl::Hidden, + cl::values(clEnumValN(UseBFI::None, "none", "disable the feature"), + clEnumValN(UseBFI::PGO, "pgo", + "enable the feature when using profile data"), + clEnumValN(UseBFI::All, "all", + "enable the feature with/wo profile data"))); + +STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops"); STATISTIC(NumLowRP, "Number of instructions hoisted in low reg pressure situation"); -STATISTIC(NumHighLatency, - "Number of high latency instructions hoisted"); -STATISTIC(NumCSEed, - "Number of hoisted machine instructions CSEed"); +STATISTIC(NumHighLatency, "Number of high latency instructions hoisted"); +STATISTIC(NumCSEed, "Number of hoisted machine instructions CSEed"); STATISTIC(NumPostRAHoisted, "Number of machine instructions hoisted out of loops post regalloc"); STATISTIC(NumStoreConst, @@ -111,182 +106,177 @@ namespace { - class MachineLICMBase : public MachineFunctionPass { - const TargetInstrInfo *TII; - const TargetLoweringBase *TLI; - const TargetRegisterInfo *TRI; - const MachineFrameInfo *MFI; - MachineRegisterInfo *MRI; - TargetSchedModel SchedModel; - bool PreRegAlloc; - bool HasProfileData; - - // Various analyses that we use... - AliasAnalysis *AA; // Alias analysis info. - MachineBlockFrequencyInfo *MBFI; // Machine block frequncy info - MachineLoopInfo *MLI; // Current MachineLoopInfo - MachineDominatorTree *DT; // Machine dominator tree for the cur loop - - // State that is updated as we process loops - bool Changed; // True if a loop is changed. - bool FirstInLoop; // True if it's the first LICM in the loop. - MachineLoop *CurLoop; // The current loop we are working on. - MachineBasicBlock *CurPreheader; // The preheader for CurLoop. - - // Exit blocks for CurLoop. - SmallVector ExitBlocks; - - bool isExitBlock(const MachineBasicBlock *MBB) const { - return is_contained(ExitBlocks, MBB); - } +class MachineLICMBase : public MachineFunctionPass { + const TargetInstrInfo *TII = nullptr; + const TargetLoweringBase *TLI = nullptr; + const TargetRegisterInfo *TRI = nullptr; + const MachineFrameInfo *MFI = nullptr; + MachineRegisterInfo *MRI = nullptr; + TargetSchedModel SchedModel; + bool PreRegAlloc; + bool HasProfileData; + + // Various analyses that we use... + AliasAnalysis *AA = nullptr; // Alias analysis info. + MachineBlockFrequencyInfo *MBFI = nullptr; // Machine block frequncy info + MachineLoopInfo *MLI = nullptr; // Current MachineLoopInfo + MachineDominatorTree *DT = nullptr; // Machine dominator tree for the cur loop + + // State that is updated as we process loops + bool Changed; // True if a loop is changed. + bool FirstInLoop; // True if it's the first LICM in the loop. + MachineLoop *CurLoop = nullptr; // The current loop we are working on. + MachineBasicBlock *CurPreheader = nullptr; // The preheader for CurLoop. + + // Exit blocks for CurLoop. + SmallVector ExitBlocks; + + bool isExitBlock(const MachineBasicBlock *MBB) const { + return is_contained(ExitBlocks, MBB); + } - // Track 'estimated' register pressure. - SmallSet RegSeen; - SmallVector RegPressure; - - // Register pressure "limit" per register pressure set. If the pressure - // is higher than the limit, then it's considered high. - SmallVector RegLimit; - - // Register pressure on path leading from loop preheader to current BB. - SmallVector, 16> BackTrace; - - // For each opcode, keep a list of potential CSE instructions. - DenseMap> CSEMap; - - enum { - SpeculateFalse = 0, - SpeculateTrue = 1, - SpeculateUnknown = 2 - }; - - // If a MBB does not dominate loop exiting blocks then it may not safe - // to hoist loads from this block. - // Tri-state: 0 - false, 1 - true, 2 - unknown - unsigned SpeculationState; - - public: - MachineLICMBase(char &PassID, bool PreRegAlloc) - : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {} - - bool runOnMachineFunction(MachineFunction &MF) override; - - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.addRequired(); - if (DisableHoistingToHotterBlocks != UseBFI::None) - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); - MachineFunctionPass::getAnalysisUsage(AU); - } + // Track 'estimated' register pressure. + SmallSet RegSeen; + SmallVector RegPressure; - void releaseMemory() override { - RegSeen.clear(); - RegPressure.clear(); - RegLimit.clear(); - BackTrace.clear(); - CSEMap.clear(); - } + // Register pressure "limit" per register pressure set. If the pressure + // is higher than the limit, then it's considered high. + SmallVector RegLimit; - private: - /// Keep track of information about hoisting candidates. - struct CandidateInfo { - MachineInstr *MI; - unsigned Def; - int FI; + // Register pressure on path leading from loop preheader to current BB. + SmallVector, 16> BackTrace; + + // For each opcode, keep a list of potential CSE instructions. + DenseMap> CSEMap; + + enum { SpeculateFalse = 0, SpeculateTrue = 1, SpeculateUnknown = 2 }; + + // If a MBB does not dominate loop exiting blocks then it may not safe + // to hoist loads from this block. + // Tri-state: 0 - false, 1 - true, 2 - unknown + unsigned SpeculationState; + +public: + MachineLICMBase(char &PassID, bool PreRegAlloc) + : MachineFunctionPass(PassID), PreRegAlloc(PreRegAlloc) {} + + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + if (DisableHoistingToHotterBlocks != UseBFI::None) + AU.addRequired(); + AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + void releaseMemory() override { + RegSeen.clear(); + RegPressure.clear(); + RegLimit.clear(); + BackTrace.clear(); + CSEMap.clear(); + } - CandidateInfo(MachineInstr *mi, unsigned def, int fi) +private: + /// Keep track of information about hoisting candidates. + struct CandidateInfo { + MachineInstr *MI; + unsigned Def; + int FI; + + CandidateInfo(MachineInstr *mi, unsigned def, int fi) : MI(mi), Def(def), FI(fi) {} - }; + }; - void HoistRegionPostRA(); + void HoistRegionPostRA(); - void HoistPostRA(MachineInstr *MI, unsigned Def); + void HoistPostRA(MachineInstr *MI, unsigned Def); - void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs, - BitVector &PhysRegClobbers, SmallSet &StoredFIs, - SmallVectorImpl &Candidates); + void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs, + BitVector &PhysRegClobbers, SmallSet &StoredFIs, + SmallVectorImpl &Candidates); - void AddToLiveIns(MCRegister Reg); + void AddToLiveIns(MCRegister Reg); - bool IsLICMCandidate(MachineInstr &I); + bool IsLICMCandidate(MachineInstr &I); - bool IsLoopInvariantInst(MachineInstr &I); + bool IsLoopInvariantInst(MachineInstr &I); - bool HasLoopPHIUse(const MachineInstr *MI) const; + bool HasLoopPHIUse(const MachineInstr *MI) const; - bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, - Register Reg) const; + bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx, + Register Reg) const; - bool IsCheapInstruction(MachineInstr &MI) const; + bool IsCheapInstruction(MachineInstr &MI) const; - bool CanCauseHighRegPressure(const DenseMap &Cost, - bool Cheap); + bool CanCauseHighRegPressure(const DenseMap &Cost, bool Cheap); - void UpdateBackTraceRegPressure(const MachineInstr *MI); + void UpdateBackTraceRegPressure(const MachineInstr *MI); - bool IsProfitableToHoist(MachineInstr &MI); + bool IsProfitableToHoist(MachineInstr &MI); - bool IsGuaranteedToExecute(MachineBasicBlock *BB); + bool IsGuaranteedToExecute(MachineBasicBlock *BB); - bool isTriviallyReMaterializable(const MachineInstr &MI) const; + bool isTriviallyReMaterializable(const MachineInstr &MI) const; - void EnterScope(MachineBasicBlock *MBB); + void EnterScope(MachineBasicBlock *MBB); - void ExitScope(MachineBasicBlock *MBB); + void ExitScope(MachineBasicBlock *MBB); - void ExitScopeIfDone( - MachineDomTreeNode *Node, - DenseMap &OpenChildren, - const DenseMap &ParentMap); + void ExitScopeIfDone( + MachineDomTreeNode *Node, + DenseMap &OpenChildren, + const DenseMap &ParentMap); - void HoistOutOfLoop(MachineDomTreeNode *HeaderN); + void HoistOutOfLoop(MachineDomTreeNode *HeaderN); - void InitRegPressure(MachineBasicBlock *BB); + void InitRegPressure(MachineBasicBlock *BB); - DenseMap calcRegisterCost(const MachineInstr *MI, - bool ConsiderSeen, - bool ConsiderUnseenAsDef); + DenseMap calcRegisterCost(const MachineInstr *MI, + bool ConsiderSeen, + bool ConsiderUnseenAsDef); - void UpdateRegPressure(const MachineInstr *MI, - bool ConsiderUnseenAsDef = false); + void UpdateRegPressure(const MachineInstr *MI, + bool ConsiderUnseenAsDef = false); - MachineInstr *ExtractHoistableLoad(MachineInstr *MI); + MachineInstr *ExtractHoistableLoad(MachineInstr *MI); - MachineInstr *LookForDuplicate(const MachineInstr *MI, - std::vector &PrevMIs); + MachineInstr *LookForDuplicate(const MachineInstr *MI, + std::vector &PrevMIs); - bool - EliminateCSE(MachineInstr *MI, - DenseMap>::iterator &CI); + bool + EliminateCSE(MachineInstr *MI, + DenseMap>::iterator &CI); - bool MayCSE(MachineInstr *MI); + bool MayCSE(MachineInstr *MI); - bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader); + bool Hoist(MachineInstr *MI, MachineBasicBlock *Preheader); - void InitCSEMap(MachineBasicBlock *BB); + void InitCSEMap(MachineBasicBlock *BB); - bool isTgtHotterThanSrc(MachineBasicBlock *SrcBlock, - MachineBasicBlock *TgtBlock); - MachineBasicBlock *getCurPreheader(); - }; + bool isTgtHotterThanSrc(MachineBasicBlock *SrcBlock, + MachineBasicBlock *TgtBlock); + MachineBasicBlock *getCurPreheader(); +}; - class MachineLICM : public MachineLICMBase { - public: - static char ID; - MachineLICM() : MachineLICMBase(ID, false) { - initializeMachineLICMPass(*PassRegistry::getPassRegistry()); - } - }; +class MachineLICM : public MachineLICMBase { +public: + static char ID; + MachineLICM() : MachineLICMBase(ID, false) { + initializeMachineLICMPass(*PassRegistry::getPassRegistry()); + } +}; - class EarlyMachineLICM : public MachineLICMBase { - public: - static char ID; - EarlyMachineLICM() : MachineLICMBase(ID, true) { - initializeEarlyMachineLICMPass(*PassRegistry::getPassRegistry()); - } - }; +class EarlyMachineLICM : public MachineLICMBase { +public: + static char ID; + EarlyMachineLICM() : MachineLICMBase(ID, true) { + initializeEarlyMachineLICMPass(*PassRegistry::getPassRegistry()); + } +}; } // end anonymous namespace @@ -363,7 +353,7 @@ if (DisableHoistingToHotterBlocks != UseBFI::None) MBFI = &getAnalysis(); MLI = &getAnalysis(); - DT = &getAnalysis(); + DT = &getAnalysis(); AA = &getAnalysis().getAAResults(); SmallVector Worklist(MLI->begin(), MLI->end()); @@ -401,7 +391,7 @@ // Check mayStore before memory operands so that e.g. DBG_VALUEs will return // true since they have no memory operands. if (!MI->mayStore()) - return false; + return false; // If we lost memory operands, conservatively assume that the instruction // writes to all slots. if (MI->memoperands_empty()) @@ -410,7 +400,7 @@ if (!MemOp->isStore() || !MemOp->getPseudoValue()) continue; if (const FixedStackPseudoSourceValue *Value = - dyn_cast(MemOp->getPseudoValue())) { + dyn_cast(MemOp->getPseudoValue())) { if (Value->getFrameIndex() == FI) return true; } @@ -420,8 +410,7 @@ /// Examine the instruction for potentai LICM candidate. Also /// gather register def and frame object update information. -void MachineLICMBase::ProcessMI(MachineInstr *MI, - BitVector &PhysRegDefs, +void MachineLICMBase::ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs, BitVector &PhysRegClobbers, SmallSet &StoredFIs, SmallVectorImpl &Candidates) { @@ -432,8 +421,7 @@ if (MO.isFI()) { // Remember if the instruction stores to the frame index. int FI = MO.getIndex(); - if (!StoredFIs.count(FI) && - MFI->isSpillSlotObjectIndex(FI) && + if (!StoredFIs.count(FI) && MFI->isSpillSlotObjectIndex(FI) && InstructionStoresToFI(MI, FI)) StoredFIs.insert(FI); HasNonInvariantUse = true; @@ -516,7 +504,7 @@ return; unsigned NumRegs = TRI->getNumRegs(); - BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. + BitVector PhysRegDefs(NumRegs); // Regs defined once in the loop. BitVector PhysRegClobbers(NumRegs); // Regs defined more than once. SmallVector Candidates; @@ -528,7 +516,8 @@ // If the header of the loop containing this basic block is a landing pad, // then don't try to hoist instructions out of this loop. const MachineLoop *ML = MLI->getLoopFor(BB); - if (ML && ML->getHeader()->isEHPad()) continue; + if (ML && ML->getHeader()->isEHPad()) + continue; // Conservatively treat live-in's as an external def. // FIXME: That means a reload that're reused in successor block(s) will not @@ -579,8 +568,7 @@ if (!MO.isReg() || MO.isDef() || !MO.getReg()) continue; Register Reg = MO.getReg(); - if (PhysRegDefs.test(Reg) || - PhysRegClobbers.test(Reg)) { + if (PhysRegDefs.test(Reg) || PhysRegClobbers.test(Reg)) { // If it's using a non-loop-invariant register, then it's obviously // not safe to hoist. Safe = false; @@ -601,7 +589,8 @@ BB->addLiveIn(Reg); for (MachineInstr &MI : *BB) { for (MachineOperand &MO : MI.operands()) { - if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; + if (!MO.isReg() || !MO.getReg() || MO.isDef()) + continue; if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg())) MO.setIsKill(false); } @@ -647,7 +636,7 @@ if (BB != CurLoop->getHeader()) { // Check loop exiting blocks. - SmallVector CurrentLoopExitingBlocks; + SmallVector CurrentLoopExitingBlocks; CurLoop->getExitingBlocks(CurrentLoopExitingBlocks); for (MachineBasicBlock *CurrentLoopExitingBlock : CurrentLoopExitingBlocks) if (!DT->dominates(BB, CurrentLoopExitingBlock)) { @@ -692,13 +681,14 @@ /// Destroy scope for the MBB that corresponds to the given dominator tree node /// if its a leaf or all of its children are done. Walk up the dominator tree to /// destroy ancestors which are now done. -void MachineLICMBase::ExitScopeIfDone(MachineDomTreeNode *Node, - DenseMap &OpenChildren, - const DenseMap &ParentMap) { +void MachineLICMBase::ExitScopeIfDone( + MachineDomTreeNode *Node, + DenseMap &OpenChildren, + const DenseMap &ParentMap) { if (OpenChildren[Node]) return; - for(;;) { + for (;;) { ExitScope(Node->getBlock()); // Now traverse upwards to pop ancestors whose offsprings are all done. MachineDomTreeNode *Parent = ParentMap.lookup(Node); @@ -717,10 +707,10 @@ if (!Preheader) return; - SmallVector Scopes; - SmallVector WorkList; - DenseMap ParentMap; - DenseMap OpenChildren; + SmallVector Scopes; + SmallVector WorkList; + DenseMap ParentMap; + DenseMap OpenChildren; // Perform a DFS walk to determine the order of visit. WorkList.push_back(HeaderN); @@ -924,7 +914,7 @@ else FoundCallerPresReg = true; } else if (!MO.isImm()) { - return false; + return false; } } return FoundCallerPresReg; @@ -1011,7 +1001,7 @@ /// Return true if the specified instruction is used by a phi node and hoisting /// it could cause a copy to be inserted. bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const { - SmallVector Work(1, MI); + SmallVector Work(1, MI); do { MI = Work.pop_back_val(); for (const MachineOperand &MO : MI->operands()) { @@ -1023,8 +1013,8 @@ for (MachineInstr &UseMI : MRI->use_instructions(Reg)) { // A PHI may cause a copy to be inserted. if (UseMI.isPHI()) { - // A PHI inside the loop causes a copy because the live range of Reg is - // extended across the PHI. + // A PHI inside the loop causes a copy because the live range of Reg + // is extended across the PHI. if (CurLoop->contains(&UseMI)) return true; // A PHI in an exit block can cause a copy to be inserted if the PHI @@ -1101,9 +1091,8 @@ /// Visit BBs from header to current BB, check if hoisting an instruction of the /// given cost matrix can cause high register pressure. -bool -MachineLICMBase::CanCauseHighRegPressure(const DenseMap& Cost, - bool CheapInstr) { +bool MachineLICMBase::CanCauseHighRegPressure( + const DenseMap &Cost, bool CheapInstr) { for (const auto &RPIdAndCost : Cost) { if (RPIdAndCost.second <= 0) continue; @@ -1157,7 +1146,7 @@ // - When hoisting the last use of a value in the loop, that value no longer // needs to be live in the loop. This lowers register pressure in the loop. - if (HoistConstStores && isCopyFeedingInvariantStore(MI, MRI, TRI)) + if (HoistConstStores && isCopyFeedingInvariantStore(MI, MRI, TRI)) return true; bool CheapInstr = IsCheapInstruction(MI); @@ -1250,11 +1239,11 @@ // Next determine the register class for a temporary register. unsigned LoadRegIndex; unsigned NewOpc = - TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(), - /*UnfoldLoad=*/true, - /*UnfoldStore=*/false, - &LoadRegIndex); - if (NewOpc == 0) return nullptr; + TII->getOpcodeAfterMemoryUnfold(MI->getOpcode(), + /*UnfoldLoad=*/true, + /*UnfoldStore=*/false, &LoadRegIndex); + if (NewOpc == 0) + return nullptr; const MCInstrDesc &MID = TII->get(NewOpc); MachineFunction &MF = *MI->getMF(); const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF); @@ -1269,8 +1258,7 @@ assert(Success && "unfoldMemoryOperand failed when getOpcodeAfterMemoryUnfold " "succeeded!"); - assert(NewMIs.size() == 2 && - "Unfolded a load into multiple instructions!"); + assert(NewMIs.size() == 2 && "Unfolded a load into multiple instructions!"); MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock::iterator Pos = MI; MBB->insert(Pos, NewMIs[0]); @@ -1346,7 +1334,7 @@ Defs.push_back(i); } - SmallVector OrigRCs; + SmallVector OrigRCs; for (unsigned i = 0, e = Defs.size(); i != e; ++i) { unsigned Idx = Defs[i]; Register Reg = MI->getOperand(Idx).getReg(); @@ -1400,7 +1388,7 @@ // Disable the instruction hoisting due to block hotness if ((DisableHoistingToHotterBlocks == UseBFI::All || - (DisableHoistingToHotterBlocks == UseBFI::PGO && HasProfileData)) && + (DisableHoistingToHotterBlocks == UseBFI::PGO && HasProfileData)) && isTgtHotterThanSrc(SrcBlock, Preheader)) { ++NumNotHoistedDueToHotness; return false; @@ -1409,7 +1397,8 @@ if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) { // If not, try unfolding a hoistable load. MI = ExtractHoistableLoad(MI); - if (!MI) return false; + if (!MI) + return false; } // If we have hoisted an instruction that may store, it can only be a constant @@ -1441,7 +1430,7 @@ CSEMap.find(Opcode); if (!EliminateCSE(MI, CI)) { // Otherwise, splice the instruction to the preheader. - Preheader->splice(Preheader->getFirstTerminator(),MI->getParent(),MI); + Preheader->splice(Preheader->getFirstTerminator(), MI->getParent(), MI); // Since we are moving the instruction out of its basic block, we do not // retain its debug location. Doing so would degrade the debugging diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp --- a/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -41,12 +41,12 @@ createBasicRegisterAllocator); namespace { - struct CompSpillWeight { - bool operator()(const LiveInterval *A, const LiveInterval *B) const { - return A->weight() < B->weight(); - } - }; -} +struct CompSpillWeight { + bool operator()(const LiveInterval *A, const LiveInterval *B) const { + return A->weight() < B->weight(); + } +}; +} // namespace namespace { /// RABasic provides a minimal implementation of the basic register allocation @@ -58,7 +58,7 @@ public RegAllocBase, private LiveRangeEdit::Delegate { // context - MachineFunction *MF; + MachineFunction *MF = nullptr; // state std::unique_ptr SpillerInstance; @@ -109,7 +109,7 @@ MachineFunctionProperties getClearedProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::IsSSA); + MachineFunctionProperties::Property::IsSSA); } // Helper for spilling all live virtual registers currently unified under preg @@ -168,10 +168,8 @@ enqueue(&LI); } -RABasic::RABasic(RegClassFilterFunc F): - MachineFunctionPass(ID), - RegAllocBase(F) { -} +RABasic::RABasic(RegClassFilterFunc F) + : MachineFunctionPass(ID), RegAllocBase(F) {} void RABasic::getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesCFG(); @@ -197,10 +195,7 @@ MachineFunctionPass::getAnalysisUsage(AU); } -void RABasic::releaseMemory() { - SpillerInstance.reset(); -} - +void RABasic::releaseMemory() { SpillerInstance.reset(); } // Spill or split all live virtual registers currently unified under PhysReg // that interfere with VirtReg. The newly spilled or split live intervals are @@ -311,8 +306,7 @@ << "********** Function: " << mf.getName() << '\n'); MF = &mf; - RegAllocBase::init(getAnalysis(), - getAnalysis(), + RegAllocBase::init(getAnalysis(), getAnalysis(), getAnalysis()); VirtRegAuxInfo VRAI(*MF, *LIS, *VRM, getAnalysis(), getAnalysis()); @@ -330,10 +324,8 @@ return true; } -FunctionPass* llvm::createBasicRegisterAllocator() { - return new RABasic(); -} +FunctionPass *llvm::createBasicRegisterAllocator() { return new RABasic(); } -FunctionPass* llvm::createBasicRegisterAllocator(RegClassFilterFunc F) { +FunctionPass *llvm::createBasicRegisterAllocator(RegClassFilterFunc F) { return new RABasic(F); } diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp --- a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp +++ b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp @@ -69,9 +69,8 @@ LiveInterval::SubRange *SR; unsigned Index; - SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR, - unsigned Index) - : ConEQ(LIS), SR(&SR), Index(Index) {} + SubRangeInfo(LiveIntervals &LIS, LiveInterval::SubRange &SR, unsigned Index) + : ConEQ(LIS), SR(&SR), Index(Index) {} }; /// Split unrelated subregister components and rename them to new vregs. @@ -88,22 +87,22 @@ /// belonging to their class. void distribute(const IntEqClasses &Classes, const SmallVectorImpl &SubRangeInfos, - const SmallVectorImpl &Intervals) const; + const SmallVectorImpl &Intervals) const; /// Constructs main liverange and add missing undef+dead flags. - void computeMainRangesFixFlags(const IntEqClasses &Classes, + void computeMainRangesFixFlags( + const IntEqClasses &Classes, const SmallVectorImpl &SubRangeInfos, - const SmallVectorImpl &Intervals) const; + const SmallVectorImpl &Intervals) const; /// Rewrite Machine Operands to use the new vreg belonging to their class. void rewriteOperands(const IntEqClasses &Classes, const SmallVectorImpl &SubRangeInfos, - const SmallVectorImpl &Intervals) const; + const SmallVectorImpl &Intervals) const; - - LiveIntervals *LIS; - MachineRegisterInfo *MRI; - const TargetInstrInfo *TII; + LiveIntervals *LIS = nullptr; + MachineRegisterInfo *MRI = nullptr; + const TargetInstrInfo *TII = nullptr; }; } // end anonymous namespace @@ -132,7 +131,7 @@ // Create a new VReg for each class. Register Reg = LI.reg(); const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); - SmallVector Intervals; + SmallVector Intervals; Intervals.push_back(&LI); LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() << " equivalence classes.\n"); @@ -152,7 +151,8 @@ return true; } -bool RenameIndependentSubregs::findComponents(IntEqClasses &Classes, +bool RenameIndependentSubregs::findComponents( + IntEqClasses &Classes, SmallVectorImpl &SubRangeInfos, LiveInterval &LI) const { // First step: Create connected components for the VNInfos inside the @@ -187,8 +187,8 @@ if ((SR.LaneMask & LaneMask).none()) continue; SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent()); - Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) - : Pos.getBaseIndex(); + Pos = + MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) : Pos.getBaseIndex(); const VNInfo *VNI = SR.getVNInfoAt(Pos); if (VNI == nullptr) continue; @@ -208,21 +208,22 @@ return NumClasses > 1; } -void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes, +void RenameIndependentSubregs::rewriteOperands( + const IntEqClasses &Classes, const SmallVectorImpl &SubRangeInfos, - const SmallVectorImpl &Intervals) const { + const SmallVectorImpl &Intervals) const { const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo(); unsigned Reg = Intervals[0]->reg(); for (MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(Reg), - E = MRI->reg_nodbg_end(); I != E; ) { + E = MRI->reg_nodbg_end(); + I != E;) { MachineOperand &MO = *I++; if (!MO.isDef() && !MO.readsReg()) continue; auto *MI = MO.getParent(); SlotIndex Pos = LIS->getInstructionIndex(*MI); - Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) - : Pos.getBaseIndex(); + Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) : Pos.getBaseIndex(); unsigned SubRegIdx = MO.getSubReg(); LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubRegIdx); @@ -262,12 +263,13 @@ // classes than the original vreg. } -void RenameIndependentSubregs::distribute(const IntEqClasses &Classes, +void RenameIndependentSubregs::distribute( + const IntEqClasses &Classes, const SmallVectorImpl &SubRangeInfos, - const SmallVectorImpl &Intervals) const { + const SmallVectorImpl &Intervals) const { unsigned NumClasses = Classes.getNumClasses(); SmallVector VNIMapping; - SmallVector SubRanges; + SmallVector SubRanges; BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); for (const SubRangeInfo &SRInfo : SubRangeInfos) { LiveInterval::SubRange &SR = *SRInfo.SR; @@ -275,14 +277,15 @@ VNIMapping.clear(); VNIMapping.reserve(NumValNos); SubRanges.clear(); - SubRanges.resize(NumClasses-1, nullptr); + SubRanges.resize(NumClasses - 1, nullptr); for (unsigned I = 0; I < NumValNos; ++I) { const VNInfo &VNI = *SR.valnos[I]; unsigned LocalID = SRInfo.ConEQ.getEqClass(&VNI); unsigned ID = Classes[LocalID + SRInfo.Index]; VNIMapping.push_back(ID); - if (ID > 0 && SubRanges[ID-1] == nullptr) - SubRanges[ID-1] = Intervals[ID]->createSubRange(Allocator, SR.LaneMask); + if (ID > 0 && SubRanges[ID - 1] == nullptr) + SubRanges[ID - 1] = + Intervals[ID]->createSubRange(Allocator, SR.LaneMask); } DistributeRange(SR, SubRanges.data(), VNIMapping); } @@ -299,7 +302,7 @@ void RenameIndependentSubregs::computeMainRangesFixFlags( const IntEqClasses &Classes, const SmallVectorImpl &SubRangeInfos, - const SmallVectorImpl &Intervals) const { + const SmallVectorImpl &Intervals) const { BumpPtrAllocator &Allocator = LIS->getVNInfoAllocator(); const SlotIndexes &Indexes = *LIS->getSlotIndexes(); for (size_t I = 0, E = Intervals.size(); I < E; ++I) { @@ -328,10 +331,10 @@ continue; MachineBasicBlock::iterator InsertPos = - llvm::findPHICopyInsertPoint(PredMBB, &MBB, Reg); + llvm::findPHICopyInsertPoint(PredMBB, &MBB, Reg); const MCInstrDesc &MCDesc = TII->get(TargetOpcode::IMPLICIT_DEF); - MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos, - DebugLoc(), MCDesc, Reg); + MachineInstrBuilder ImpDef = + BuildMI(*PredMBB, InsertPos, DebugLoc(), MCDesc, Reg); SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); SlotIndex RegDefIdx = DefIdx.getRegSlot(); for (LiveInterval::SubRange &SR : LI.subranges()) {