Index: clang/test/Preprocessor/riscv-target-features.c =================================================================== --- clang/test/Preprocessor/riscv-target-features.c +++ clang/test/Preprocessor/riscv-target-features.c @@ -49,15 +49,19 @@ // CHECK-NOT: __riscv_zcd {{.*$}} // CHECK-NOT: __riscv_zcf {{.*$}} // CHECK-NOT: __riscv_h {{.*$}} -// CHECK-NOT: __riscv_zvkb {{.*$}} +// CHECK-NOT: __riscv_zvbb {{.*$}} +// CHECK-NOT: __riscv_zvbc {{.*$}} // CHECK-NOT: __riscv_zvkg {{.*$}} // CHECK-NOT: __riscv_zvkn {{.*$}} +// CHECK-NOT: __riscv_zvkned {{.*$}} +// CHECK-NOT: __riscv_zvkng {{.*$}} // CHECK-NOT: __riscv_zvknha {{.*$}} // CHECK-NOT: __riscv_zvknhb {{.*$}} -// CHECK-NOT: __riscv_zvkned {{.*$}} // CHECK-NOT: __riscv_zvks {{.*$}} // CHECK-NOT: __riscv_zvksed {{.*$}} +// CHECK-NOT: __riscv_zvksg {{.*$}} // CHECK-NOT: __riscv_zvksh {{.*$}} +// CHECK-NOT: __riscv_zvkt {{.*$}} // CHECK-NOT: __riscv_zicond {{.*$}} // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ @@ -526,76 +530,108 @@ // CHECK-ZFA-EXT: __riscv_zfa 1000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve64x_zvkb0p3 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s +// RUN: -march=rv32i_zve64x_zvbb0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve64x_zvkb0p3 -x c -E -dM %s \ -// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKB-EXT %s -// CHECK-ZVKB-EXT: __riscv_zvkb 3000{{$}} +// RUN: -march=rv64i_zve64x_zvbb0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBB-EXT %s +// CHECK-ZVBB-EXT: __riscv_zvbb 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve32x_zvkg0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve64x_zvbc0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvbc0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVBC-EXT %s +// CHECK-ZVBC-EXT: __riscv_zvbc 4000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvkg0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve32x_zvkg0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve32x_zvkg0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKG-EXT %s -// CHECK-ZVKG-EXT: __riscv_zvkg 3000{{$}} +// CHECK-ZVKG-EXT: __riscv_zvkg 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve64x_zvkn0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve64x_zvkn0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve64x_zvkn0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve64x_zvkn0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKN-EXT %s -// CHECK-ZVKN-EXT: __riscv_zvkn 3000{{$}} +// CHECK-ZVKN-EXT: __riscv_zvkn 4000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvkng0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvkng0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNG-EXT %s +// CHECK-ZVKNG-EXT: __riscv_zvkng 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve32x_zvknha0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve32x_zvknha0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve32x_zvknha0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve32x_zvknha0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHA-EXT %s -// CHECK-ZVKNHA-EXT: __riscv_zvknha 3000{{$}} +// CHECK-ZVKNHA-EXT: __riscv_zvknha 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve64x_zvknhb0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve64x_zvknhb0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve64x_zvknhb0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve64x_zvknhb0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNHB-EXT %s -// CHECK-ZVKNHB-EXT: __riscv_zvknhb 3000{{$}} +// CHECK-ZVKNHB-EXT: __riscv_zvknhb 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve32x_zvkned0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve32x_zvkned0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve32x_zvkned0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve32x_zvkned0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKNED-EXT %s -// CHECK-ZVKNED-EXT: __riscv_zvkned 3000{{$}} +// CHECK-ZVKNED-EXT: __riscv_zvkned 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve32x_zvks0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve64x_zvks0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve32x_zvks0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve64x_zvks0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKS-EXT %s -// CHECK-ZVKS-EXT: __riscv_zvks 3000{{$}} +// CHECK-ZVKS-EXT: __riscv_zvks 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve32x_zvksed0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve32x_zvksed0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve32x_zvksed0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve32x_zvksed0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSED-EXT %s -// CHECK-ZVKSED-EXT: __riscv_zvksed 3000{{$}} +// CHECK-ZVKSED-EXT: __riscv_zvksed 4000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve64x_zvksg0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve64x_zvksg0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSG-EXT %s +// CHECK-ZVKSG-EXT: __riscv_zvksg 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ -// RUN: -march=rv32i_zve32x_zvksh0p3 -x c -E -dM %s \ +// RUN: -march=rv32i_zve32x_zvksh0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s // RUN: %clang -target riscv64 -menable-experimental-extensions \ -// RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \ +// RUN: -march=rv64i_zve32x_zvksh0p4 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s -// CHECK-ZVKSH-EXT: __riscv_zvksh 3000{{$}} +// CHECK-ZVKSH-EXT: __riscv_zvksh 4000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_zve32x_zvkt0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_zve32x_zvkt0p4 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKT-EXT %s +// CHECK-ZVKT-EXT: __riscv_zvkt 4000{{$}} // RUN: %clang -target riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \ Index: llvm/docs/RISCVUsage.rst =================================================================== --- llvm/docs/RISCVUsage.rst +++ llvm/docs/RISCVUsage.rst @@ -202,8 +202,8 @@ ``experimental-zvfh`` LLVM implements `this draft text `_. -``experimental-zvkb``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksed``, ``experimental-zvksh`` - LLVM implements the `0.3 draft specification `_. Note that current vector crypto extension version can be found in: . +``experimental-zvbb``, ``experimental-zvbc``, ``experimental-zvkg``, ``experimental-zvkn``, ``experimental-zvkng``, ``experimental-zvknha``, ``experimental-zvknhb``, ``experimental-zvkns``, ``experimental-zvks``, ``experimental-zvksg``, ``experimental-zvksed``, ``experimental-zvksh``, ``experimental-zvkt`` + LLVM implements the `0.4.6 draft specification `_. Note that current vector crypto extension version can be found in: . To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -145,15 +145,20 @@ {"ztso", RISCVExtensionVersion{0, 1}}, // vector crypto - {"zvkb", RISCVExtensionVersion{0, 3}}, - {"zvkg", RISCVExtensionVersion{0, 3}}, - {"zvkn", RISCVExtensionVersion{0, 3}}, - {"zvknha", RISCVExtensionVersion{0, 3}}, - {"zvknhb", RISCVExtensionVersion{0, 3}}, - {"zvkned", RISCVExtensionVersion{0, 3}}, - {"zvks", RISCVExtensionVersion{0, 3}}, - {"zvksed", RISCVExtensionVersion{0, 3}}, - {"zvksh", RISCVExtensionVersion{0, 3}}, + {"zvbb", RISCVExtensionVersion{0, 4}}, + {"zvbc", RISCVExtensionVersion{0, 4}}, + {"zvkg", RISCVExtensionVersion{0, 4}}, + {"zvkg", RISCVExtensionVersion{0, 4}}, + {"zvkn", RISCVExtensionVersion{0, 4}}, + {"zvkned", RISCVExtensionVersion{0, 4}}, + {"zvkng", RISCVExtensionVersion{0, 4}}, + {"zvknha", RISCVExtensionVersion{0, 4}}, + {"zvknhb", RISCVExtensionVersion{0, 4}}, + {"zvks", RISCVExtensionVersion{0, 4}}, + {"zvksed", RISCVExtensionVersion{0, 4}}, + {"zvksg", RISCVExtensionVersion{0, 4}}, + {"zvksh", RISCVExtensionVersion{0, 4}}, + {"zvkt", RISCVExtensionVersion{0, 4}}, }; static bool stripExperimentalPrefix(StringRef &Ext) { @@ -883,9 +888,19 @@ errc::invalid_argument, "'zvl*b' requires 'v' or 'zve*' extension to also be specified"); - if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkn") || - Exts.count("zvknha") || Exts.count("zvkned") || Exts.count("zvks") || - Exts.count("zvksed") || Exts.count("zvksh")) && + if (Exts.count("zvbb") && !HasVector) + return createStringError( + errc::invalid_argument, + "'zvbb' requires 'v' or 'zve*' extension to also be specified"); + + if (Exts.count("zvbc") && !Exts.count("zve64x")) + return createStringError( + errc::invalid_argument, + "'zvbc' requires 'v' or 'zve64*' extension to also be specified"); + + if ((Exts.count("zvkg") || Exts.count("zvkn") || Exts.count("zvkned") || + Exts.count("zvkng") || Exts.count("zvknha") || Exts.count("zvks") || + Exts.count("zvksed") || Exts.count("zvksg") || Exts.count("zvksh")) && !HasVector) return createStringError( errc::invalid_argument, @@ -933,9 +948,13 @@ "zkne", "zknd", "zknh"}; static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; -static const char *ImpliedExtsZvkn[] = {"zvkned", "zvknhb", "zvkb"}; +static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb", + "zvkt"}; +static const char *ImpliedExtsZvkng[] = {"zvkg", "zvkn"}; static const char *ImpliedExtsZvknhb[] = {"zvknha"}; -static const char *ImpliedExtsZvks[] = {"zvksed", "zvksh", "zvkb"}; +static const char *ImpliedExtsZvks[] = {"zvbb", "zvbc", "zvksed", "zvksh", + "zvkt"}; +static const char *ImpliedExtsZvksg[] = {"zvks", "zvkg"}; static const char *ImpliedExtsXsfvcp[] = {"zve32x"}; static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsZcb[] = {"zca"}; @@ -977,8 +996,10 @@ {{"zve64x"}, {ImpliedExtsZve64x}}, {{"zvfh"}, {ImpliedExtsZvfh}}, {{"zvkn"}, {ImpliedExtsZvkn}}, + {{"zvkng"}, {ImpliedExtsZvkng}}, {{"zvknhb"}, {ImpliedExtsZvknhb}}, {{"zvks"}, {ImpliedExtsZvks}}, + {{"zvksg"}, {ImpliedExtsZvksg}}, {{"zvl1024b"}, {ImpliedExtsZvl1024b}}, {{"zvl128b"}, {ImpliedExtsZvl128b}}, {{"zvl16384b"}, {ImpliedExtsZvl16384b}}, Index: llvm/lib/Target/RISCV/RISCVFeatures.td =================================================================== --- llvm/lib/Target/RISCV/RISCVFeatures.td +++ llvm/lib/Target/RISCV/RISCVFeatures.td @@ -481,12 +481,19 @@ AssemblerPredicate<(all_of FeatureStdExtZawrs), "'Zawrs' (Wait on Reservation Set)">; -def FeatureStdExtZvkb - : SubtargetFeature<"experimental-zvkb", "HasStdExtZvkb", "true", - "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">; -def HasStdExtZvkb : Predicate<"Subtarget->hasStdExtZvkb()">, - AssemblerPredicate<(all_of FeatureStdExtZvkb), - "'Zvkb' (Vector Bitmanip instructions for Cryptography.)">; +def FeatureStdExtZvbb + : SubtargetFeature<"experimental-zvbb", "HasStdExtZvbb", "true", + "'Zvbb' (Vector Bit-manipulation used in Cryptography)">; +def HasStdExtZvbb : Predicate<"Subtarget->hasStdExtZvbb()">, + AssemblerPredicate<(all_of FeatureStdExtZvbb), + "'Zvbb' (Vector Bit-manipulation used in Cryptography)">; + +def FeatureStdExtZvbc + : SubtargetFeature<"experimental-zvbc", "HasStdExtZvbc", "true", + "'Zvbc' (Vector Carryless Multiplication)">; +def HasStdExtZvbc : Predicate<"Subtarget->hasStdExtZvbc()">, + AssemblerPredicate<(all_of FeatureStdExtZvbc), + "'Zvbc' (Vector Carryless Multiplication)">; def FeatureStdExtZvkg : SubtargetFeature<"experimental-zvkg", "HasStdExtZvkg", "true", @@ -498,7 +505,19 @@ def FeatureStdExtZvkn : SubtargetFeature<"experimental-zvkn", "HasStdExtZvkn", "true", "This extension is shorthand for the following set of " - "other extensions: Zvkned, Zvknhb and Zvkb.">; + "other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.">; + +def FeatureStdExtZvkned + : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true", + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; +def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, + AssemblerPredicate<(all_of FeatureStdExtZvkned), + "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; + +def FeatureStdExtZvkng + : SubtargetFeature<"experimental-zvkng", "HasStdExtZvkng", "true", + "This extension is shorthand for the following set of " + "other extensions: Zvkn and Zvkt.">; def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", @@ -512,17 +531,10 @@ AssemblerPredicate<(all_of FeatureStdExtZvknha), "'Zvknha' (Vector SHA-2. (SHA-256 only))">; -def FeatureStdExtZvkned - : SubtargetFeature<"experimental-zvkned", "HasStdExtZvkned", "true", - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; -def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, - AssemblerPredicate<(all_of FeatureStdExtZvkned), - "'Zvkned' (Vector AES Encryption & Decryption (Single Round))">; - def FeatureStdExtZvks : SubtargetFeature<"experimental-zvks", "HasStdExtZvks", "true", "This extension is shorthand for the following set of " - "other extensions: Zvksed, Zvksh and Zvkb.">; + "other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.">; def FeatureStdExtZvksed : SubtargetFeature<"experimental-zvksed", "HasStdExtZvksed", "true", @@ -531,6 +543,11 @@ AssemblerPredicate<(all_of FeatureStdExtZvksed), "'Zvksed' (SM4 Block Cipher Instructions.)">; +def FeatureStdExtZvksg + : SubtargetFeature<"experimental-zvksg", "HasStdExtZvksg", "true", + "This extension is shorthand for the following set of " + "other extensions: Zvks and Zvkt.">; + def FeatureStdExtZvksh : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true", "'Zvksh' (SM3 Hash Function Instructions.)">; Index: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -128,15 +128,24 @@ let OperandNamespace = "RISCVOp"; } -let Predicates = [HasStdExtZvkb] in { - defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>; +let Predicates = [HasStdExtZvbb] in { def VBREV8_V : VALUVs2<0b010010, 0b01000, OPMVV, "vbrev8.v">; + def VBREV_V : VALUVs2<0b010010, 0b01010, OPMVV, "vbrev.v">; + def VCLZ_V : VALUVs2<0b010010, 0b01100, OPMVV, "vclz.v">; + def VCPOP_V : VALUVs2<0b010010, 0b01110, OPMVV, "vcpop.v">; + def VCTZ_V : VALUVs2<0b010010, 0b01101, OPMVV, "vctz.v">; + def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">; + + defm VANDN_V : VALU_IV_V_X<"vandn", 0b000001>; + defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>; + defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>; + defm VWSLL_V : VALU_IV_V_X_I<"vwsll", 0b110101, uimm5>; +} // Predicates = [HasStdExtZvbb] + +let Predicates = [HasStdExtZvbc] in { defm VCLMUL_V : VCLMUL_MV_V_X<"vclmul", 0b001100>; defm VCLMULH_V : VCLMUL_MV_V_X<"vclmulh", 0b001101>; - def VREV8_V : VALUVs2<0b010010, 0b01001, OPMVV, "vrev8.v">; - defm VROL_V : VALU_IV_V_X<"vrol", 0b010101>; - defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>; -} // Predicates = [HasStdExtZvkb] +} // Predicates = [HasStdExtZvbc] let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in { def VGHSH_VV : PALUVVNoVm<0b101100, OPMVV, "vghsh.vv">; Index: llvm/test/MC/RISCV/attribute-arch.s =================================================================== --- llvm/test/MC/RISCV/attribute-arch.s +++ llvm/test/MC/RISCV/attribute-arch.s @@ -111,32 +111,44 @@ .attribute arch, "rv32izbc1p0" # CHECK: attribute 5, "rv32i2p1_zbc1p0" -.attribute arch, "rv32i_zve64x_zvkb0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0" +.attribute arch, "rv32i_zve64x_zvbb0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p4_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" -.attribute arch, "rv32i_zve32x_zvkg0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0" +.attribute arch, "rv32i_zve64x_zvbc0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc0p4_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" -.attribute arch, "rv32i_zve64x_zvkn0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" +.attribute arch, "rv32i_zve32x_zvkg0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p4_zvl32b1p0" -.attribute arch, "rv32i_zve32x_zvknha0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p3_zvl32b1p0" +.attribute arch, "rv32i_zve64x_zvkn0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p4_zvbc0p4_zve32x1p0_zve64x1p0_zvkn0p4_zvkned0p4_zvknha0p4_zvknhb0p4_zvkt0p4_zvl32b1p0_zvl64b1p0" -.attribute arch, "rv32i_zve64x_zvknhb0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" +.attribute arch, "rv32i_zve64x_zvkng0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p4_zvbc0p4_zve32x1p0_zve64x1p0_zvkg0p4_zvkn0p4_zvkned0p4_zvkng0p4_zvknha0p4_zvknhb0p4_zvkt0p4_zvl32b1p0_zvl64b1p0" -.attribute arch, "rv32i_zve32x_zvkned0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p3_zvl32b1p0" +.attribute arch, "rv32i_zve32x_zvknha0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p4_zvl32b1p0" -.attribute arch, "rv32i_zve32x_zvks0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" +.attribute arch, "rv32i_zve64x_zvknhb0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p4_zvknhb0p4_zvl32b1p0_zvl64b1p0" -.attribute arch, "rv32i_zve32x_zvksed0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0" +.attribute arch, "rv32i_zve32x_zvkned0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p4_zvl32b1p0" -.attribute arch, "rv32i_zve32x_zvksh0p3" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0" +.attribute arch, "rv32i_zve64x_zvks0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p4_zvbc0p4_zve32x1p0_zve64x1p0_zvks0p4_zvksed0p4_zvksh0p4_zvkt0p4_zvl32b1p0_zvl64b1p0" + +.attribute arch, "rv32i_zve64x_zvksg0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbb0p4_zvbc0p4_zve32x1p0_zve64x1p0_zvkg0p4_zvks0p4_zvksed0p4_zvksg0p4_zvksh0p4_zvkt0p4_zvl32b1p0_zvl64b1p0" + +.attribute arch, "rv32i_zve32x_zvksed0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p4_zvl32b1p0" + +.attribute arch, "rv32i_zve32x_zvksh0p4" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p4_zvl32b1p0" + +.attribute arch, "rv32i_zvkt0p4" +# CHECK: attribute 5, "rv32i2p1_zvkt0p4" .attribute arch, "rv32izbs1p0" # CHECK: attribute 5, "rv32i2p1_zbs1p0" Index: llvm/test/MC/RISCV/rvv/zvbb.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/zvbb.s @@ -0,0 +1,106 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvbb %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \ +# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvbb - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvbb %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vandn.vv v10, v9, v8, v0.t +# CHECK-INST: vandn.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0x04] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 05 94 04 + +vandn.vx v10, v9, a0, v0.t +# CHECK-INST: vandn.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0x04] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 45 95 04 + +vbrev8.v v10, v9, v0.t +# CHECK-INST: vbrev8.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0x25,0x94,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 25 94 48 + +vbrev.v v10, v9, v0.t +# CHECK-INST: vbrev.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0x25,0x95,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 25 95 48 + +vclz.v v10, v9, v0.t +# CHECK-INST: vclz.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0x25,0x96,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 25 96 48 + +vcpop.v v10, v9, v0.t +# CHECK-INST: vcpop.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0x25,0x97,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 25 97 48 + +vctz.v v10, v9, v0.t +# CHECK-INST: vctz.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0xa5,0x96,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 a5 96 48 + +vrev8.v v10, v9, v0.t +# CHECK-INST: vrev8.v v10, v9, v0.t +# CHECK-ENCODING: [0x57,0xa5,0x94,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 a5 94 48 + +vrol.vv v10, v9, v8, v0.t +# CHECK-INST: vrol.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 05 94 54 + +vrol.vx v10, v9, a0, v0.t +# CHECK-INST: vrol.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 45 95 54 + +vror.vv v10, v9, v8, v0.t +# CHECK-INST: vror.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0x50] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 05 94 50 + +vror.vx v10, v9, a0, v0.t +# CHECK-INST: vror.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0x50] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 45 95 50 + +vror.vi v10, v9, 33, v0.t +# CHECK-INST: vror.vi v10, v9, 33, v0.t +# CHECK-ENCODING: [0x57,0xb5,0x90,0x54] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 b5 90 54 + +vwsll.vv v10, v9, v8, v0.t +# CHECK-INST: vwsll.vv v10, v9, v8, v0.t +# CHECK-ENCODING: [0x57,0x05,0x94,0xd4] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 05 94 d4 + +vwsll.vx v10, v9, a0, v0.t +# CHECK-INST: vwsll.vx v10, v9, a0, v0.t +# CHECK-ENCODING: [0x57,0x45,0x95,0xd4] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 45 95 d4 + +vwsll.vi v10, v9, 29, v0.t +# CHECK-INST: vwsll.vi v10, v9, 29, v0.t +# CHECK-ENCODING: [0x57,0xb5,0x9e,0xd4] +# CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector Bit-manipulation used in Cryptography){{$}} +# CHECK-UNKNOWN: 57 b5 9e d4 + Index: llvm/test/MC/RISCV/rvv/zvbc.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/zvbc.s @@ -0,0 +1,33 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve64x --mattr=+experimental-zvbc %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \ +# RUN: | llvm-objdump -d --mattr=+zve64x --mattr=+experimental-zvbc - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve64x --mattr=+experimental-zvbc %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +vclmul.vv v10, v9, v8 +# CHECK-INST: vclmul.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x32] +# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-UNKNOWN: 57 25 94 32 + +vclmul.vx v10, v9, a0 +# CHECK-INST: vclmul.vx v10, v9, a0 +# CHECK-ENCODING: [0x57,0x65,0x95,0x32] +# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-UNKNOWN: 57 65 95 32 + +vclmulh.vv v10, v9, v8 +# CHECK-INST: vclmulh.vv v10, v9, v8 +# CHECK-ENCODING: [0x57,0x25,0x94,0x36] +# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-UNKNOWN: 57 25 94 36 + +vclmulh.vx v10, v9, a0 +# CHECK-INST: vclmulh.vx v10, v9, a0 +# CHECK-ENCODING: [0x57,0x65,0x95,0x36] +# CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} +# CHECK-UNKNOWN: 57 65 95 36 Index: llvm/test/MC/RISCV/rvv/zvkb.s =================================================================== --- llvm/test/MC/RISCV/rvv/zvkb.s +++ /dev/null @@ -1,87 +0,0 @@ -# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \ -# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST -# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \ -# RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \ -# RUN: | llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb - \ -# RUN: | FileCheck %s --check-prefix=CHECK-INST -# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \ -# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN - -vandn.vv v10, v9, v8, v0.t -# CHECK-INST: vandn.vv v10, v9, v8, v0.t -# CHECK-ENCODING: [0x57,0x05,0x94,0x04] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 05 94 04 - -vandn.vx v10, v9, a0, v0.t -# CHECK-INST: vandn.vx v10, v9, a0, v0.t -# CHECK-ENCODING: [0x57,0x45,0x95,0x04] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 45 95 04 - -vbrev8.v v10, v9, v0.t -# CHECK-INST: vbrev8.v v10, v9, v0.t -# CHECK-ENCODING: [0x57,0x25,0x94,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 25 94 48 - -vclmul.vv v10, v9, v8 -# CHECK-INST: vclmul.vv v10, v9, v8 -# CHECK-ENCODING: [0x57,0x25,0x94,0x32] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 25 94 32 - -vclmul.vx v10, v9, a0 -# CHECK-INST: vclmul.vx v10, v9, a0 -# CHECK-ENCODING: [0x57,0x65,0x95,0x32] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 65 95 32 - -vclmulh.vv v10, v9, v8 -# CHECK-INST: vclmulh.vv v10, v9, v8 -# CHECK-ENCODING: [0x57,0x25,0x94,0x36] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 25 94 36 - -vclmulh.vx v10, v9, a0 -# CHECK-INST: vclmulh.vx v10, v9, a0 -# CHECK-ENCODING: [0x57,0x65,0x95,0x36] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 65 95 36 - -vrev8.v v10, v9, v0.t -# CHECK-INST: vrev8.v v10, v9, v0.t -# CHECK-ENCODING: [0x57,0xa5,0x94,0x48] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 a5 94 48 - -vrol.vv v10, v9, v8, v0.t -# CHECK-INST: vrol.vv v10, v9, v8, v0.t -# CHECK-ENCODING: [0x57,0x05,0x94,0x54] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 05 94 54 - -vrol.vx v10, v9, a0, v0.t -# CHECK-INST: vrol.vx v10, v9, a0, v0.t -# CHECK-ENCODING: [0x57,0x45,0x95,0x54] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 45 95 54 - -vror.vv v10, v9, v8, v0.t -# CHECK-INST: vror.vv v10, v9, v8, v0.t -# CHECK-ENCODING: [0x57,0x05,0x94,0x50] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 05 94 50 - -vror.vx v10, v9, a0, v0.t -# CHECK-INST: vror.vx v10, v9, a0, v0.t -# CHECK-ENCODING: [0x57,0x45,0x95,0x50] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 45 95 50 - -vror.vi v10, v9, 33, v0.t -# CHECK-INST: vror.vi v10, v9, 33, v0.t -# CHECK-ENCODING: [0x57,0xb5,0x90,0x54] -# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}} -# CHECK-UNKNOWN: 57 b5 90 54