diff --git a/clang/include/clang/Basic/BuiltinsRISCVVector.def b/clang/include/clang/Basic/BuiltinsRISCVVector.def --- a/clang/include/clang/Basic/BuiltinsRISCVVector.def +++ b/clang/include/clang/Basic/BuiltinsRISCVVector.def @@ -16,6 +16,7 @@ #endif #include "clang/Basic/riscv_vector_builtins.inc" +#include "clang/Basic/riscv_sifive_vector_builtins.inc" #undef BUILTIN #undef TARGET_BUILTIN diff --git a/clang/include/clang/Basic/CMakeLists.txt b/clang/include/clang/Basic/CMakeLists.txt --- a/clang/include/clang/Basic/CMakeLists.txt +++ b/clang/include/clang/Basic/CMakeLists.txt @@ -93,3 +93,12 @@ clang_tablegen(riscv_vector_builtin_sema.inc -gen-riscv-vector-builtin-sema SOURCE riscv_vector.td TARGET ClangRISCVVectorBuiltinSema) +clang_tablegen(riscv_sifive_vector_builtins.inc -gen-riscv-sifive-vector-builtins + SOURCE riscv_sifive_vector.td + TARGET ClangRISCVSiFiveVectorBuiltins) +clang_tablegen(riscv_sifive_vector_builtin_cg.inc -gen-riscv-sifive-vector-builtin-codegen + SOURCE riscv_sifive_vector.td + TARGET ClangRISCVSiFiveVectorBuiltinCG) +clang_tablegen(riscv_sifive_vector_builtin_sema.inc -gen-riscv-sifive-vector-builtin-sema + SOURCE riscv_sifive_vector.td + TARGET ClangRISCVSiFiveVectorBuiltinSema) diff --git a/clang/include/clang/Basic/riscv_sifive_vector.td b/clang/include/clang/Basic/riscv_sifive_vector.td --- a/clang/include/clang/Basic/riscv_sifive_vector.td +++ b/clang/include/clang/Basic/riscv_sifive_vector.td @@ -12,6 +12,8 @@ // //===----------------------------------------------------------------------===// +include "riscv_vector_common.td" + //===----------------------------------------------------------------------===// // Instruction definitions //===----------------------------------------------------------------------===// diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2148,5 +2148,3 @@ } } } - -include "riscv_sifive_vector.td" diff --git a/clang/include/clang/Sema/RISCVIntrinsicManager.h b/clang/include/clang/Sema/RISCVIntrinsicManager.h --- a/clang/include/clang/Sema/RISCVIntrinsicManager.h +++ b/clang/include/clang/Sema/RISCVIntrinsicManager.h @@ -22,6 +22,8 @@ namespace sema { class RISCVIntrinsicManager { public: + enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR }; + virtual ~RISCVIntrinsicManager() = default; // Create RISC-V intrinsic and insert into symbol table and return true if diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h --- a/clang/include/clang/Sema/Sema.h +++ b/clang/include/clang/Sema/Sema.h @@ -1621,6 +1621,9 @@ /// Indicate RISC-V vector builtin functions enabled or not. bool DeclareRISCVVBuiltins = false; + /// Indicate RISC-V Sifive vector builtin functions enabled or not. + bool DeclareRISCVVectorBuiltins = false; + private: std::unique_ptr RVIntrinsicManager; diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -20019,6 +20019,8 @@ // Vector builtins are handled from here. #include "clang/Basic/riscv_vector_builtin_cg.inc" + // SiFive Vector builtins are handled from here. +#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc" } assert(ID != Intrinsic::not_intrinsic); diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -102,6 +102,10 @@ riscv_ntlh.h ) +set(sifive_files + sifive_vector.h + ) + set(systemz_files s390intrin.h vecintrin.h @@ -249,6 +253,7 @@ ${ppc_files} ${ppc_htm_files} ${riscv_files} + ${sifive_files} ${systemz_files} ${ve_files} ${x86_files} diff --git a/clang/lib/Headers/sifive_vector.h b/clang/lib/Headers/sifive_vector.h new file mode 100644 --- /dev/null +++ b/clang/lib/Headers/sifive_vector.h @@ -0,0 +1,16 @@ +//===----- sifive_vector.h - SiFive Vector definitions --------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef _SIFIVE_VECTOR_H_ +#define _SIFIVE_VECTOR_H_ + +#include "riscv_vector.h" + +#pragma clang riscv intrinsic sifive_vector + +#endif //_SIFIVE_VECTOR_H_ diff --git a/clang/lib/Parse/ParsePragma.cpp b/clang/lib/Parse/ParsePragma.cpp --- a/clang/lib/Parse/ParsePragma.cpp +++ b/clang/lib/Parse/ParsePragma.cpp @@ -4024,6 +4024,7 @@ } // Handle '#pragma clang riscv intrinsic vector'. +// '#pragma clang riscv intrinsic sifive_vector'. void PragmaRISCVHandler::HandlePragma(Preprocessor &PP, PragmaIntroducer Introducer, Token &FirstToken) { @@ -4039,9 +4040,11 @@ PP.Lex(Tok); II = Tok.getIdentifierInfo(); - if (!II || !II->isStr("vector")) { + StringRef IntrinsicClass = II->getName(); + if (!II || !(II->isStr("vector") || II->isStr("sifive_vector"))) { PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument) - << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'vector'"; + << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true + << "'vector' or 'sifive_vector'"; return; } @@ -4052,5 +4055,8 @@ return; } - Actions.DeclareRISCVVBuiltins = true; + if (IntrinsicClass == "vector") + Actions.DeclareRISCVVBuiltins = true; + else if (IntrinsicClass == "sifive_vector") + Actions.DeclareRISCVVectorBuiltins = true; } diff --git a/clang/lib/Sema/SemaLookup.cpp b/clang/lib/Sema/SemaLookup.cpp --- a/clang/lib/Sema/SemaLookup.cpp +++ b/clang/lib/Sema/SemaLookup.cpp @@ -933,7 +933,7 @@ } } - if (DeclareRISCVVBuiltins) { + if (DeclareRISCVVBuiltins || DeclareRISCVVectorBuiltins) { if (!RVIntrinsicManager) RVIntrinsicManager = CreateRISCVIntrinsicManager(*this); diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp --- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp +++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp @@ -28,6 +28,8 @@ using namespace clang; using namespace clang::RISCV; +using IntrinsicKind = sema::RISCVIntrinsicManager::IntrinsicKind; + namespace { // Function definition of a RVV intrinsic. @@ -58,16 +60,35 @@ #undef DECL_SIGNATURE_TABLE }; +static const PrototypeDescriptor RVSiFiveVectorSignatureTable[] = { +#define DECL_SIGNATURE_TABLE +#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc" +#undef DECL_SIGNATURE_TABLE +}; + static const RVVIntrinsicRecord RVVIntrinsicRecords[] = { #define DECL_INTRINSIC_RECORDS #include "clang/Basic/riscv_vector_builtin_sema.inc" #undef DECL_INTRINSIC_RECORDS }; +static const RVVIntrinsicRecord RVSiFiveVectorIntrinsicRecords[] = { +#define DECL_INTRINSIC_RECORDS +#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc" +#undef DECL_INTRINSIC_RECORDS +}; + // Get subsequence of signature table. -static ArrayRef ProtoSeq2ArrayRef(uint16_t Index, - uint8_t Length) { - return ArrayRef(&RVVSignatureTable[Index], Length); +static ArrayRef +ProtoSeq2ArrayRef(IntrinsicKind K, uint16_t Index, uint8_t Length) { + switch (K) { + default: + llvm_unreachable("Unsupported intrinsic kind."); + case IntrinsicKind::RVV: + return ArrayRef(&RVVSignatureTable[Index], Length); + case IntrinsicKind::SIFIVE_VECTOR: + return ArrayRef(&RVSiFiveVectorSignatureTable[Index], Length); + } } static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type) { @@ -172,123 +193,132 @@ bool HasRV64 = TI.hasFeature("64bit"); bool HasFullMultiply = TI.hasFeature("v"); - // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics - // in RISCVVEmitter.cpp. - for (auto &Record : RVVIntrinsicRecords) { - // Create Intrinsics for each type and LMUL. - BasicType BaseType = BasicType::Unknown; - ArrayRef BasicProtoSeq = - ProtoSeq2ArrayRef(Record.PrototypeIndex, Record.PrototypeLength); - ArrayRef SuffixProto = - ProtoSeq2ArrayRef(Record.SuffixIndex, Record.SuffixLength); - ArrayRef OverloadedSuffixProto = ProtoSeq2ArrayRef( - Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize); - - PolicyScheme UnMaskedPolicyScheme = - static_cast(Record.UnMaskedPolicyScheme); - PolicyScheme MaskedPolicyScheme = - static_cast(Record.MaskedPolicyScheme); - - const Policy DefaultPolicy; - - llvm::SmallVector ProtoSeq = - RVVIntrinsic::computeBuiltinTypes(BasicProtoSeq, /*IsMasked=*/false, - /*HasMaskedOffOperand=*/false, - Record.HasVL, Record.NF, - UnMaskedPolicyScheme, DefaultPolicy); - - llvm::SmallVector ProtoMaskSeq = - RVVIntrinsic::computeBuiltinTypes( - BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand, - Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy); - - bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone; - bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone; - SmallVector SupportedUnMaskedPolicies = - RVVIntrinsic::getSupportedUnMaskedPolicies(); - SmallVector SupportedMaskedPolicies = - RVVIntrinsic::getSupportedMaskedPolicies(Record.HasTailPolicy, - Record.HasMaskPolicy); - - for (unsigned int TypeRangeMaskShift = 0; - TypeRangeMaskShift <= static_cast(BasicType::MaxOffset); - ++TypeRangeMaskShift) { - unsigned int BaseTypeI = 1 << TypeRangeMaskShift; - BaseType = static_cast(BaseTypeI); - - if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI) - continue; - - // Check requirement. - if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) && - !HasRV64) - continue; - - if ((BaseType == BasicType::Int64) && - ((Record.RequiredExtensions & RVV_REQ_FullMultiply) == - RVV_REQ_FullMultiply) && - !HasFullMultiply) - continue; - - // Expanded with different LMUL. - for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) { - if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3)))) + auto ConstructRVVIntrinsics = [&](ArrayRef Recs, + IntrinsicKind K) { + // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics + // in RISCVVEmitter.cpp. + for (auto &Record : Recs) { + // Create Intrinsics for each type and LMUL. + BasicType BaseType = BasicType::Unknown; + ArrayRef BasicProtoSeq = + ProtoSeq2ArrayRef(K, Record.PrototypeIndex, Record.PrototypeLength); + ArrayRef SuffixProto = + ProtoSeq2ArrayRef(K, Record.SuffixIndex, Record.SuffixLength); + ArrayRef OverloadedSuffixProto = ProtoSeq2ArrayRef( + K, Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize); + + PolicyScheme UnMaskedPolicyScheme = + static_cast(Record.UnMaskedPolicyScheme); + PolicyScheme MaskedPolicyScheme = + static_cast(Record.MaskedPolicyScheme); + + const Policy DefaultPolicy; + + llvm::SmallVector ProtoSeq = + RVVIntrinsic::computeBuiltinTypes(BasicProtoSeq, /*IsMasked=*/false, + /*HasMaskedOffOperand=*/false, + Record.HasVL, Record.NF, + UnMaskedPolicyScheme, DefaultPolicy); + + llvm::SmallVector ProtoMaskSeq = + RVVIntrinsic::computeBuiltinTypes( + BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand, + Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy); + + bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone; + bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone; + SmallVector SupportedUnMaskedPolicies = + RVVIntrinsic::getSupportedUnMaskedPolicies(); + SmallVector SupportedMaskedPolicies = + RVVIntrinsic::getSupportedMaskedPolicies(Record.HasTailPolicy, + Record.HasMaskPolicy); + + for (unsigned int TypeRangeMaskShift = 0; + TypeRangeMaskShift <= static_cast(BasicType::MaxOffset); + ++TypeRangeMaskShift) { + unsigned int BaseTypeI = 1 << TypeRangeMaskShift; + BaseType = static_cast(BaseTypeI); + + if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI) continue; - std::optional Types = - TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq); - - // Ignored to create new intrinsic if there are any illegal types. - if (!Types.has_value()) + // Check requirement. + if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) && + !HasRV64) continue; - std::string SuffixStr = RVVIntrinsic::getSuffixStr( - TypeCache, BaseType, Log2LMUL, SuffixProto); - std::string OverloadedSuffixStr = RVVIntrinsic::getSuffixStr( - TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto); - - // Create non-masked intrinsic. - InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, false, *Types, - UnMaskedHasPolicy, DefaultPolicy); + if ((BaseType == BasicType::Int64) && + ((Record.RequiredExtensions & RVV_REQ_FullMultiply) == + RVV_REQ_FullMultiply) && + !HasFullMultiply) + continue; - // Create non-masked policy intrinsic. - if (Record.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) { - for (const auto &P : SupportedUnMaskedPolicies) { + // Expanded with different LMUL. + for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) { + if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3)))) + continue; + + std::optional Types = + TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq); + + // Ignored to create new intrinsic if there are any illegal types. + if (!Types.has_value()) + continue; + + std::string SuffixStr = RVVIntrinsic::getSuffixStr( + TypeCache, BaseType, Log2LMUL, SuffixProto); + std::string OverloadedSuffixStr = RVVIntrinsic::getSuffixStr( + TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto); + + // Create non-masked intrinsic. + InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, false, *Types, + UnMaskedHasPolicy, DefaultPolicy); + + // Create non-masked policy intrinsic. + if (Record.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) { + for (auto P : SupportedUnMaskedPolicies) { + llvm::SmallVector PolicyPrototype = + RVVIntrinsic::computeBuiltinTypes( + BasicProtoSeq, /*IsMasked=*/false, + /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF, + UnMaskedPolicyScheme, P); + std::optional PolicyTypes = TypeCache.computeTypes( + BaseType, Log2LMUL, Record.NF, PolicyPrototype); + InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, + /*IsMask=*/false, *PolicyTypes, UnMaskedHasPolicy, + P); + } + } + if (!Record.HasMasked) + continue; + // Create masked intrinsic. + std::optional MaskTypes = + TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoMaskSeq); + InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, true, + *MaskTypes, MaskedHasPolicy, DefaultPolicy); + if (Record.MaskedPolicyScheme == PolicyScheme::SchemeNone) + continue; + // Create masked policy intrinsic. + for (auto P : SupportedMaskedPolicies) { llvm::SmallVector PolicyPrototype = RVVIntrinsic::computeBuiltinTypes( - BasicProtoSeq, /*IsMasked=*/false, - /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF, - UnMaskedPolicyScheme, P); + BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand, + Record.HasVL, Record.NF, MaskedPolicyScheme, P); std::optional PolicyTypes = TypeCache.computeTypes( BaseType, Log2LMUL, Record.NF, PolicyPrototype); InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, - /*IsMask=*/false, *PolicyTypes, UnMaskedHasPolicy, - P); + /*IsMask=*/true, *PolicyTypes, MaskedHasPolicy, P); } - } - if (!Record.HasMasked) - continue; - // Create masked intrinsic. - std::optional MaskTypes = - TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoMaskSeq); - InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, true, - *MaskTypes, MaskedHasPolicy, DefaultPolicy); - if (Record.MaskedPolicyScheme == PolicyScheme::SchemeNone) - continue; - // Create masked policy intrinsic. - for (auto P : SupportedMaskedPolicies) { - llvm::SmallVector PolicyPrototype = - RVVIntrinsic::computeBuiltinTypes( - BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand, - Record.HasVL, Record.NF, MaskedPolicyScheme, P); - std::optional PolicyTypes = TypeCache.computeTypes( - BaseType, Log2LMUL, Record.NF, PolicyPrototype); - InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, - /*IsMask=*/true, *PolicyTypes, MaskedHasPolicy, P); - } - } // End for different LMUL - } // End for different TypeRange - } + } // End for different LMUL + } // End for different TypeRange + } + }; + if (S.DeclareRISCVVBuiltins) + ConstructRVVIntrinsics(RVVIntrinsicRecords, + IntrinsicKind::RVV); + if (S.DeclareRISCVVectorBuiltins) + ConstructRVVIntrinsics(RVSiFiveVectorIntrinsicRecords, + IntrinsicKind::SIFIVE_VECTOR); } // Compute name and signatures for intrinsic with practical types. diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c @@ -1,7 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) #define p24_20 (0b11111) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) #define p24_20 (0b11111) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) #define p11_7 (0b11111) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) #define p26 (0b1) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c @@ -2,7 +2,7 @@ // REQUIRES: riscv-registered-target // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) #define p26 (0b1) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s -#include +#include #define p27_26 (0b11) #define p26 (0b1) diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c @@ -5,7 +5,7 @@ // RUN: -target-feature +xsfvcp \ // RUN: -fsyntax-only -verify %s -#include +#include #define p27_26 (0b11) #define p26 (0b1) diff --git a/clang/test/Sema/riscv-bad-intrinsic-pragma.c b/clang/test/Sema/riscv-bad-intrinsic-pragma.c --- a/clang/test/Sema/riscv-bad-intrinsic-pragma.c +++ b/clang/test/Sema/riscv-bad-intrinsic-pragma.c @@ -2,7 +2,7 @@ // RUN: 2>&1 | FileCheck %s #pragma clang riscv intrinsic vvvv -// CHECK: warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector' [-Wignored-pragmas] +// CHECK: warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector' or 'sifive_vector' [-Wignored-pragmas] #pragma clang riscv what + 3241 // CHECK: warning: unexpected argument 'what' to '#pragma riscv'; expected 'intrinsic' [-Wignored-pragmas] diff --git a/clang/utils/TableGen/TableGen.cpp b/clang/utils/TableGen/TableGen.cpp --- a/clang/utils/TableGen/TableGen.cpp +++ b/clang/utils/TableGen/TableGen.cpp @@ -91,6 +91,9 @@ GenRISCVVectorBuiltins, GenRISCVVectorBuiltinCG, GenRISCVVectorBuiltinSema, + GenRISCVSiFiveVectorBuiltins, + GenRISCVSiFiveVectorBuiltinCG, + GenRISCVSiFiveVectorBuiltinSema, GenAttrDocs, GenDiagDocs, GenOptDocs, @@ -251,6 +254,12 @@ "Generate riscv_vector_builtin_cg.inc for clang"), clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema", "Generate riscv_vector_builtin_sema.inc for clang"), + clEnumValN(GenRISCVSiFiveVectorBuiltins, "gen-riscv-sifive-vector-builtins", + "Generate riscv_sifive_vector_builtins.inc for clang"), + clEnumValN(GenRISCVSiFiveVectorBuiltinCG, "gen-riscv-sifive-vector-builtin-codegen", + "Generate riscv_sifive_vector_builtin_cg.inc for clang"), + clEnumValN(GenRISCVSiFiveVectorBuiltinSema, "gen-riscv-sifive-vector-builtin-sema", + "Generate riscv_sifive_vector_builtin_sema.inc for clang"), clEnumValN(GenAttrDocs, "gen-attr-docs", "Generate attribute documentation"), clEnumValN(GenDiagDocs, "gen-diag-docs", @@ -472,6 +481,15 @@ case GenRISCVVectorBuiltinSema: EmitRVVBuiltinSema(Records, OS); break; + case GenRISCVSiFiveVectorBuiltins: + EmitRVVBuiltins(Records, OS); + break; + case GenRISCVSiFiveVectorBuiltinCG: + EmitRVVBuiltinCG(Records, OS); + break; + case GenRISCVSiFiveVectorBuiltinSema: + EmitRVVBuiltinSema(Records, OS); + break; case GenAttrDocs: EmitClangAttrDocs(Records, OS); break; diff --git a/llvm/docs/CommandGuide/tblgen.rst b/llvm/docs/CommandGuide/tblgen.rst --- a/llvm/docs/CommandGuide/tblgen.rst +++ b/llvm/docs/CommandGuide/tblgen.rst @@ -348,6 +348,14 @@ Generate ``riscv_vector_builtin_cg.inc`` for Clang. +.. option:: -gen-riscv-sifive-vector-builtins + + Generate ``riscv_sifive_vector_builtins.inc`` for Clang. + +.. option:: -gen-riscv-sifive-vector-builtin-codegen + + Generate ``riscv_sifive_vector_builtin_cg.inc`` for Clang. + .. option:: -gen-attr-docs Generate attribute documentation.