diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -31,8 +31,8 @@ class DeadMachineInstructionElim : public MachineFunctionPass { bool runOnMachineFunction(MachineFunction &MF) override; - const MachineRegisterInfo *MRI; - const TargetInstrInfo *TII; + const MachineRegisterInfo *MRI = nullptr; + const TargetInstrInfo *TII = nullptr; LiveRegUnits LivePhysRegs; public: diff --git a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp --- a/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp +++ b/llvm/lib/CodeGen/ExpandPostRAPseudos.cpp @@ -28,8 +28,8 @@ namespace { struct ExpandPostRA : public MachineFunctionPass { private: - const TargetRegisterInfo *TRI; - const TargetInstrInfo *TII; + const TargetRegisterInfo *TRI = nullptr; + const TargetInstrInfo *TII = nullptr; public: static char ID; // Pass identification, replacement for typeid diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -339,9 +339,9 @@ }; class MachineCopyPropagation : public MachineFunctionPass { - const TargetRegisterInfo *TRI; - const TargetInstrInfo *TII; - const MachineRegisterInfo *MRI; + const TargetRegisterInfo *TRI = nullptr; + const TargetInstrInfo *TII = nullptr; + const MachineRegisterInfo *MRI = nullptr; // Return true if this is a copy instruction and false otherwise. bool UseCopyInstr; diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -115,15 +115,15 @@ namespace { class MachineSinking : public MachineFunctionPass { - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; - MachineRegisterInfo *MRI; // Machine register information - MachineDominatorTree *DT; // Machine dominator tree - MachinePostDominatorTree *PDT; // Machine post dominator tree - MachineCycleInfo *CI; - MachineBlockFrequencyInfo *MBFI; - const MachineBranchProbabilityInfo *MBPI; - AliasAnalysis *AA; + const TargetInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; + MachineRegisterInfo *MRI = nullptr; // Machine register information + MachineDominatorTree *DT = nullptr; // Machine dominator tree + MachinePostDominatorTree *PDT = nullptr; // Machine post dominator tree + MachineCycleInfo *CI = nullptr; + MachineBlockFrequencyInfo *MBFI = nullptr; + const MachineBranchProbabilityInfo *MBPI = nullptr; + AliasAnalysis *AA = nullptr; RegisterClassInfo RegClassInfo; // Remember which edges have been considered for breaking. diff --git a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp --- a/llvm/lib/CodeGen/ProcessImplicitDefs.cpp +++ b/llvm/lib/CodeGen/ProcessImplicitDefs.cpp @@ -27,9 +27,9 @@ /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def /// for each use. Add isUndef marker to implicit_def defs and their uses. class ProcessImplicitDefs : public MachineFunctionPass { - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; - MachineRegisterInfo *MRI; + const TargetInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; + MachineRegisterInfo *MRI = nullptr; SmallSetVector WorkList; diff --git a/llvm/lib/CodeGen/SelectOptimize.cpp b/llvm/lib/CodeGen/SelectOptimize.cpp --- a/llvm/lib/CodeGen/SelectOptimize.cpp +++ b/llvm/lib/CodeGen/SelectOptimize.cpp @@ -98,15 +98,15 @@ class SelectOptimize : public FunctionPass { const TargetMachine *TM = nullptr; - const TargetSubtargetInfo *TSI; + const TargetSubtargetInfo *TSI = nullptr; const TargetLowering *TLI = nullptr; const TargetTransformInfo *TTI = nullptr; - const LoopInfo *LI; - DominatorTree *DT; + const LoopInfo *LI = nullptr; + DominatorTree *DT = nullptr; std::unique_ptr BFI; std::unique_ptr BPI; - ProfileSummaryInfo *PSI; - OptimizationRemarkEmitter *ORE; + ProfileSummaryInfo *PSI = nullptr; + OptimizationRemarkEmitter *ORE = nullptr; TargetSchedModel TSchedModel; public: diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -1744,12 +1744,12 @@ bool SrcOrder; // SUnits - The SUnits for the current graph. - std::vector *SUnits; + std::vector *SUnits = nullptr; MachineFunction &MF; - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; - const TargetLowering *TLI; + const TargetInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; + const TargetLowering *TLI = nullptr; ScheduleDAGRRList *scheduleDAG = nullptr; // SethiUllmanNumbers - The SethiUllman number for each node. diff --git a/llvm/lib/CodeGen/StackColoring.cpp b/llvm/lib/CodeGen/StackColoring.cpp --- a/llvm/lib/CodeGen/StackColoring.cpp +++ b/llvm/lib/CodeGen/StackColoring.cpp @@ -407,8 +407,8 @@ /// StackColoring - A machine pass for merging disjoint stack allocations, /// marked by the LIFETIME_START and LIFETIME_END pseudo instructions. class StackColoring : public MachineFunctionPass { - MachineFrameInfo *MFI; - MachineFunction *MF; + MachineFrameInfo *MFI = nullptr; + MachineFunction *MF = nullptr; /// A class representing liveness information for a single basic block. /// Each bit in the BitVector represents the liveness property @@ -448,7 +448,7 @@ VNInfo::Allocator VNInfoAllocator; /// SlotIndex analysis object. - SlotIndexes *Indexes; + SlotIndexes *Indexes = nullptr; /// The list of lifetime markers found. These markers are to be removed /// once the coloring is done. diff --git a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp --- a/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp +++ b/llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -48,7 +48,7 @@ /// information provided by this pass is optional and not required by the /// aformentioned intrinsic to function. class StackMapLiveness : public MachineFunctionPass { - const TargetRegisterInfo *TRI; + const TargetRegisterInfo *TRI = nullptr; LivePhysRegs LiveRegs; public: diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp --- a/llvm/lib/CodeGen/StackSlotColoring.cpp +++ b/llvm/lib/CodeGen/StackSlotColoring.cpp @@ -59,10 +59,10 @@ namespace { class StackSlotColoring : public MachineFunctionPass { - LiveStacks* LS; - MachineFrameInfo *MFI; - const TargetInstrInfo *TII; - const MachineBlockFrequencyInfo *MBFI; + LiveStacks* LS = nullptr; + MachineFrameInfo *MFI = nullptr; + const TargetInstrInfo *TII = nullptr; + const MachineBlockFrequencyInfo *MBFI = nullptr; // SSIntervals - Spill slot intervals. std::vector SSIntervals; diff --git a/llvm/lib/Target/X86/X86FixupBWInsts.cpp b/llvm/lib/Target/X86/X86FixupBWInsts.cpp --- a/llvm/lib/Target/X86/X86FixupBWInsts.cpp +++ b/llvm/lib/Target/X86/X86FixupBWInsts.cpp @@ -148,8 +148,8 @@ /// Register Liveness information after the current instruction. LivePhysRegs LiveRegs; - ProfileSummaryInfo *PSI; - MachineBlockFrequencyInfo *MBFI; + ProfileSummaryInfo *PSI = nullptr; + MachineBlockFrequencyInfo *MBFI = nullptr; }; char FixupBWInstPass::ID = 0; } diff --git a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp --- a/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp @@ -154,9 +154,9 @@ using EdgeSet = MachineGadgetGraph::EdgeSet; using NodeSet = MachineGadgetGraph::NodeSet; - const X86Subtarget *STI; - const TargetInstrInfo *TII; - const TargetRegisterInfo *TRI; + const X86Subtarget *STI = nullptr; + const TargetInstrInfo *TII = nullptr; + const TargetRegisterInfo *TRI = nullptr; std::unique_ptr getGadgetGraph(MachineFunction &MF, const MachineLoopInfo &MLI,