Index: lib/Target/X86/AsmParser/X86AsmParser.cpp =================================================================== --- lib/Target/X86/AsmParser/X86AsmParser.cpp +++ lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -683,9 +683,12 @@ std::unique_ptr DefaultMemSIOperand(SMLoc Loc); std::unique_ptr DefaultMemDIOperand(SMLoc Loc); + unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg); void AddDefaultSrcDestOperands( OperandVector& Operands, std::unique_ptr &&Src, std::unique_ptr &&Dst); + bool VerifyAndAdjustOperands(OperandVector& OrigOperands, + OperandVector& FinalOperands); std::unique_ptr ParseOperand(); std::unique_ptr ParseATTOperand(); std::unique_ptr ParseIntelOperand(); @@ -746,11 +749,6 @@ bool OmitRegisterFromClobberLists(unsigned RegNo) override; - /// doSrcDstMatch - Returns true if operands are matching in their - /// word size (%si and %di, %esi and %edi, etc.). Order depends on - /// the parsing mode (Intel vs. AT&T). - bool doSrcDstMatch(X86Operand &Op1, X86Operand &Op2); - /// Parses AVX512 specific operand primitives: masked registers ({%k}, {z}) /// and memory broadcasting ({1to}) primitives, updating Operands vector if required. /// \return \c true if no parsing errors occurred, \c false otherwise. @@ -866,27 +864,6 @@ return false; } -bool X86AsmParser::doSrcDstMatch(X86Operand &Op1, X86Operand &Op2) -{ - // Return true and let a normal complaint about bogus operands happen. - if (!Op1.isMem() || !Op2.isMem()) - return true; - - // Actually these might be the other way round if Intel syntax is - // being used. It doesn't matter. - unsigned diReg = Op1.Mem.BaseReg; - unsigned siReg = Op2.Mem.BaseReg; - - if (X86MCRegisterClasses[X86::GR16RegClassID].contains(siReg)) - return X86MCRegisterClasses[X86::GR16RegClassID].contains(diReg); - if (X86MCRegisterClasses[X86::GR32RegClassID].contains(siReg)) - return X86MCRegisterClasses[X86::GR32RegClassID].contains(diReg); - if (X86MCRegisterClasses[X86::GR64RegClassID].contains(siReg)) - return X86MCRegisterClasses[X86::GR64RegClassID].contains(diReg); - // Again, return true and let another error happen. - return true; -} - bool X86AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { MCAsmParser &Parser = getParser(); @@ -1024,6 +1001,35 @@ Loc, Loc, 0); } +unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg) { + bool IsSI = false; + switch (Reg) { + default: + assert("Only (R|E)SI and (R|E)DI are expected!"); + break; + case X86::RSI: + case X86::ESI: + case X86::SI: + IsSI = true; + break; + case X86::RDI: + case X86::EDI: + case X86::DI: + IsSI = false; + break; + } + + switch (RegClassID) { + default: + assert("Unexpected register class"); + return Reg; + case X86::GR64RegClassID: return IsSI ? X86::RSI : X86::RDI; + case X86::GR32RegClassID: return IsSI ? X86::ESI : X86::EDI; + case X86::GR16RegClassID: return IsSI ? X86::SI : X86::DI; + + } +} + void X86AsmParser::AddDefaultSrcDestOperands( OperandVector& Operands, std::unique_ptr &&Src, std::unique_ptr &&Dst) { @@ -1037,6 +1043,68 @@ } } +bool X86AsmParser::VerifyAndAdjustOperands(OperandVector& OrigOperands, + OperandVector& FinalOperands) { + + if (OrigOperands.size() > 1) { + // Check if sizes match, OrigOpernads also contains the instruction name + assert(OrigOperands.size() == FinalOperands.size() + 1 + && "Opernand size mismatch"); + + // Verify types match + int RegClassID = -1; + for (int i = 0; i < FinalOperands.size(); ++i) { + X86Operand &OrigOp = (X86Operand &)*OrigOperands[i + 1]; + X86Operand &FinalOp = (X86Operand &)*FinalOperands[i]; + + if (FinalOp.isReg() && + (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg())) + // Return false and let a normal complaint about bogus operands happen + return false; + + if (FinalOp.isMem()) { + + if (!OrigOp.isMem()) + // Return false and let a normal complaint about bogus operands happen + return false; + + unsigned OrigReg = OrigOp.Mem.BaseReg; + unsigned FinalReg = FinalOp.Mem.BaseReg; + + // If we've already encounterd a register class, make sure all register + // bases are of the same register class + if (RegClassID != -1 && + !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { + return Error(OrigOp.getStartLoc(), + "mismatching source and destination index registers"); + } + + if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) + RegClassID = X86::GR64RegClassID; + else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) + RegClassID = X86::GR32RegClassID; + else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) + RegClassID = X86::GR16RegClassID; + + FinalReg = GetSIDIForRegClass(RegClassID, FinalReg); + + FinalOp.Mem.Size = OrigOp.Mem.Size; + FinalOp.Mem.SegReg = OrigOp.Mem.SegReg; + FinalOp.Mem.BaseReg = FinalReg; // TODO : Orig reg? + } + } + + // Remove old operandss + for (int i = 0; i < FinalOperands.size(); ++i) + OrigOperands.pop_back(); + } + //OrigOperands.append(FinalOperands.begin(), FinalOperands.end()); + for (int i = 0; i < FinalOperands.size(); ++i) + OrigOperands.push_back(std::move(FinalOperands[i])); + + return false; +} + std::unique_ptr X86AsmParser::ParseOperand() { if (isParsingIntelSyntax()) return ParseIntelOperand(); @@ -2259,62 +2327,74 @@ } } + SmallVector, 2> TmpOperands; + bool HadVerifyError = false; + // Append default arguments to "ins[bwld]" - if (Name.startswith("ins") && Operands.size() == 1 && - (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd")) { - AddDefaultSrcDestOperands(Operands, + if (Name.startswith("ins") && + (Operands.size() == 1 || Operands.size() == 3) && + (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" || + Name == "ins")) { + + AddDefaultSrcDestOperands(TmpOperands, X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), DefaultMemDIOperand(NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); } // Append default arguments to "outs[bwld]" - if (Name.startswith("outs") && Operands.size() == 1 && + if (Name.startswith("outs") && + (Operands.size() == 1 || Operands.size() == 3) && (Name == "outsb" || Name == "outsw" || Name == "outsl" || - Name == "outsd" )) { - AddDefaultSrcDestOperands(Operands, + Name == "outsd" || Name == "outs")) { + AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc), X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); } // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate // values of $SIREG according to the mode. It would be nice if this // could be achieved with InstAlias in the tables. - if (Name.startswith("lods") && Operands.size() == 1 && + if (Name.startswith("lods") && + (Operands.size() == 1 || Operands.size() == 2) && (Name == "lods" || Name == "lodsb" || Name == "lodsw" || - Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) - Operands.push_back(DefaultMemSIOperand(NameLoc)); + Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) { + TmpOperands.push_back(DefaultMemSIOperand(NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); + } // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate // values of $DIREG according to the mode. It would be nice if this // could be achieved with InstAlias in the tables. - if (Name.startswith("stos") && Operands.size() == 1 && + if (Name.startswith("stos") && + (Operands.size() == 1 || Operands.size() == 2) && (Name == "stos" || Name == "stosb" || Name == "stosw" || - Name == "stosl" || Name == "stosd" || Name == "stosq")) - Operands.push_back(DefaultMemDIOperand(NameLoc)); + Name == "stosl" || Name == "stosd" || Name == "stosq")) { + TmpOperands.push_back(DefaultMemDIOperand(NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); + } // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate // values of $DIREG according to the mode. It would be nice if this // could be achieved with InstAlias in the tables. - if (Name.startswith("scas") && Operands.size() == 1 && + if (Name.startswith("scas") && + (Operands.size() == 1 || Operands.size() == 2) && (Name == "scas" || Name == "scasb" || Name == "scasw" || - Name == "scasl" || Name == "scasd" || Name == "scasq")) - Operands.push_back(DefaultMemDIOperand(NameLoc)); + Name == "scasl" || Name == "scasd" || Name == "scasq")) { + TmpOperands.push_back(DefaultMemDIOperand(NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); + } // Add default SI and DI operands to "cmps[bwlq]". if (Name.startswith("cmps") && + (Operands.size() == 1 || Operands.size() == 3) && (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" || Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) { - if (Operands.size() == 1) { - AddDefaultSrcDestOperands(Operands, - DefaultMemDIOperand(NameLoc), - DefaultMemSIOperand(NameLoc)); - } else if (Operands.size() == 3) { - X86Operand &Op = (X86Operand &)*Operands[1]; - X86Operand &Op2 = (X86Operand &)*Operands[2]; - if (!doSrcDstMatch(Op, Op2)) - return Error(Op.getStartLoc(), - "mismatching source and destination index registers"); - } + AddDefaultSrcDestOperands(TmpOperands, + DefaultMemDIOperand(NameLoc), + DefaultMemSIOperand(NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); } // Add default SI and DI operands to "movs[bwlq]". @@ -2323,20 +2403,19 @@ Name == "movsl" || Name == "movsd" || Name == "movsq")) || (Name.startswith("smov") && (Name == "smov" || Name == "smovb" || Name == "smovw" || - Name == "smovl" || Name == "smovd" || Name == "smovq"))) { - if (Operands.size() == 1) { - if (Name == "movsd") + Name == "smovl" || Name == "smovd" || Name == "smovq")) && + (Operands.size() == 1 || Operands.size() == 3)) { + if (Name == "movsd" && Operands.size() == 1) Operands.back() = X86Operand::CreateToken("movsl", NameLoc); - AddDefaultSrcDestOperands(Operands, - DefaultMemSIOperand(NameLoc), - DefaultMemDIOperand(NameLoc)); - } else if (Operands.size() == 3) { - X86Operand &Op = (X86Operand &)*Operands[1]; - X86Operand &Op2 = (X86Operand &)*Operands[2]; - if (!doSrcDstMatch(Op, Op2)) - return Error(Op.getStartLoc(), - "mismatching source and destination index registers"); - } + AddDefaultSrcDestOperands(TmpOperands, + DefaultMemSIOperand(NameLoc), + DefaultMemDIOperand(NameLoc)); + HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands); + } + + // Check if we encountered an error for one the string insturctions + if (HadVerifyError) { + return HadVerifyError; } // FIXME: Hack to handle recognize s{hr,ar,hl} $1, . Canonicalize to Index: lib/Target/X86/X86InstrInfo.td =================================================================== --- lib/Target/X86/X86InstrInfo.td +++ lib/Target/X86/X86InstrInfo.td @@ -2745,6 +2745,11 @@ def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; +def : InstAlias<"lods $src", (LODSB srcidx8:$src), 0>; +def : InstAlias<"lods $src", (LODSW srcidx16:$src), 0>; +def : InstAlias<"lods $src", (LODSL srcidx32:$src), 0>; +def : InstAlias<"lods $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; + // stos aliases. Accept the source being omitted because it's implicit in // the mnemonic, or the mnemonic suffix being omitted because it's implicit @@ -2757,6 +2762,11 @@ def : InstAlias<"stos {%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; def : InstAlias<"stos {%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; def : InstAlias<"stos {%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"stos $dst", (STOSB dstidx8:$dst), 0>; +def : InstAlias<"stos $dst", (STOSW dstidx16:$dst), 0>; +def : InstAlias<"stos $dst", (STOSL dstidx32:$dst), 0>; +def : InstAlias<"stos $dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; + // scas aliases. Accept the destination being omitted because it's implicit // in the mnemonic, or the mnemonic suffix being omitted because it's implicit @@ -2769,6 +2779,24 @@ def : InstAlias<"scas {$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; def : InstAlias<"scas {$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; def : InstAlias<"scas {$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; +def : InstAlias<"scas $dst", (SCASB dstidx8:$dst), 0>; +def : InstAlias<"scas $dst", (SCASW dstidx16:$dst), 0>; +def : InstAlias<"scas $dst", (SCASL dstidx32:$dst), 0>; +def : InstAlias<"scas $dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; + +// cmps aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"cmps {$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0>; +def : InstAlias<"cmps {$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0>; +def : InstAlias<"cmps {$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0>; +def : InstAlias<"cmps {$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0>, Requires<[In64BitMode]>; + +// movs aliases. Mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"movs {$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0>; +def : InstAlias<"movs {$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0>; +def : InstAlias<"movs {$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0>; +def : InstAlias<"movs {$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0>, Requires<[In64BitMode]>; // div and idiv aliases for explicit A register. def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; @@ -2881,6 +2909,18 @@ def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; def : InstAlias<"imul{q} {$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; +// ins aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the destination. +def : InstAlias<"ins {%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0>; +def : InstAlias<"ins {%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0>; +def : InstAlias<"ins {%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0>; + +// outs aliases. Accept the mnemonic suffix being omitted because it's implicit +// in the source. +def : InstAlias<"outs {$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0>; +def : InstAlias<"outs {$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0>; +def : InstAlias<"outs {$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0>; + // inb %dx -> inb %al, %dx def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; Index: test/MC/X86/intel-syntax.s =================================================================== --- test/MC/X86/intel-syntax.s +++ test/MC/X86/intel-syntax.s @@ -736,3 +736,18 @@ fbstp tbyte ptr [eax] // CHECK: fbld (%eax) // CHECK: fbstp (%eax) + +ins byte ptr [eax], dx +// CHECK: insb %dx, %es:(%edi) +outs dx, word ptr [eax] +// CHECK: outsw (%esi), %dx +lods dword ptr [eax] +// CHECK: lodsl (%esi), %eax +stos qword ptr [eax] +// CHECK: stosq %rax, %es:(%edi) +scas byte ptr [eax] +// CHECK: scasb %es:(%edi), %al +cmps word ptr [eax], word ptr [ebx] +// CHECK: cmpsw %es:(%edi), (%esi) +movs dword ptr [eax], dword ptr [ebx] +// CHECK: movsl (%esi), %es:(%edi) \ No newline at end of file