diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2374,3 +2374,91 @@ } } } + +class VCIXSuffix { + list suffix = !cond(!eq(range, "c"): ["8mf8", "8mf4", "8mf2", "8m1", "8m2", "8m4", "8m8"], + !eq(range, "s"): ["16mf4", "16mf2", "16m1", "16m2", "16m4", "16m8"], + !eq(range, "i"): ["32mf2", "32m1", "32m2", "32m4", "32m8"], + !eq(range, "l"): ["64m1", "64m2", "64m4", "64m8"]); +} + +class VCIXBuiltinSet intrinsic_types> + : RVVBuiltin { + let Name = name; + let OverloadedName = name; + let IRName = IR_name; + let HasMasked = false; + let IntrinsicTypes = intrinsic_types; +} + +multiclass VCIXBuiltinSet intrinsic_types> { + if !find(prototype, "0") then { + def : VCIXBuiltinSet; + } + def : VCIXBuiltinSet; +} + +multiclass RVVVCIXBuiltinSet range, string prototype, + list intrinsic_types, bit EncodeVtype, + bit UseGPR> { + defvar suffix = !if(EncodeVtype, "", "Uv"); + foreach r = range in { + let RequiredFeatures = !if(!and(UseGPR, !eq(r, "l")), + ["Xsfvcp", "RV64"], ["Xsfvcp"]) in { + // If EncodeVtype is true, then these intrinsic don't have any vector + // types in the output and inputs, but we still need to add vetvli for + // them. So we encode different VTYPE into the intrinsic names, and + // then will know which vsetvli is correct. + if EncodeVtype then { + foreach s = VCIXSuffix.suffix in { + defvar name = NAME # "_u" # s; + defvar IR_name = NAME # "_e" # s; + // Since we already encode the Vtype into the name, so just set + // Log2LMUL to zero. Otherwise the RISCVVEmitter will expand + // lots of redunant intrinsic but have same names. + let Log2LMUL = [0] in + def : VCIXBuiltinSet; + } + } else { + defm : VCIXBuiltinSet; + } + } + } +} + +let SupportOverloading = false in { + defm sf_vc_x_se : RVVVCIXBuiltinSet<["c", "s", "i", "l"], "0KzKzKzUe", [0, 3], /*EncodeVtype*/1, /*UseGPR*/1>; + defm sf_vc_i_se : RVVVCIXBuiltinSet<["c", "s", "i", "l"], "0KzKzKzKz", [2, 3], /*EncodeVtype*/1, /*UseGPR*/0>; + defm sf_vc_xv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUe", [0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_iv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvKz", [0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_vv : RVVVCIXBuiltinSet<["csi", "l"], "0KzKzUvUv", [0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_fv : RVVVCIXBuiltinSet<["si", "l"], "0KzKzUvFe", [0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_xvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUe", [0, 1, 3], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_ivv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvKz", [0, 1, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_vvv : RVVVCIXBuiltinSet<["csi", "l"], "0KzUvUvUv", [0, 1, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_fvv : RVVVCIXBuiltinSet<["si", "l"], "0KzUvUvFe", [0, 1, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_x : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzUe", [-1, 1, 2], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_v_i : RVVVCIXBuiltinSet<["csi", "l"], "UvKzKzKz", [-1, 1, 2], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_xv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUe", [-1, 0, 2], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_v_iv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvKz", [-1, 0, 2], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_vv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUv", [-1, 0, 2], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_fv : RVVVCIXBuiltinSet<["si", "l"], "UvKzUvFe", [-1, 0, 2], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_xvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUe", [-1, 0, 3], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_v_ivv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvKz", [-1, 0, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_vvv : RVVVCIXBuiltinSet<["csi", "l"], "UvKzUvUvUv", [-1, 0, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_fvv : RVVVCIXBuiltinSet<["si", "l"], "UvKzUvUvFe", [-1, 0, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { + defm sf_vc_xvw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUe", [0, 1, 2, 3], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_ivw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvKz", [0, 1, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_vvw : RVVVCIXBuiltinSet<["csi"], "0KzUwUvUv", [0, 1, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_fvw : RVVVCIXBuiltinSet<["si"], "0KzUwUvFe", [0, 1, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_xvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUe", [-1, 0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/1>; + defm sf_vc_v_ivw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvKz", [-1, 0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_vvw : RVVVCIXBuiltinSet<["csi"], "UwKzUwUvUv", [-1, 0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + defm sf_vc_v_fvw : RVVVCIXBuiltinSet<["si"], "UwKzUwUvFe", [-1, 0, 2, 3], /*EncodeVtype*/0, /*UseGPR*/0>; + } +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c @@ -0,0 +1,116 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; +const int p24_20 = 0x1f; +const int p11_7 = 0x1f; + +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u64m1(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u64m2(uint64_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u64m2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u64m4(uint64_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u64m4(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e64m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u64m8(uint64_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u64m8(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_x_se_u64m1(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u64m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_x_se_u64m2(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u64m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_x_se_u64m4(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u64m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_x_se_u64m8(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u64m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_x_u64m1(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u64m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_x_u64m2(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u64m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_x_u64m4(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u64m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_x_u64m8(uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u64m8(p27_26, p24_20, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c @@ -0,0 +1,1690 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; +const int p24_20 = 0x1f; +const int p11_7 = 0x1f; +const int simm5 = 10; + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf8.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf8.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8mf8(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8mf8(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf4.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf4.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8mf4(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf2.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8mf2.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8mf2(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m1.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m1.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8m1(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m2.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m2.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8m2(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m4.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m4.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8m4(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m8.i32.i8.i32(i32 3, i32 31, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e8m8.i64.i8.i64(i64 3, i64 31, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u8m8(uint8_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u8m8(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e16mf4.i32.i16.i32(i32 3, i32 31, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e16mf4.i64.i16.i64(i64 3, i64 31, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u16mf4(uint16_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u16mf4(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e16mf2.i32.i16.i32(i32 3, i32 31, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e16mf2.i64.i16.i64(i64 3, i64 31, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u16mf2(uint16_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u16mf2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m1.i32.i16.i32(i32 3, i32 31, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m1.i64.i16.i64(i64 3, i64 31, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u16m1(uint16_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u16m1(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m2.i32.i16.i32(i32 3, i32 31, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m2.i64.i16.i64(i64 3, i64 31, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u16m2(uint16_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u16m2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m4.i32.i16.i32(i32 3, i32 31, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m4.i64.i16.i64(i64 3, i64 31, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u16m4(uint16_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u16m4(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m8.i32.i16.i32(i32 3, i32 31, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e16m8.i64.i16.i64(i64 3, i64 31, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u16m8(uint16_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u16m8(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e32mf2.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e32mf2.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u32mf2(uint32_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u32mf2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m1.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m1.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u32m1(uint32_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u32m1(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m2.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m2.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u32m2(uint32_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u32m2(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m4.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m4.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u32m4(uint32_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u32m4(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_x_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m8.i32.i32.i32(i32 3, i32 31, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_x_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.x.se.e32m8.i64.i32.i64(i64 3, i64 31, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_x_se_u32m8(uint32_t rs1, size_t vl) { + __riscv_sf_vc_x_se_u32m8(p27_26, p24_20, p11_7, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_x_se_u8mf8(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8mf8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_x_se_u8mf4(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8mf4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_x_se_u8mf2(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8mf2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_x_se_u8m1(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv16i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv16i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_x_se_u8m2(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv32i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv32i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_x_se_u8m4(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv64i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv64i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_x_se_u8m8(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u8m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_x_se_u16mf4(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u16mf4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_x_se_u16mf2(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u16mf2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_x_se_u16m1(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u16m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_x_se_u16m2(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u16m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv16i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv16i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_x_se_u16m4(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u16m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv32i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv32i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_x_se_u16m8(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u16m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv1i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_x_se_u32mf2(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32mf2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv2i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_x_se_u32m1(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv4i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_x_se_u32m2(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv8i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_x_se_u32m4(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv16i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.se.nxv16i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_x_se_u32m8(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_se_u32m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_x_u8mf8(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8mf8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_x_u8mf4(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8mf4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_x_u8mf2(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8mf2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_x_u8m1(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv16i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv16i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_x_u8m2(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv32i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv32i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_x_u8m4(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv64i8.i32.i8.i32(i32 3, i32 31, i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv64i8.i64.i8.i64(i64 3, i64 31, i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_x_u8m8(uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u8m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_x_u16mf4(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u16mf4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_x_u16mf2(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u16mf2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_x_u16m1(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u16m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_x_u16m2(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u16m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv16i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv16i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_x_u16m4(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u16m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv32i16.i32.i16.i32(i32 3, i32 31, i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv32i16.i64.i16.i64(i64 3, i64 31, i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_x_u16m8(uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u16m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv1i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_x_u32mf2(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u32mf2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv2i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_x_u32m1(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m1(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv4i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_x_u32m2(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m2(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv8i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_x_u32m4(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m4(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_x_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv16i32.i32.i32.i32(i32 3, i32 31, i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_x_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.x.nxv16i32.i64.i32.i64(i64 3, i64 31, i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_x_u32m8(uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_x_u32m8(p27_26, p24_20, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8mf8.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8mf8.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8mf8(size_t vl) { + __riscv_sf_vc_i_se_u8mf8(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8mf4.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8mf4.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8mf4(size_t vl) { + __riscv_sf_vc_i_se_u8mf4(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8mf2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8mf2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8mf2(size_t vl) { + __riscv_sf_vc_i_se_u8mf2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m1.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8m1(size_t vl) { + __riscv_sf_vc_i_se_u8m1(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8m2(size_t vl) { + __riscv_sf_vc_i_se_u8m2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m4.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8m4(size_t vl) { + __riscv_sf_vc_i_se_u8m4(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m8.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e8m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u8m8(size_t vl) { + __riscv_sf_vc_i_se_u8m8(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e16mf4.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e16mf4.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u16mf4(size_t vl) { + __riscv_sf_vc_i_se_u16mf4(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e16mf2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e16mf2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u16mf2(size_t vl) { + __riscv_sf_vc_i_se_u16mf2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m1.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u16m1(size_t vl) { + __riscv_sf_vc_i_se_u16m1(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u16m2(size_t vl) { + __riscv_sf_vc_i_se_u16m2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m4.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u16m4(size_t vl) { + __riscv_sf_vc_i_se_u16m4(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m8.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e16m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u16m8(size_t vl) { + __riscv_sf_vc_i_se_u16m8(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e32mf2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e32mf2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u32mf2(size_t vl) { + __riscv_sf_vc_i_se_u32mf2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m1.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u32m1(size_t vl) { + __riscv_sf_vc_i_se_u32m1(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u32m2(size_t vl) { + __riscv_sf_vc_i_se_u32m2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m4.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u32m4(size_t vl) { + __riscv_sf_vc_i_se_u32m4(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m8.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e32m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u32m8(size_t vl) { + __riscv_sf_vc_i_se_u32m8(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m1.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u64m1(size_t vl) { + __riscv_sf_vc_i_se_u64m1(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m2.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m2.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u64m2(size_t vl) { + __riscv_sf_vc_i_se_u64m2(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m4.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m4.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u64m4(size_t vl) { + __riscv_sf_vc_i_se_u64m4(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_i_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m8.i32.i32.i32(i32 3, i32 31, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_i_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.i.se.e64m8.i64.i64.i64(i64 3, i64 31, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_i_se_u64m8(size_t vl) { + __riscv_sf_vc_i_se_u64m8(p27_26, p24_20, p11_7, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_i_se_u8mf8(size_t vl) { + return __riscv_sf_vc_v_i_se_u8mf8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_i_se_u8mf4(size_t vl) { + return __riscv_sf_vc_v_i_se_u8mf4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_i_se_u8mf2(size_t vl) { + return __riscv_sf_vc_v_i_se_u8mf2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_i_se_u8m1(size_t vl) { + return __riscv_sf_vc_v_i_se_u8m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv16i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv16i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_i_se_u8m2(size_t vl) { + return __riscv_sf_vc_v_i_se_u8m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv32i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv32i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_i_se_u8m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u8m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv64i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv64i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_i_se_u8m8(size_t vl) { + return __riscv_sf_vc_v_i_se_u8m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_i_se_u16mf4(size_t vl) { + return __riscv_sf_vc_v_i_se_u16mf4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_i_se_u16mf2(size_t vl) { + return __riscv_sf_vc_v_i_se_u16mf2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_i_se_u16m1(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_i_se_u16m2(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv16i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv16i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_i_se_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv32i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv32i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_i_se_u16m8(size_t vl) { + return __riscv_sf_vc_v_i_se_u16m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_i_se_u32mf2(size_t vl) { + return __riscv_sf_vc_v_i_se_u32mf2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_i_se_u32m1(size_t vl) { + return __riscv_sf_vc_v_i_se_u32m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_i_se_u32m2(size_t vl) { + return __riscv_sf_vc_v_i_se_u32m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_i_se_u32m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u32m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv16i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv16i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_i_se_u32m8(size_t vl) { + return __riscv_sf_vc_v_i_se_u32m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_i_se_u64m1(size_t vl) { + return __riscv_sf_vc_v_i_se_u64m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_i_se_u64m2(size_t vl) { + return __riscv_sf_vc_v_i_se_u64m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_i_se_u64m4(size_t vl) { + return __riscv_sf_vc_v_i_se_u64m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.se.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_i_se_u64m8(size_t vl) { + return __riscv_sf_vc_v_i_se_u64m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_i_u8mf8(size_t vl) { + return __riscv_sf_vc_v_i_u8mf8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_i_u8mf4(size_t vl) { + return __riscv_sf_vc_v_i_u8mf4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_i_u8mf2(size_t vl) { + return __riscv_sf_vc_v_i_u8mf2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_i_u8m1(size_t vl) { + return __riscv_sf_vc_v_i_u8m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv16i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv16i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_i_u8m2(size_t vl) { + return __riscv_sf_vc_v_i_u8m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv32i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv32i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_i_u8m4(size_t vl) { + return __riscv_sf_vc_v_i_u8m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv64i8.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv64i8.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_i_u8m8(size_t vl) { + return __riscv_sf_vc_v_i_u8m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_i_u16mf4(size_t vl) { + return __riscv_sf_vc_v_i_u16mf4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_i_u16mf2(size_t vl) { + return __riscv_sf_vc_v_i_u16mf2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_i_u16m1(size_t vl) { + return __riscv_sf_vc_v_i_u16m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_i_u16m2(size_t vl) { + return __riscv_sf_vc_v_i_u16m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv16i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv16i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_i_u16m4(size_t vl) { + return __riscv_sf_vc_v_i_u16m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv32i16.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv32i16.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_i_u16m8(size_t vl) { + return __riscv_sf_vc_v_i_u16m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_i_u32mf2(size_t vl) { + return __riscv_sf_vc_v_i_u32mf2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_i_u32m1(size_t vl) { + return __riscv_sf_vc_v_i_u32m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_i_u32m2(size_t vl) { + return __riscv_sf_vc_v_i_u32m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_i_u32m4(size_t vl) { + return __riscv_sf_vc_v_i_u32m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv16i32.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv16i32.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_i_u32m8(size_t vl) { + return __riscv_sf_vc_v_i_u32m8(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv1i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_i_u64m1(size_t vl) { + return __riscv_sf_vc_v_i_u64m1(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv2i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_i_u64m2(size_t vl) { + return __riscv_sf_vc_v_i_u64m2(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv4i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_i_u64m4(size_t vl) { + return __riscv_sf_vc_v_i_u64m4(p27_26, p24_20, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_i_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i64.i32.i32.i32(i32 3, i32 31, i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_i_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.i.nxv8i64.i64.i64.i64(i64 3, i64 31, i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_i_u64m8(size_t vl) { + return __riscv_sf_vc_v_i_u64m8(p27_26, p24_20, simm5, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c @@ -0,0 +1,116 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; +const int p11_7 = 0x1f; + +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u64m1(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u64m2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u64m4(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u64m8(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_xv_se_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u64m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_xv_se_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u64m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_xv_se_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u64m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_xv_se_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u64m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_xv_u64m1(vuint64m1_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u64m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_xv_u64m2(vuint64m2_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u64m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_xv_u64m4(vuint64m4_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u64m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_xv_u64m8(vuint64m8_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u64m8(p27_26, vs2, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c @@ -0,0 +1,3244 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; +const int p27 = 1; +const int p11_7 = 0x1f; +const int simm5 = 10; + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i8.nxv1i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i8.nxv1i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8mf8(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i8.nxv2i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i8.nxv2i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8mf4(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i8.nxv4i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i8.nxv4i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8mf2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i8.nxv8i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i8.nxv8i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8m1(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i8.nxv16i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv16i8.nxv16i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8m2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i8.nxv32i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv32i8.nxv32i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8m4(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv64i8.nxv64i8.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv64i8.nxv64i8.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u8m8(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i16.nxv1i16.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i16.nxv1i16.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u16mf4(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i16.nxv2i16.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i16.nxv2i16.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u16mf2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i16.nxv4i16.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i16.nxv4i16.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m1(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i16.nxv8i16.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i16.nxv8i16.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u16m2(vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i16.nxv16i16.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv16i16.nxv16i16.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u16m4(vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m4(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv32i16.nxv32i16.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv32i16.nxv32i16.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u16m8(vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u16m8(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i32.nxv1i32.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i32.nxv1i32.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u32mf2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i32.nxv2i32.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i32.nxv2i32.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u32m1(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i32.nxv4i32.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i32.nxv4i32.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u32m2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i32.nxv8i32.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i32.nxv8i32.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u32m4(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv16i32.nxv16i32.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv16i32.nxv16i32.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u32m8(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv1i64.nxv1i64.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv1i64.nxv1i64.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u64m1(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv2i64.nxv2i64.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv2i64.nxv2i64.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u64m2(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv4i64.nxv4i64.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv4i64.nxv4i64.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u64m4(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vv.se.i32.nxv8i64.nxv8i64.i32(i32 3, i32 31, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vv.se.i64.nxv8i64.nxv8i64.i64(i64 3, i64 31, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vv_se_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) { + __riscv_sf_vc_vv_se_u64m8(p27_26, p11_7, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i8.i32.nxv1i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i8.i64.nxv1i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_vv_se_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8mf8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i8.i32.nxv2i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i8.i64.nxv2i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_vv_se_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8mf4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i8.i32.nxv4i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i8.i64.nxv4i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_vv_se_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8mf2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i8.i32.nxv8i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i8.i64.nxv8i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_vv_se_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv16i8.i32.nxv16i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv16i8.i64.nxv16i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_vv_se_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv32i8.i32.nxv32i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv32i8.i64.nxv32i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_vv_se_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv64i8.i32.nxv64i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv64i8.i64.nxv64i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_vv_se_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u8m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i16.i32.nxv1i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i16.i64.nxv1i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_vv_se_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u16mf4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i16.i32.nxv2i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i16.i64.nxv2i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_vv_se_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u16mf2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i16.i32.nxv4i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i16.i64.nxv4i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_vv_se_u16m1(vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u16m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i16.i32.nxv8i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i16.i64.nxv8i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_vv_se_u16m2(vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u16m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv16i16.i32.nxv16i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv16i16.i64.nxv16i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_vv_se_u16m4(vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u16m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv32i16.i32.nxv32i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv32i16.i64.nxv32i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_vv_se_u16m8(vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u16m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i32.i32.nxv1i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i32.i64.nxv1i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_vv_se_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u32mf2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i32.i32.nxv2i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i32.i64.nxv2i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_vv_se_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u32m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i32.nxv4i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i32.i64.nxv4i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_vv_se_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u32m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i32.i32.nxv8i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i32.i64.nxv8i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_vv_se_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u32m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv16i32.i32.nxv16i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv16i32.i64.nxv16i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_vv_se_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u32m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i64.i32.nxv1i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv1i64.i64.nxv1i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_vv_se_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u64m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i64.i32.nxv2i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv2i64.i64.nxv2i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_vv_se_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u64m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i64.i32.nxv4i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv4i64.i64.nxv4i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_vv_se_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u64m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i64.i32.nxv8i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.se.nxv8i64.i64.nxv8i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_vv_se_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_se_u64m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i8.i32.nxv1i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i8.i64.nxv1i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_vv_u8mf8(vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8mf8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i8.i32.nxv2i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i8.i64.nxv2i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_vv_u8mf4(vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8mf4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i8.i32.nxv4i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i8.i64.nxv4i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_vv_u8mf2(vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8mf2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i8.i32.nxv8i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i8.i64.nxv8i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_vv_u8m1(vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv16i8.i32.nxv16i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv16i8.i64.nxv16i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_vv_u8m2(vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv32i8.i32.nxv32i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv32i8.i64.nxv32i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_vv_u8m4(vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv64i8.i32.nxv64i8.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv64i8.i64.nxv64i8.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_vv_u8m8(vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u8m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i16.i32.nxv1i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i16.i64.nxv1i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_vv_u16mf4(vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u16mf4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i16.i32.nxv2i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i16.i64.nxv2i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_vv_u16mf2(vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u16mf2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i16.i32.nxv4i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i16.i64.nxv4i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_vv_u16m1(vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u16m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i16.i32.nxv8i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i16.i64.nxv8i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_vv_u16m2(vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u16m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv16i16.i32.nxv16i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv16i16.i64.nxv16i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_vv_u16m4(vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u16m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv32i16.i32.nxv32i16.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv32i16.i64.nxv32i16.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_vv_u16m8(vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u16m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i32.i32.nxv1i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i32.i64.nxv1i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_vv_u32mf2(vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u32mf2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i32.i32.nxv2i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i32.i64.nxv2i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_vv_u32m1(vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u32m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i32.i32.nxv4i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i32.i64.nxv4i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_vv_u32m2(vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u32m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i32.i32.nxv8i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i32.i64.nxv8i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_vv_u32m4(vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u32m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv16i32.i32.nxv16i32.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv16i32.i64.nxv16i32.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_vv_u32m8(vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u32m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i64.i32.nxv1i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv1i64.i64.nxv1i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_vv_u64m1(vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u64m1(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i64.i32.nxv2i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv2i64.i64.nxv2i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_vv_u64m2(vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u64m2(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i64.i32.nxv4i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv4i64.i64.nxv4i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_vv_u64m4(vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u64m4(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vv_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i64.i32.nxv8i64.i32(i32 3, [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vv.nxv8i64.i64.nxv8i64.i64(i64 3, [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_vv_u64m8(vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vv_u64m8(p27_26, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv1i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8mf8(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv2i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8mf4(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv4i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8mf2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv8i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8m1(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv16i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv16i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8m2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv32i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv32i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8m4(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv64i8.i8.i32(i32 3, i32 31, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv64i8.i8.i64(i64 3, i64 31, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u8m8(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv1i16.i16.i32(i32 3, i32 31, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i16.i16.i64(i64 3, i64 31, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u16mf4(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv2i16.i16.i32(i32 3, i32 31, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i16.i16.i64(i64 3, i64 31, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u16mf2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv4i16.i16.i32(i32 3, i32 31, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i16.i16.i64(i64 3, i64 31, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u16m1(vuint16m1_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m1(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv8i16.i16.i32(i32 3, i32 31, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i16.i16.i64(i64 3, i64 31, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u16m2(vuint16m2_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv16i16.i16.i32(i32 3, i32 31, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv16i16.i16.i64(i64 3, i64 31, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u16m4(vuint16m4_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m4(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv32i16.i16.i32(i32 3, i32 31, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv32i16.i16.i64(i64 3, i64 31, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u16m8(vuint16m8_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u16m8(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv1i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i32.i32.i64(i64 3, i64 31, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u32mf2(vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u32mf2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv2i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv2i32.i32.i64(i64 3, i64 31, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u32m1(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv4i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv4i32.i32.i64(i64 3, i64 31, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u32m2(vuint32m2_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u32m2(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv8i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv8i32.i32.i64(i64 3, i64 31, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u32m4(vuint32m4_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u32m4(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xv.se.i32.nxv16i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xv.se.i64.nxv16i32.i32.i64(i64 3, i64 31, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xv_se_u32m8(vuint32m8_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xv_se_u32m8(p27_26, p11_7, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_xv_se_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8mf8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_xv_se_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8mf4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_xv_se_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8mf2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_xv_se_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv16i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv16i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_xv_se_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv32i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv32i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_xv_se_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv64i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv64i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_xv_se_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u8m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_xv_se_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u16mf4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_xv_se_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u16mf2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_xv_se_u16m1(vuint16m1_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u16m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_xv_se_u16m2(vuint16m2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u16m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv16i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv16i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_xv_se_u16m4(vuint16m4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u16m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv32i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv32i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_xv_se_u16m8(vuint16m8_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u16m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv1i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_xv_se_u32mf2(vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32mf2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv2i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_xv_se_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv4i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_xv_se_u32m2(vuint32m2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv8i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_xv_se_u32m4(vuint32m4_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv16i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.se.nxv16i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_xv_se_u32m8(vuint32m8_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_se_u32m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_xv_u8mf8(vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8mf8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_xv_u8mf4(vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8mf4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_xv_u8mf2(vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8mf2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_xv_u8m1(vuint8m1_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv16i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv16i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_xv_u8m2(vuint8m2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv32i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv32i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_xv_u8m4(vuint8m4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv64i8.i32.i8.i32(i32 3, [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv64i8.i64.i8.i64(i64 3, [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_xv_u8m8(vuint8m8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u8m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_xv_u16mf4(vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u16mf4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_xv_u16mf2(vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u16mf2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_xv_u16m1(vuint16m1_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u16m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_xv_u16m2(vuint16m2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u16m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv16i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv16i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_xv_u16m4(vuint16m4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u16m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv32i16.i32.i16.i32(i32 3, [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv32i16.i64.i16.i64(i64 3, [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_xv_u16m8(vuint16m8_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u16m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv1i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_xv_u32mf2(vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32mf2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv2i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_xv_u32m1(vuint32m1_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m1(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv4i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_xv_u32m2(vuint32m2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m2(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv8i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_xv_u32m4(vuint32m4_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m4(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv16i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xv.nxv16i32.i64.i32.i64(i64 3, [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_xv_u32m8(vuint32m8_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xv_u32m8(p27_26, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8mf8(vuint8mf8_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8mf8(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8mf4(vuint8mf4_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8mf4(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8mf2(vuint8mf2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8mf2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8m1(vuint8m1_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8m1(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv16i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv16i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8m2(vuint8m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8m2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv32i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv32i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8m4(vuint8m4_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8m4(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv64i8.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv64i8.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u8m8(vuint8m8_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u8m8(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i16.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i16.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u16mf4(vuint16mf4_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16mf4(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i16.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i16.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u16mf2(vuint16mf2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16mf2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i16.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i16.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u16m1(vuint16m1_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m1(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i16.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i16.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u16m2(vuint16m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv16i16.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv16i16.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u16m4(vuint16m4_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m4(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv32i16.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv32i16.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u16m8(vuint16m8_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u16m8(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i32.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u32mf2(vuint32mf2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u32mf2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i32.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u32m1(vuint32m1_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u32m1(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i32.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u32m2(vuint32m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u32m2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i32.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u32m4(vuint32m4_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u32m4(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv16i32.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv16i32.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u32m8(vuint32m8_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u32m8(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv1i64.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u64m1(vuint64m1_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u64m1(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv2i64.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv2i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u64m2(vuint64m2_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u64m2(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv4i64.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv4i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u64m4(vuint64m4_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u64m4(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_iv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.iv.se.i32.nxv8i64.i32.i32(i32 3, i32 31, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_iv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.iv.se.i64.nxv8i64.i64.i64(i64 3, i64 31, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_iv_se_u64m8(vuint64m8_t vs2, size_t vl) { + __riscv_sf_vc_iv_se_u64m8(p27_26, p11_7, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_iv_se_u8mf8(vuint8mf8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8mf8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_iv_se_u8mf4(vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8mf4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_iv_se_u8mf2(vuint8mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8mf2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_iv_se_u8m1(vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv16i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv16i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_iv_se_u8m2(vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv32i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv32i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_iv_se_u8m4(vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv64i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv64i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_iv_se_u8m8(vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u8m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_iv_se_u16mf4(vuint16mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u16mf4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_iv_se_u16mf2(vuint16mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u16mf2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_iv_se_u16m1(vuint16m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u16m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_iv_se_u16m2(vuint16m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u16m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv16i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv16i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_iv_se_u16m4(vuint16m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u16m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv32i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv32i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_iv_se_u16m8(vuint16m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u16m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_iv_se_u32mf2(vuint32mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32mf2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_iv_se_u32m1(vuint32m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_iv_se_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_iv_se_u32m4(vuint32m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv16i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv16i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_iv_se_u32m8(vuint32m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u32m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv1i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_iv_se_u64m1(vuint64m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u64m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv2i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_iv_se_u64m2(vuint64m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u64m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv4i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_iv_se_u64m4(vuint64m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u64m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.se.nxv8i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_iv_se_u64m8(vuint64m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_se_u64m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_iv_u8mf8(vuint8mf8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8mf8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_iv_u8mf4(vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8mf4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_iv_u8mf2(vuint8mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8mf2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_iv_u8m1(vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv16i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv16i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_iv_u8m2(vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv32i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv32i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_iv_u8m4(vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv64i8.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv64i8.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_iv_u8m8(vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u8m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_iv_u16mf4(vuint16mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u16mf4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_iv_u16mf2(vuint16mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u16mf2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_iv_u16m1(vuint16m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u16m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_iv_u16m2(vuint16m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u16m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv16i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv16i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_iv_u16m4(vuint16m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u16m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv32i16.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv32i16.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_iv_u16m8(vuint16m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u16m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_iv_u32mf2(vuint32mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32mf2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_iv_u32m1(vuint32m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_iv_u32m2(vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_iv_u32m4(vuint32m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv16i32.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv16i32.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_iv_u32m8(vuint32m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u32m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv1i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_iv_u64m1(vuint64m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u64m1(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv2i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_iv_u64m2(vuint64m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u64m2(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv4i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_iv_u64m4(vuint64m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u64m4(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_iv_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i64.i32.i32.i32(i32 3, [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_iv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.iv.nxv8i64.i64.i64.i64(i64 3, [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_iv_u64m8(vuint64m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_iv_u64m8(p27_26, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv1i16.f16.i32(i32 1, i32 31, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv1i16.f16.i64(i64 1, i64 31, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u16mf4(vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16mf4(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv2i16.f16.i32(i32 1, i32 31, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv2i16.f16.i64(i64 1, i64 31, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u16mf2(vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16mf2(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv4i16.f16.i32(i32 1, i32 31, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv4i16.f16.i64(i64 1, i64 31, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u16m1(vuint16m1_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16m1(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv8i16.f16.i32(i32 1, i32 31, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv8i16.f16.i64(i64 1, i64 31, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u16m2(vuint16m2_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16m2(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv16i16.f16.i32(i32 1, i32 31, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv16i16.f16.i64(i64 1, i64 31, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u16m4(vuint16m4_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16m4(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv32i16.f16.i32(i32 1, i32 31, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv32i16.f16.i64(i64 1, i64 31, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u16m8(vuint16m8_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fv_se_u16m8(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv1i32.f32.i32(i32 1, i32 31, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv1i32.f32.i64(i64 1, i64 31, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u32mf2(vuint32mf2_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fv_se_u32mf2(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv2i32.f32.i32(i32 1, i32 31, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv2i32.f32.i64(i64 1, i64 31, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u32m1(vuint32m1_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fv_se_u32m1(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv4i32.f32.i32(i32 1, i32 31, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv4i32.f32.i64(i64 1, i64 31, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u32m2(vuint32m2_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fv_se_u32m2(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv8i32.f32.i32(i32 1, i32 31, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv8i32.f32.i64(i64 1, i64 31, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u32m4(vuint32m4_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fv_se_u32m4(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv16i32.f32.i32(i32 1, i32 31, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv16i32.f32.i64(i64 1, i64 31, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u32m8(vuint32m8_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fv_se_u32m8(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv1i64.f64.i32(i32 1, i32 31, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv1i64.f64.i64(i64 1, i64 31, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u64m1(vuint64m1_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fv_se_u64m1(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv2i64.f64.i32(i32 1, i32 31, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv2i64.f64.i64(i64 1, i64 31, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u64m2(vuint64m2_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fv_se_u64m2(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv4i64.f64.i32(i32 1, i32 31, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv4i64.f64.i64(i64 1, i64 31, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u64m4(vuint64m4_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fv_se_u64m4(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fv.se.i32.nxv8i64.f64.i32(i32 1, i32 31, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fv.se.i64.nxv8i64.f64.i64(i64 1, i64 31, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fv_se_u64m8(vuint64m8_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fv_se_u64m8(p27, p11_7, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv1i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv1i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_fv_se_u16mf4(vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16mf4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv2i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv2i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_fv_se_u16mf2(vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16mf2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv4i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv4i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_fv_se_u16m1(vuint16m1_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16m1(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv8i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv8i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_fv_se_u16m2(vuint16m2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16m2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv16i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv16i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_fv_se_u16m4(vuint16m4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16m4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv32i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv32i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_fv_se_u16m8(vuint16m8_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u16m8(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv1i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv1i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_fv_se_u32mf2(vuint32mf2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u32mf2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv2i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv2i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_fv_se_u32m1(vuint32m1_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u32m1(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv4i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_fv_se_u32m2(vuint32m2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u32m2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv8i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv8i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_fv_se_u32m4(vuint32m4_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u32m4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv16i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv16i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_fv_se_u32m8(vuint32m8_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u32m8(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv1i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv1i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_fv_se_u64m1(vuint64m1_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u64m1(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv2i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv2i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_fv_se_u64m2(vuint64m2_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u64m2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv4i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv4i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_fv_se_u64m4(vuint64m4_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u64m4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv8i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.se.nxv8i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_fv_se_u64m8(vuint64m8_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_se_u64m8(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv1i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv1i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_fv_u16mf4(vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16mf4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv2i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv2i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_fv_u16mf2(vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16mf2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv4i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv4i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_fv_u16m1(vuint16m1_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16m1(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv8i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv8i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_fv_u16m2(vuint16m2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16m2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv16i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv16i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_fv_u16m4(vuint16m4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16m4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv32i16.i32.f16.i32(i32 1, [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv32i16.i64.f16.i64(i64 1, [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_fv_u16m8(vuint16m8_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u16m8(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv1i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv1i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_fv_u32mf2(vuint32mf2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u32mf2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv2i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv2i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_fv_u32m1(vuint32m1_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u32m1(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv4i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv4i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_fv_u32m2(vuint32m2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u32m2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv8i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv8i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_fv_u32m4(vuint32m4_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u32m4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv16i32.i32.f32.i32(i32 1, [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv16i32.i64.f32.i64(i64 1, [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_fv_u32m8(vuint32m8_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u32m8(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv1i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv1i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_fv_u64m1(vuint64m1_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u64m1(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv2i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv2i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_fv_u64m2(vuint64m2_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u64m2(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv4i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv4i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_fv_u64m4(vuint64m4_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u64m4(p27, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fv_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv8i64.i32.f64.i32(i32 1, [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fv.nxv8i64.i64.f64.i64(i64 1, [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_fv_u64m8(vuint64m8_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fv_u64m8(p27, vs2, fs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c @@ -0,0 +1,115 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; + +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u64m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u64m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u64m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u64m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_xvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u64m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_xvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u64m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_xvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u64m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_xvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u64m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_xvv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u64m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_xvv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u64m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_xvv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u64m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_xvv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, uint64_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u64m8(p27_26, vd, vs2, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c @@ -0,0 +1,3243 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; +const int p27 = 1; +const int simm5 = 10; + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i8.nxv1i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8mf8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i8.nxv2i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i8.nxv2i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i8.nxv4i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i8.nxv4i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i8.nxv8i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i8.nxv8i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i8.nxv16i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv16i8.nxv16i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i8.nxv32i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv32i8.nxv32i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv64i8.nxv64i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv64i8.nxv64i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u8m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i16.nxv1i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i16.nxv1i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u16mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i16.nxv2i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i16.nxv2i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u16mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i16.nxv4i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i16.nxv4i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u16m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i16.nxv8i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i16.nxv8i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u16m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i16.nxv16i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv16i16.nxv16i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u16m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv32i16.nxv32i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv32i16.nxv32i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u16m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i32.nxv1i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i32.nxv1i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u32mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i32.nxv2i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i32.nxv2i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u32m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i32.nxv4i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i32.nxv4i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u32m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i32.nxv8i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i32.nxv8i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u32m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv16i32.nxv16i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv16i32.nxv16i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u32m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i64.nxv1i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv1i64.nxv1i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv2i64.nxv2i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv2i64.nxv2i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv4i64.nxv4i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv4i64.nxv4i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i32.nxv8i64.nxv8i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvv.se.i64.nxv8i64.nxv8i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) { + __riscv_sf_vc_vvv_se_u64m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.i32.nxv1i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i8.i64.nxv1i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_vvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8mf8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.i32.nxv2i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i8.i64.nxv2i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_vvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.i32.nxv4i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i8.i64.nxv4i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_vvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.i32.nxv8i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i8.i64.nxv8i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_vvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.i32.nxv16i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv16i8.i64.nxv16i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_vvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.i32.nxv32i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv32i8.i64.nxv32i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_vvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.i32.nxv64i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv64i8.i64.nxv64i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_vvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u8m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.i32.nxv1i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i16.i64.nxv1i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_vvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u16mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.i32.nxv2i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i16.i64.nxv2i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_vvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u16mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.i32.nxv4i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i16.i64.nxv4i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_vvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u16m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.i32.nxv8i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i16.i64.nxv8i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_vvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u16m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.i32.nxv16i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv16i16.i64.nxv16i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_vvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u16m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.i32.nxv32i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv32i16.i64.nxv32i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_vvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u16m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.i32.nxv1i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i32.i64.nxv1i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_vvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.i32.nxv2i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i32.i64.nxv2i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_vvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.i32.nxv4i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i32.i64.nxv4i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_vvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.i32.nxv8i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i32.i64.nxv8i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_vvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.i32.nxv16i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv16i32.i64.nxv16i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_vvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u32m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.i32.nxv1i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv1i64.i64.nxv1i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_vvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u64m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.i32.nxv2i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv2i64.i64.nxv2i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_vvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u64m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.i32.nxv4i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv4i64.i64.nxv4i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_vvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u64m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.i32.nxv8i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.se.nxv8i64.i64.nxv8i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_vvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_se_u64m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i8.i32.nxv1i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i8.i64.nxv1i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_vvv_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8mf8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i8.i32.nxv2i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i8.i64.nxv2i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_vvv_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i8.i32.nxv4i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i8.i64.nxv4i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_vvv_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i8.i32.nxv8i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i8.i64.nxv8i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_vvv_u8m1(vuint8m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv16i8.i32.nxv16i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv16i8.i64.nxv16i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_vvv_u8m2(vuint8m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv32i8.i32.nxv32i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv32i8.i64.nxv32i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_vvv_u8m4(vuint8m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv64i8.i32.nxv64i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv64i8.i64.nxv64i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_vvv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u8m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i16.i32.nxv1i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i16.i64.nxv1i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_vvv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u16mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i16.i32.nxv2i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i16.i64.nxv2i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_vvv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u16mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i16.i32.nxv4i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i16.i64.nxv4i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_vvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u16m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i16.i32.nxv8i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i16.i64.nxv8i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_vvv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u16m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv16i16.i32.nxv16i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv16i16.i64.nxv16i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_vvv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u16m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv32i16.i32.nxv32i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv32i16.i64.nxv32i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_vvv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, vuint16m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u16m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i32.i32.nxv1i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i32.i64.nxv1i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_vvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i32.i32.nxv2i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i32.i64.nxv2i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_vvv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i32.i32.nxv4i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i32.i64.nxv4i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_vvv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i32.i32.nxv8i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i32.i64.nxv8i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_vvv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv16i32.i32.nxv16i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv16i32.i64.nxv16i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_vvv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, vuint32m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u32m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i64.i32.nxv1i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv1i64.i64.nxv1i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_vvv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, vuint64m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u64m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i64.i32.nxv2i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv2i64.i64.nxv2i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_vvv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, vuint64m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u64m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i64.i32.nxv4i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv4i64.i64.nxv4i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_vvv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, vuint64m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u64m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvv_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i64.i32.nxv8i64.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvv.nxv8i64.i64.nxv8i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_vvv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, vuint64m8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvv_u64m8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8mf8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv16i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv32i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv32i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv64i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv64i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u8m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u16mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u16mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u16m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u16m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv16i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u16m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv32i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv32i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u16m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv2i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv4i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv8i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i32.nxv16i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvv.se.i64.nxv16i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvv_se_u32m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_xvv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8mf8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_xvv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_xvv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_xvv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv16i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_xvv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv32i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_xvv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv64i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_xvv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u8m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_xvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_xvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_xvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_xvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv16i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_xvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv32i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_xvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u16m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv1i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_xvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u32mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv2i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_xvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u32m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv4i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_xvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u32m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv8i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_xvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u32m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.se.nxv16i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_xvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_se_u32m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_xvv_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8mf8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_xvv_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_xvv_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_xvv_u8m1(vuint8m1_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv16i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv16i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_xvv_u8m2(vuint8m2_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv32i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv32i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_xvv_u8m4(vuint8m4_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv64i8.i32.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv64i8.i64.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_xvv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u8m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_xvv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_xvv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_xvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_xvv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv16i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv16i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_xvv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv32i16.i32.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv32i16.i64.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_xvv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u16m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv1i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_xvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u32mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv2i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_xvv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u32m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv4i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_xvv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u32m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv8i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_xvv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u32m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv16i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvv.nxv16i32.i64.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_xvv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvv_u32m8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8mf8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv16i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv16i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv32i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv32i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv64i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv64i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u8m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u16mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u16mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u16m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u16m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv16i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv16i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u16m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv32i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv32i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u16m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u32mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u32m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u32m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u32m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv16i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv16i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u32m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv1i64.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv1i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv2i64.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv2i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv4i64.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv4i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i32.nxv8i64.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivv.se.i64.nxv8i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, size_t vl) { + __riscv_sf_vc_ivv_se_u64m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_ivv_se_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8mf8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_ivv_se_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_ivv_se_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_ivv_se_u8m1(vuint8m1_t vd, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv16i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_ivv_se_u8m2(vuint8m2_t vd, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv32i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_ivv_se_u8m4(vuint8m4_t vd, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv64i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_ivv_se_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u8m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_ivv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u16mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_ivv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u16mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_ivv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u16m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_ivv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u16m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv16i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_ivv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u16m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv32i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_ivv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u16m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_ivv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u32mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_ivv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u32m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_ivv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u32m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_ivv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u32m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv16i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_ivv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u32m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv1i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_ivv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u64m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv2i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_ivv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u64m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv4i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_ivv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u64m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.se.nxv8i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_ivv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_se_u64m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf8_t test_sf_vc_v_ivv_u8mf8(vuint8mf8_t vd, vuint8mf8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8mf8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf4_t test_sf_vc_v_ivv_u8mf4(vuint8mf4_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8mf2_t test_sf_vc_v_ivv_u8mf2(vuint8mf2_t vd, vuint8mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m1_t test_sf_vc_v_ivv_u8m1(vuint8m1_t vd, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv16i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv16i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m2_t test_sf_vc_v_ivv_u8m2(vuint8m2_t vd, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv32i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv32i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m4_t test_sf_vc_v_ivv_u8m4(vuint8m4_t vd, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u8m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv64i8.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u8m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv64i8.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint8m8_t test_sf_vc_v_ivv_u8m8(vuint8m8_t vd, vuint8m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u8m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_ivv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u16mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_ivv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u16mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_ivv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u16m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_ivv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u16m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv16i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv16i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_ivv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u16m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv32i16.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv32i16.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_ivv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u16m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_ivv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u32mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_ivv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u32m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_ivv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u32m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_ivv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u32m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv16i32.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv16i32.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_ivv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u32m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv1i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_ivv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u64m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv2i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_ivv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u64m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv4i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_ivv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u64m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivv_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i64.i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivv.nxv8i64.i64.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_ivv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivv_u64m8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv1i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv1i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u16mf4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv2i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv2i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u16mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv4i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv4i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u16m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv8i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv8i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u16m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv16i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv16i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u16m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv32i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv32i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u16m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv1i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv1i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv2i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv2i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv4i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv4i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv8i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv8i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv16i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv16i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u32m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv1i64.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv1i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u64m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv2i64.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv2i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u64m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv4i64.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv4i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u64m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i32.nxv8i64.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvv.se.i64.nxv8i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, double fs1, size_t vl) { + __riscv_sf_vc_fvv_se_u64m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv1i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv1i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_fvv_se_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16mf4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv2i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv2i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_fvv_se_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv4i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv4i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_fvv_se_u16m1(vuint16m1_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv8i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv8i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_fvv_se_u16m2(vuint16m2_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv16i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv16i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_fvv_se_u16m4(vuint16m4_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv32i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv32i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_fvv_se_u16m8(vuint16m8_t vd, vuint16m8_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u16m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv1i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv1i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_fvv_se_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u32mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv2i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv2i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_fvv_se_u32m1(vuint32m1_t vd, vuint32m1_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u32m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv4i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv4i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_fvv_se_u32m2(vuint32m2_t vd, vuint32m2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u32m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv8i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv8i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_fvv_se_u32m4(vuint32m4_t vd, vuint32m4_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u32m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv16i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv16i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_fvv_se_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u32m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv1i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv1i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_fvv_se_u64m1(vuint64m1_t vd, vuint64m1_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u64m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv2i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv2i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_fvv_se_u64m2(vuint64m2_t vd, vuint64m2_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u64m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv4i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv4i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_fvv_se_u64m4(vuint64m4_t vd, vuint64m4_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u64m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_se_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv8i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_se_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.se.nxv8i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_fvv_se_u64m8(vuint64m8_t vd, vuint64m8_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_se_u64m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv1i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv1i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_fvv_u16mf4(vuint16mf4_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16mf4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv2i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv2i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_fvv_u16mf2(vuint16mf2_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv4i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv4i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_fvv_u16m1(vuint16m1_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv8i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv8i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_fvv_u16m2(vuint16m2_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv16i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv16i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_fvv_u16m4(vuint16m4_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u16m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv32i16.i32.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv32i16.i64.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_fvv_u16m8(vuint16m8_t vd, vuint16m8_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u16m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv1i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv1i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_fvv_u32mf2(vuint32mf2_t vd, vuint32mf2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u32mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv2i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv2i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_fvv_u32m1(vuint32m1_t vd, vuint32m1_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u32m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv4i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv4i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_fvv_u32m2(vuint32m2_t vd, vuint32m2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u32m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv8i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv8i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_fvv_u32m4(vuint32m4_t vd, vuint32m4_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u32m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u32m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv16i32.i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u32m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv16i32.i64.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_fvv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u32m8(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv1i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv1i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_fvv_u64m1(vuint64m1_t vd, vuint64m1_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u64m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv2i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv2i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_fvv_u64m2(vuint64m2_t vd, vuint64m2_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u64m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv4i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv4i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_fvv_u64m4(vuint64m4_t vd, vuint64m4_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u64m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvv_u64m8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv8i64.i32.f64.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvv_u64m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvv.nxv8i64.i64.f64.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], double [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_fvv_u64m8(vuint64m8_t vd, vuint64m8_t vs2, double fs1, size_t vl) { + return __riscv_sf_vc_v_fvv_u64m8(p27, vd, vs2, fs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c @@ -0,0 +1,2277 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include + +const int p27_26 = 3; +const int p27 = 1; +const int simm5 = 10; + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv1i16.nxv1i8.nxv1i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u8mf8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i16.nxv2i8.nxv2i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv2i16.nxv2i8.nxv2i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u8mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i16.nxv4i8.nxv4i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv4i16.nxv4i8.nxv4i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u8mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i16.nxv8i8.nxv8i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv8i16.nxv8i8.nxv8i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u8m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i16.nxv16i8.nxv16i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv16i16.nxv16i8.nxv16i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u8m2(vuint16m4_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u8m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv32i16.nxv32i8.nxv32i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv32i16.nxv32i8.nxv32i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u8m4(vuint16m8_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u8m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i32.nxv1i16.nxv1i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv1i32.nxv1i16.nxv1i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i32.nxv2i16.nxv2i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv2i32.nxv2i16.nxv2i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i32.nxv4i16.nxv4i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv4i32.nxv4i16.nxv4i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i32.nxv8i16.nxv8i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv8i32.nxv8i16.nxv8i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv16i32.nxv16i16.nxv16i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv16i32.nxv16i16.nxv16i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u16m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i64.nxv1i32.nxv1i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv1i64.nxv1i32.nxv1i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u32mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv2i64.nxv2i32.nxv2i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv2i64.nxv2i32.nxv2i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u32m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv4i64.nxv4i32.nxv4i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv4i64.nxv4i32.nxv4i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u32m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i32.nxv8i64.nxv8i32.nxv8i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_vvw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.vvw.se.i64.nxv8i64.nxv8i32.nxv8i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_vvw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + __riscv_sf_vc_vvw_se_u32m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv1i16.i32.nxv1i8.nxv1i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv1i16.i64.nxv1i8.nxv1i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_vvw_se_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8mf8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv2i16.i32.nxv2i8.nxv2i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv2i16.i64.nxv2i8.nxv2i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_vvw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv4i16.i32.nxv4i8.nxv4i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv4i16.i64.nxv4i8.nxv4i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_vvw_se_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv8i16.i32.nxv8i8.nxv8i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv8i16.i64.nxv8i8.nxv8i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_vvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv16i16.i32.nxv16i8.nxv16i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv16i16.i64.nxv16i8.nxv16i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_vvw_se_u8m2(vuint16m4_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv32i16.i32.nxv32i8.nxv32i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv32i16.i64.nxv32i8.nxv32i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_vvw_se_u8m4(vuint16m8_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u8m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv1i32.i32.nxv1i16.nxv1i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv1i32.i64.nxv1i16.nxv1i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_vvw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u16mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv2i32.i32.nxv2i16.nxv2i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv2i32.i64.nxv2i16.nxv2i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_vvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u16mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv4i32.i32.nxv4i16.nxv4i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv4i32.i64.nxv4i16.nxv4i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_vvw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u16m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv8i32.i32.nxv8i16.nxv8i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv8i32.i64.nxv8i16.nxv8i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_vvw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u16m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv16i32.i32.nxv16i16.nxv16i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv16i32.i64.nxv16i16.nxv16i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_vvw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u16m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv1i64.i32.nxv1i32.nxv1i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv1i64.i64.nxv1i32.nxv1i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_vvw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u32mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv2i64.i32.nxv2i32.nxv2i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv2i64.i64.nxv2i32.nxv2i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_vvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u32m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv4i64.i32.nxv4i32.nxv4i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv4i64.i64.nxv4i32.nxv4i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_vvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u32m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv8i64.i32.nxv8i32.nxv8i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.se.nxv8i64.i64.nxv8i32.nxv8i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_vvw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_se_u32m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv1i16.i32.nxv1i8.nxv1i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv1i16.i64.nxv1i8.nxv1i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_vvw_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, vuint8mf8_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8mf8(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv2i16.i32.nxv2i8.nxv2i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv2i16.i64.nxv2i8.nxv2i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_vvw_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, vuint8mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv4i16.i32.nxv4i8.nxv4i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv4i16.i64.nxv4i8.nxv4i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_vvw_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, vuint8mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv8i16.i32.nxv8i8.nxv8i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv8i16.i64.nxv8i8.nxv8i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_vvw_u8m1(vuint16m2_t vd, vuint8m1_t vs2, vuint8m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv16i16.i32.nxv16i8.nxv16i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv16i16.i64.nxv16i8.nxv16i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_vvw_u8m2(vuint16m4_t vd, vuint8m2_t vs2, vuint8m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv32i16.i32.nxv32i8.nxv32i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv32i16.i64.nxv32i8.nxv32i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_vvw_u8m4(vuint16m8_t vd, vuint8m4_t vs2, vuint8m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u8m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv1i32.i32.nxv1i16.nxv1i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv1i32.i64.nxv1i16.nxv1i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_vvw_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, vuint16mf4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u16mf4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv2i32.i32.nxv2i16.nxv2i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv2i32.i64.nxv2i16.nxv2i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_vvw_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, vuint16mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u16mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv4i32.i32.nxv4i16.nxv4i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv4i32.i64.nxv4i16.nxv4i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_vvw_u16m1(vuint32m2_t vd, vuint16m1_t vs2, vuint16m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u16m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv8i32.i32.nxv8i16.nxv8i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv8i32.i64.nxv8i16.nxv8i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_vvw_u16m2(vuint32m4_t vd, vuint16m2_t vs2, vuint16m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u16m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv16i32.i32.nxv16i16.nxv16i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv16i32.i64.nxv16i16.nxv16i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_vvw_u16m4(vuint32m8_t vd, vuint16m4_t vs2, vuint16m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u16m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv1i64.i32.nxv1i32.nxv1i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv1i64.i64.nxv1i32.nxv1i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_vvw_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, vuint32mf2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u32mf2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv2i64.i32.nxv2i32.nxv2i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv2i64.i64.nxv2i32.nxv2i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_vvw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, vuint32m1_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u32m1(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv4i64.i32.nxv4i32.nxv4i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv4i64.i64.nxv4i32.nxv4i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_vvw_u32m2(vuint64m4_t vd, vuint32m2_t vs2, vuint32m2_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u32m2(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_vvw_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv8i64.i32.nxv8i32.nxv8i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_vvw_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.vvw.nxv8i64.i64.nxv8i32.nxv8i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], [[VS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_vvw_u32m4(vuint64m8_t vd, vuint32m4_t vs2, vuint32m4_t vs1, size_t vl) { + return __riscv_sf_vc_v_vvw_u32m4(p27_26, vd, vs2, vs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv1i16.nxv1i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv1i16.nxv1i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u8mf8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv2i16.nxv2i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv2i16.nxv2i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u8mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv4i16.nxv4i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv4i16.nxv4i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u8mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv8i16.nxv8i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv8i16.nxv8i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u8m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv16i16.nxv16i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv16i16.nxv16i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u8m2(vuint16m4_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u8m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv32i16.nxv32i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv32i16.nxv32i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u8m4(vuint16m8_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u8m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv1i32.nxv1i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv1i32.nxv1i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u16mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv2i32.nxv2i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv2i32.nxv2i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u16mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv4i32.nxv4i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv4i32.nxv4i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u16m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv8i32.nxv8i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv8i32.nxv8i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u16m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv16i32.nxv16i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv16i32.nxv16i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u16m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv1i64.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv1i64.nxv1i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv2i64.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv2i64.nxv2i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv4i64.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv4i64.nxv4i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_xvw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i32.nxv8i64.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_xvw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.xvw.se.i64.nxv8i64.nxv8i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_xvw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { + __riscv_sf_vc_xvw_se_u32m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv1i16.i32.nxv1i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv1i16.i64.nxv1i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_xvw_se_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u8mf8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv2i16.i32.nxv2i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv2i16.i64.nxv2i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_xvw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u8mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv4i16.i32.nxv4i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv4i16.i64.nxv4i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_xvw_se_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u8mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv8i16.i32.nxv8i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv8i16.i64.nxv8i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_xvw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u8m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv16i16.i32.nxv16i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv16i16.i64.nxv16i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_xvw_se_u8m2(vuint16m4_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u8m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv32i16.i32.nxv32i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv32i16.i64.nxv32i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_xvw_se_u8m4(vuint16m8_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u8m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv1i32.i32.nxv1i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv1i32.i64.nxv1i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_xvw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u16mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv2i32.i32.nxv2i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv2i32.i64.nxv2i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_xvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u16mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv4i32.i32.nxv4i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv4i32.i64.nxv4i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_xvw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u16m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv8i32.i32.nxv8i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv8i32.i64.nxv8i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_xvw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u16m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv16i32.i32.nxv16i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv16i32.i64.nxv16i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_xvw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u16m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv1i64.i32.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv1i64.i64.nxv1i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_xvw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv2i64.i32.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv2i64.i64.nxv2i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_xvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv4i64.i32.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv4i64.i64.nxv4i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_xvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv8i64.i32.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.se.nxv8i64.i64.nxv8i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_xvw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_se_u32m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv1i16.i32.nxv1i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv1i16.i64.nxv1i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_xvw_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u8mf8(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv2i16.i32.nxv2i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv2i16.i64.nxv2i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_xvw_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u8mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv4i16.i32.nxv4i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv4i16.i64.nxv4i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_xvw_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u8mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv8i16.i32.nxv8i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv8i16.i64.nxv8i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_xvw_u8m1(vuint16m2_t vd, vuint8m1_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u8m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv16i16.i32.nxv16i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv16i16.i64.nxv16i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_xvw_u8m2(vuint16m4_t vd, vuint8m2_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u8m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv32i16.i32.nxv32i8.i8.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv32i16.i64.nxv32i8.i8.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i8 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_xvw_u8m4(vuint16m8_t vd, vuint8m4_t vs2, uint8_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u8m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv1i32.i32.nxv1i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv1i32.i64.nxv1i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_xvw_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u16mf4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv2i32.i32.nxv2i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv2i32.i64.nxv2i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_xvw_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u16mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv4i32.i32.nxv4i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv4i32.i64.nxv4i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_xvw_u16m1(vuint32m2_t vd, vuint16m1_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u16m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv8i32.i32.nxv8i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv8i32.i64.nxv8i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_xvw_u16m2(vuint32m4_t vd, vuint16m2_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u16m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv16i32.i32.nxv16i16.i16.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv16i32.i64.nxv16i16.i16.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i16 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_xvw_u16m4(vuint32m8_t vd, vuint16m4_t vs2, uint16_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u16m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv1i64.i32.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv1i64.i64.nxv1i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_xvw_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32mf2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv2i64.i32.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv2i64.i64.nxv2i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_xvw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32m1(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv4i64.i32.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv4i64.i64.nxv4i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_xvw_u32m2(vuint64m4_t vd, vuint32m2_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32m2(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_xvw_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv8i64.i32.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_xvw_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.xvw.nxv8i64.i64.nxv8i32.i32.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i32 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_xvw_u32m4(vuint64m8_t vd, vuint32m4_t vs2, uint32_t rs1, size_t vl) { + return __riscv_sf_vc_v_xvw_u32m4(p27_26, vd, vs2, rs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv1i16.nxv1i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv1i16.nxv1i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u8mf8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv2i16.nxv2i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv2i16.nxv2i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u8mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv4i16.nxv4i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv4i16.nxv4i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u8mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv8i16.nxv8i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv8i16.nxv8i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u8m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv16i16.nxv16i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv16i16.nxv16i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u8m2(vuint16m4_t vd, vuint8m2_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u8m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv32i16.nxv32i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv32i16.nxv32i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u8m4(vuint16m8_t vd, vuint8m4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u8m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv1i32.nxv1i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv1i32.nxv1i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u16mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv2i32.nxv2i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv2i32.nxv2i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u16mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv4i32.nxv4i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv4i32.nxv4i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u16m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv8i32.nxv8i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv8i32.nxv8i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u16m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv16i32.nxv16i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv16i32.nxv16i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u16m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv1i64.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv1i64.nxv1i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv2i64.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv2i64.nxv2i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv4i64.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv4i64.nxv4i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_ivw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i32.nxv8i64.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_ivw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.ivw.se.i64.nxv8i64.nxv8i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_ivw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, size_t vl) { + __riscv_sf_vc_ivw_se_u32m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv1i16.i32.nxv1i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv1i16.i64.nxv1i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_ivw_se_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8mf8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv2i16.i32.nxv2i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv2i16.i64.nxv2i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_ivw_se_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv4i16.i32.nxv4i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv4i16.i64.nxv4i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_ivw_se_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv8i16.i32.nxv8i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv8i16.i64.nxv8i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_ivw_se_u8m1(vuint16m2_t vd, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv16i16.i32.nxv16i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv16i16.i64.nxv16i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_ivw_se_u8m2(vuint16m4_t vd, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv32i16.i32.nxv32i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv32i16.i64.nxv32i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_ivw_se_u8m4(vuint16m8_t vd, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u8m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv1i32.i32.nxv1i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv1i32.i64.nxv1i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_ivw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u16mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv2i32.i32.nxv2i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv2i32.i64.nxv2i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_ivw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u16mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv4i32.i32.nxv4i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv4i32.i64.nxv4i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_ivw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u16m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv8i32.i32.nxv8i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv8i32.i64.nxv8i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_ivw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u16m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv16i32.i32.nxv16i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv16i32.i64.nxv16i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_ivw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u16m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv1i64.i32.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv1i64.i64.nxv1i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_ivw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u32mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv2i64.i32.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv2i64.i64.nxv2i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_ivw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u32m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv4i64.i32.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv4i64.i64.nxv4i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_ivw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u32m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv8i64.i32.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.se.nxv8i64.i64.nxv8i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_ivw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_se_u32m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u8mf8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv1i16.i32.nxv1i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u8mf8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv1i16.i64.nxv1i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_sf_vc_v_ivw_u8mf8(vuint16mf4_t vd, vuint8mf8_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8mf8(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u8mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv2i16.i32.nxv2i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u8mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv2i16.i64.nxv2i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_sf_vc_v_ivw_u8mf4(vuint16mf2_t vd, vuint8mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u8mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv4i16.i32.nxv4i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u8mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv4i16.i64.nxv4i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_sf_vc_v_ivw_u8mf2(vuint16m1_t vd, vuint8mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u8m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv8i16.i32.nxv8i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u8m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv8i16.i64.nxv8i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_sf_vc_v_ivw_u8m1(vuint16m2_t vd, vuint8m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u8m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv16i16.i32.nxv16i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u8m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv16i16.i64.nxv16i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_sf_vc_v_ivw_u8m2(vuint16m4_t vd, vuint8m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u8m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv32i16.i32.nxv32i8.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u8m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv32i16.i64.nxv32i8.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_sf_vc_v_ivw_u8m4(vuint16m8_t vd, vuint8m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u8m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv1i32.i32.nxv1i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv1i32.i64.nxv1i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_ivw_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u16mf4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv2i32.i32.nxv2i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv2i32.i64.nxv2i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_ivw_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u16mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv4i32.i32.nxv4i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv4i32.i64.nxv4i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_ivw_u16m1(vuint32m2_t vd, vuint16m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u16m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv8i32.i32.nxv8i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv8i32.i64.nxv8i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_ivw_u16m2(vuint32m4_t vd, vuint16m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u16m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv16i32.i32.nxv16i16.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv16i32.i64.nxv16i16.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_ivw_u16m4(vuint32m8_t vd, vuint16m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u16m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv1i64.i32.nxv1i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv1i64.i64.nxv1i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_ivw_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u32mf2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv2i64.i32.nxv2i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv2i64.i64.nxv2i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_ivw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u32m1(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv4i64.i32.nxv4i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv4i64.i64.nxv4i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_ivw_u32m2(vuint64m4_t vd, vuint32m2_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u32m2(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_ivw_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv8i64.i32.nxv8i32.i32.i32(i32 3, [[VD:%.*]], [[VS2:%.*]], i32 10, i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_ivw_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.ivw.nxv8i64.i64.nxv8i32.i64.i64(i64 3, [[VD:%.*]], [[VS2:%.*]], i64 10, i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_ivw_u32m4(vuint64m8_t vd, vuint32m4_t vs2, size_t vl) { + return __riscv_sf_vc_v_ivw_u32m4(p27_26, vd, vs2, simm5, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv1i32.nxv1i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv1i32.nxv1i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u16mf4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv2i32.nxv2i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv2i32.nxv2i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u16mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv4i32.nxv4i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv4i32.nxv4i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u16m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv8i32.nxv8i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv8i32.nxv8i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u16m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv16i32.nxv16i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv16i32.nxv16i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u16m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv1i64.nxv1i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv1i64.nxv1i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv2i64.nxv2i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv2i64.nxv2i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv4i64.nxv4i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv4i64.nxv4i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_fvw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i32.nxv8i64.nxv8i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret void +// +// CHECK-RV64-LABEL: @test_sf_vc_fvw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.sf.vc.fvw.se.i64.nxv8i64.nxv8i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret void +// +void test_sf_vc_fvw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, float fs1, size_t vl) { + __riscv_sf_vc_fvw_se_u32m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv1i32.i32.nxv1i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv1i32.i64.nxv1i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_fvw_se_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u16mf4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv2i32.i32.nxv2i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv2i32.i64.nxv2i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_fvw_se_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u16mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv4i32.i32.nxv4i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv4i32.i64.nxv4i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_fvw_se_u16m1(vuint32m2_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u16m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv8i32.i32.nxv8i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv8i32.i64.nxv8i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_fvw_se_u16m2(vuint32m4_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u16m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv16i32.i32.nxv16i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv16i32.i64.nxv16i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_fvw_se_u16m4(vuint32m8_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u16m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv1i64.i32.nxv1i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv1i64.i64.nxv1i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_fvw_se_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u32mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv2i64.i32.nxv2i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv2i64.i64.nxv2i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_fvw_se_u32m1(vuint64m2_t vd, vuint32m1_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u32m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv4i64.i32.nxv4i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv4i64.i64.nxv4i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_fvw_se_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u32m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_se_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv8i64.i32.nxv8i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_se_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.se.nxv8i64.i64.nxv8i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_fvw_se_u32m4(vuint64m8_t vd, vuint32m4_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_se_u32m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u16mf4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv1i32.i32.nxv1i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u16mf4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv1i32.i64.nxv1i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32mf2_t test_sf_vc_v_fvw_u16mf4(vuint32mf2_t vd, vuint16mf4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u16mf4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u16mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv2i32.i32.nxv2i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u16mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv2i32.i64.nxv2i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m1_t test_sf_vc_v_fvw_u16mf2(vuint32m1_t vd, vuint16mf2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u16mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u16m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv4i32.i32.nxv4i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv4i32.i64.nxv4i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m2_t test_sf_vc_v_fvw_u16m1(vuint32m2_t vd, vuint16m1_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u16m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u16m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv8i32.i32.nxv8i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv8i32.i64.nxv8i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m4_t test_sf_vc_v_fvw_u16m2(vuint32m4_t vd, vuint16m2_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u16m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u16m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv16i32.i32.nxv16i16.f16.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv16i32.i64.nxv16i16.f16.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], half [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint32m8_t test_sf_vc_v_fvw_u16m4(vuint32m8_t vd, vuint16m4_t vs2, _Float16 fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u16m4(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u32mf2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv1i64.i32.nxv1i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u32mf2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv1i64.i64.nxv1i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m1_t test_sf_vc_v_fvw_u32mf2(vuint64m1_t vd, vuint32mf2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u32mf2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u32m1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv2i64.i32.nxv2i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv2i64.i64.nxv2i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m2_t test_sf_vc_v_fvw_u32m1(vuint64m2_t vd, vuint32m1_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u32m1(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u32m2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv4i64.i32.nxv4i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u32m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv4i64.i64.nxv4i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m4_t test_sf_vc_v_fvw_u32m2(vuint64m4_t vd, vuint32m2_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u32m2(p27, vd, vs2, fs1, vl); +} + +// CHECK-RV32-LABEL: @test_sf_vc_v_fvw_u32m4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv8i64.i32.nxv8i32.f32.i32(i32 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret [[TMP0]] +// +// CHECK-RV64-LABEL: @test_sf_vc_v_fvw_u32m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.sf.vc.v.fvw.nxv8i64.i64.nxv8i32.f32.i64(i64 1, [[VD:%.*]], [[VS2:%.*]], float [[FS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint64m8_t test_sf_vc_v_fvw_u32m4(vuint64m8_t vd, vuint32m4_t vs2, float fs1, size_t vl) { + return __riscv_sf_vc_v_fvw_u32m4(p27, vd, vs2, fs1, vl); +}