diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -59,6 +59,8 @@
 // CHECK-NOT: __riscv_zvksed {{.*$}}
 // CHECK-NOT: __riscv_zvksh {{.*$}}
 // CHECK-NOT: __riscv_zicond {{.*$}}
+// CHECK-NOT: __riscv_smaia
+// CHECK-NOT: __riscv_ssaia
 
 // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
 // RUN: -o - | FileCheck %s
@@ -604,3 +606,15 @@
 // RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
 // CHECK-ZICOND-EXT: __riscv_zicond  1000000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32ismaia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMAIA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64ismaia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SMAIA-EXT %s
+// CHECK-SMAIA-EXT: __riscv_smaia  1000000{{$}}
+
+// RUN: %clang -target riscv32 -march=rv32issaia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
+// RUN: %clang -target riscv64 -march=rv64issaia -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-SSAIA-EXT %s
+// CHECK-SSAIA-EXT: __riscv_ssaia  1000000{{$}}
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -88,6 +88,8 @@
      ``F``            Supported
      ``H``            Assembly Support
      ``M``            Supported
+     ``Smaia``        Supported
+     ``Ssaia``        Supported
      ``Svinval``      Assembly Support
      ``Svnapot``      Assembly Support
      ``Svpbmt``       Supported
@@ -168,6 +170,9 @@
 ``zicsr``, ``zifencei``
   Between versions 2.0 and 2.1 of the base I specification, a backwards incompatible change was made to remove selected instructions and CSRs from the base ISA.  These instructions were grouped into a set of new extensions, but were no longer required by the base ISA.  This change is described in "Preface to Document Version 20190608-Base-Ratified" from the specification document.  LLVM currently implements version 2.0 of the base specification.  Thus, instructions from these extensions are accepted as part of the base ISA.  LLVM also allows the explicit specification of the extensions in an march string.
 
+``smaia``, ``ssaia``
+  LLVM currently support version 1.0-RC3: https://github.com/riscv/riscv-aia/releases/download/1.0-RC3/riscv-interrupts-1.0-RC3.pdf
+
 Experimental Extensions
 =======================
 
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -116,6 +116,9 @@
     {"svpbmt", RISCVExtensionVersion{1, 0}},
     {"svinval", RISCVExtensionVersion{1, 0}},
 
+    {"smaia", RISCVExtensionVersion{1, 0}},
+    {"ssaia", RISCVExtensionVersion{1, 0}},
+
     // vendor-defined ('X') extensions
     {"xsfvcp", RISCVExtensionVersion{1, 0}},
     {"xtheadba", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -545,6 +545,19 @@
                                 AssemblerPredicate<(all_of FeatureStdExtZicond),
                                 "'Zicond' (Integer Conditional Operations)">;
 
+def FeatureStdExtSmaia
+    : SubtargetFeature<"smaia", "HasStdExtSmaia", "true",
+                       "'Smaia' (Smaia encompasses all added CSRs and all "
+                       "modifications to interrupt response behavior that the "
+                       "AIA specifies for a hart, over all privilege levels.)",
+                       []>;
+
+def FeatureStdExtSsaia
+    : SubtargetFeature<"ssaia", "HasStdExtSsaia", "true",
+                       "'Ssaia' (Ssaia is essentially the same as Smaia except "
+                       "excluding the machine-level CSRs and behavior not "
+                       "directly visible to supervisor level.)", []>;
+
 //===----------------------------------------------------------------------===//
 // Vendor extensions
 //===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -378,3 +378,51 @@
 //===-----------------------------------------------
 
 def SEED : SysReg<"seed", 0x015>;
+
+//===-----------------------------------------------
+// Advanced Interrupt Architecture
+//===-----------------------------------------------
+
+// Machine-level CSRs
+def : SysReg<"miselect", 0x350>;
+def : SysReg<"mireg", 0x351>;
+def : SysReg<"mtopei", 0x35C>;
+def : SysReg<"mtopi", 0xFB0>;
+def : SysReg<"mvien", 0x308>;
+def : SysReg<"mvip", 0x309>;
+let isRV32Only = 1 in {
+def : SysReg<"midelegh", 0x313>;
+def : SysReg<"mieh", 0x314>;
+def : SysReg<"mvienh", 0x318>;
+def : SysReg<"mviph", 0x319>;
+def : SysReg<"miph", 0x354>;
+} // isRV32Only
+
+// Supervisor-level CSRs
+def : SysReg<"siselect", 0x150>;
+def : SysReg<"sireg", 0x151>;
+def : SysReg<"stopei", 0x15C>;
+def : SysReg<"stopi", 0xDB0>;
+let isRV32Only = 1 in {
+def : SysReg<"sieh", 0x114>;
+def : SysReg<"siph", 0x154>;
+} // isRV32Only
+
+// Hypervisor and VS CSRs
+def : SysReg<"hvien", 0x608>;
+def : SysReg<"hvictl", 0x609>;
+def : SysReg<"hviprio1", 0x646>;
+def : SysReg<"hviprio2", 0x647>;
+def : SysReg<"vsiselect", 0x250>;
+def : SysReg<"vsireg", 0x251>;
+def : SysReg<"vstopei", 0x25C>;
+def : SysReg<"vstopi", 0xEB0>;
+let isRV32Only = 1 in {
+def : SysReg<"hidelegh", 0x613>;
+def : SysReg<"hvienh", 0x618>;
+def : SysReg<"hviph", 0x655>;
+def : SysReg<"hviprio1h", 0x656>;
+def : SysReg<"hviprio2h", 0x657>;
+def : SysReg<"vsieh", 0x214>;
+def : SysReg<"vsiph", 0x254>;
+} // isRV32Only
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -65,6 +65,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
+; RUN: llc -mtriple=riscv32 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
+; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -137,6 +139,8 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
+; RUN: llc -mtriple=riscv64 -mattr=+smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
+; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
 
 ; CHECK: .attribute 4, 16
 
@@ -204,6 +208,8 @@
 ; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
 ; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
 ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
+; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
+; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
 
 ; RV64M: .attribute 5, "rv64i2p1_m2p0"
 ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -275,6 +281,8 @@
 ; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
 ; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
 ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0"
+; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0"
+; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -239,3 +239,9 @@
 
 .attribute arch, "rv32izicond1p0"
 # CHECK: attribute      5, "rv32i2p1_zicond1p0"
+
+.attribute arch, "rv32i_smaia"
+# CHECK: attribute      5, "rv32i2p1_smaia1p0"
+
+.attribute arch, "rv32i_ssaia"
+# CHECK: attribute      5, "rv32i2p1_ssaia1p0"
diff --git a/llvm/test/MC/RISCV/hypervisor-csr-names.s b/llvm/test/MC/RISCV/hypervisor-csr-names.s
--- a/llvm/test/MC/RISCV/hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/hypervisor-csr-names.s
@@ -447,3 +447,119 @@
 csrrs t1, hstateen3, zero
 # uimm12
 csrrs t2, 0x60F, zero
+
+#########################################
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#########################################
+
+# hvien
+# name
+# CHECK-INST: csrrs t1, hvien, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x60]
+# CHECK-INST-ALIAS: csrr t1, hvien
+# uimm12
+# CHECK-INST: csrrs t2, hvien, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x60]
+# CHECK-INST-ALIAS: csrr t2, hvien
+# name
+csrrs t1, hvien, zero
+# uimm12
+csrrs t2, 0x608, zero
+
+# hvictl
+# name
+# CHECK-INST: csrrs t1, hvictl, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x60]
+# CHECK-INST-ALIAS: csrr t1, hvictl
+# uimm12
+# CHECK-INST: csrrs t2, hvictl, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x60]
+# CHECK-INST-ALIAS: csrr t2, hvictl
+# name
+csrrs t1, hvictl, zero
+# uimm12
+csrrs t2, 0x609, zero
+
+# hviprio1
+# name
+# CHECK-INST: csrrs t1, hviprio1, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x64]
+# CHECK-INST-ALIAS: csrr t1, hviprio1
+# uimm12
+# CHECK-INST: csrrs t2, hviprio1, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x64]
+# CHECK-INST-ALIAS: csrr t2, hviprio1
+# name
+csrrs t1, hviprio1, zero
+# uimm12
+csrrs t2, 0x646, zero
+
+# hviprio2
+# name
+# CHECK-INST: csrrs t1, hviprio2, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x64]
+# CHECK-INST-ALIAS: csrr t1, hviprio2
+# uimm12
+# CHECK-INST: csrrs t2, hviprio2, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x64]
+# CHECK-INST-ALIAS: csrr t2, hviprio2
+# name
+csrrs t1, hviprio2, zero
+# uimm12
+csrrs t2, 0x647, zero
+
+# vsiselect
+# name
+# CHECK-INST: csrrs t1, vsiselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x25]
+# CHECK-INST-ALIAS: csrr t1, vsiselect
+# uimm12
+# CHECK-INST: csrrs t2, vsiselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x25]
+# CHECK-INST-ALIAS: csrr t2, vsiselect
+# name
+csrrs t1, vsiselect, zero
+# uimm12
+csrrs t2, 0x250, zero
+
+# vsireg
+# name
+# CHECK-INST: csrrs t1, vsireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x25]
+# CHECK-INST-ALIAS: csrr t1, vsireg
+# uimm12
+# CHECK-INST: csrrs t2, vsireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x25]
+# CHECK-INST-ALIAS: csrr t2, vsireg
+# name
+csrrs t1, vsireg, zero
+# uimm12
+csrrs t2, 0x251, zero
+
+# vstopei
+# name
+# CHECK-INST: csrrs t1, vstopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x25]
+# CHECK-INST-ALIAS: csrr t1, vstopei
+# uimm12
+# CHECK-INST: csrrs t2, vstopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x25]
+# CHECK-INST-ALIAS: csrr t2, vstopei
+# name
+csrrs t1, vstopei, zero
+# uimm12
+csrrs t2, 0x25C, zero
+
+# vstopi
+# name
+# CHECK-INST: csrrs t1, vstopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xeb]
+# CHECK-INST-ALIAS: csrr t1, vstopi
+# uimm12
+# CHECK-INST: csrrs t2, vstopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xeb]
+# CHECK-INST-ALIAS: csrr t2, vstopi
+# name
+csrrs t1, vstopi, zero
+# uimm12
+csrrs t2, 0xEB0, zero
diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s
--- a/llvm/test/MC/RISCV/machine-csr-names.s
+++ b/llvm/test/MC/RISCV/machine-csr-names.s
@@ -2410,3 +2410,91 @@
 csrrs t1, mstateen3, zero
 # uimm12
 csrrs t2, 0x30F, zero
+
+#########################################
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#########################################
+
+# miselect
+# name
+# CHECK-INST: csrrs t1, miselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x35]
+# CHECK-INST-ALIAS: csrr t1, miselect
+# uimm12
+# CHECK-INST: csrrs t2, miselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x35]
+# CHECK-INST-ALIAS: csrr t2, miselect
+# name
+csrrs t1, miselect, zero
+# uimm12
+csrrs t2, 0x350, zero
+
+# mireg
+# name
+# CHECK-INST: csrrs t1, mireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x35]
+# CHECK-INST-ALIAS: csrr t1, mireg
+# uimm12
+# CHECK-INST: csrrs t2, mireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x35]
+# CHECK-INST-ALIAS: csrr t2, mireg
+# name
+csrrs t1, mireg, zero
+# uimm12
+csrrs t2, 0x351, zero
+
+# mtopei
+# name
+# CHECK-INST: csrrs t1, mtopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x35]
+# CHECK-INST-ALIAS: csrr t1, mtopei
+# uimm12
+# CHECK-INST: csrrs t2, mtopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x35]
+# CHECK-INST-ALIAS: csrr t2, mtopei
+# name
+csrrs t1, mtopei, zero
+# uimm12
+csrrs t2, 0x35C, zero
+
+# mtopi
+# name
+# CHECK-INST: csrrs t1, mtopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xfb]
+# CHECK-INST-ALIAS: csrr t1, mtopi
+# uimm12
+# CHECK-INST: csrrs t2, mtopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xfb]
+# CHECK-INST-ALIAS: csrr t2, mtopi
+# name
+csrrs t1, mtopi, zero
+# uimm12
+csrrs t2, 0xFB0, zero
+
+# mvien
+# name
+# CHECK-INST: csrrs t1, mvien, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x30]
+# CHECK-INST-ALIAS: csrr t1, mvien
+# uimm12
+# CHECK-INST: csrrs t2, mvien, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x30]
+# CHECK-INST-ALIAS: csrr t2, mvien
+# name
+csrrs t1, mvien, zero
+# uimm12
+csrrs t2, 0x308, zero
+
+# mvip
+# name
+# CHECK-INST: csrrs t1, mvip, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x30]
+# CHECK-INST-ALIAS: csrr t1, mvip
+# uimm12
+# CHECK-INST: csrrs t2, mvip, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x30]
+# CHECK-INST-ALIAS: csrr t2, mvip
+# name
+csrrs t1, mvip, zero
+# uimm12
+csrrs t2, 0x309, zero
diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -117,3 +117,105 @@
 csrrs t1, hstateen3h, zero
 # uimm12
 csrrs t2, 0x61F, zero
+
+#########################################
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#########################################
+
+# hidelegh
+# name
+# CHECK-INST: csrrs t1, hidelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x61]
+# CHECK-INST-ALIAS: csrr t1, hidelegh
+# uimm12
+# CHECK-INST: csrrs t2, hidelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x61]
+# CHECK-INST-ALIAS: csrr t2, hidelegh
+# name
+csrrs t1, hidelegh, zero
+# uimm12
+csrrs t2, 0x613, zero
+
+# hvienh
+# name
+# CHECK-INST: csrrs t1, hvienh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x61]
+# CHECK-INST-ALIAS: csrr t1, hvienh
+# uimm12
+# CHECK-INST: csrrs t2, hvienh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x61]
+# CHECK-INST-ALIAS: csrr t2, hvienh
+# name
+csrrs t1, hvienh, zero
+# uimm12
+csrrs t2, 0x618, zero
+
+# hviph
+# name
+# CHECK-INST: csrrs t1, hviph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x50,0x65]
+# CHECK-INST-ALIAS: csrr t1, hviph
+# uimm12
+# CHECK-INST: csrrs t2, hviph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x65]
+# CHECK-INST-ALIAS: csrr t2, hviph
+# name
+csrrs t1, hviph, zero
+# uimm12
+csrrs t2, 0x655, zero
+
+# hviprio1h
+# name
+# CHECK-INST: csrrs t1, hviprio1h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x60,0x65]
+# CHECK-INST-ALIAS: csrr t1, hviprio1h
+# uimm12
+# CHECK-INST: csrrs t2, hviprio1h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x65]
+# CHECK-INST-ALIAS: csrr t2, hviprio1h
+# name
+csrrs t1, hviprio1h, zero
+# uimm12
+csrrs t2, 0x656, zero
+
+# hviprio2h
+# name
+# CHECK-INST: csrrs t1, hviprio2h, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x70,0x65]
+# CHECK-INST-ALIAS: csrr t1, hviprio2h
+# uimm12
+# CHECK-INST: csrrs t2, hviprio2h, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x65]
+# CHECK-INST-ALIAS: csrr t2, hviprio2h
+# name
+csrrs t1, hviprio2h, zero
+# uimm12
+csrrs t2, 0x657, zero
+
+# vsieh
+# name
+# CHECK-INST: csrrs t1, vsieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x21]
+# CHECK-INST-ALIAS: csrr t1, vsieh
+# uimm12
+# CHECK-INST: csrrs t2, vsieh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x21]
+# CHECK-INST-ALIAS: csrr t2, vsieh
+# name
+csrrs t1, vsieh, zero
+# uimm12
+csrrs t2, 0x214, zero
+
+# vsiph
+# name
+# CHECK-INST: csrrs t1, vsiph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x25]
+# CHECK-INST-ALIAS: csrr t1, vsiph
+# uimm12
+# CHECK-INST: csrrs t2, vsiph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x25]
+# CHECK-INST-ALIAS: csrr t2, vsiph
+# name
+csrrs t1, vsiph, zero
+# uimm12
+csrrs t2, 0x254, zero
diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -1075,3 +1075,77 @@
 csrrs t1, mstateen3h, zero
 # uimm12
 csrrs t2, 0x31F, zero
+
+#########################################
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#########################################
+
+# midelegh
+# name
+# CHECK-INST: csrrs t1, midelegh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x30,0x31]
+# CHECK-INST-ALIAS: csrr t1, midelegh
+# uimm12
+# CHECK-INST: csrrs t2, midelegh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x31]
+# CHECK-INST-ALIAS: csrr t2, midelegh
+# name
+csrrs t1, midelegh, zero
+# uimm12
+csrrs t2, 0x313, zero
+
+# mieh
+# name
+# CHECK-INST: csrrs t1, mieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x31]
+# CHECK-INST-ALIAS: csrr t1, mieh
+# uimm12
+# CHECK-INST: csrrs t2, mieh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x31]
+# CHECK-INST-ALIAS: csrr t2, mieh
+# name
+csrrs t1, mieh, zero
+# uimm12
+csrrs t2, 0x314, zero
+
+# mvienh
+# name
+# CHECK-INST: csrrs t1, mvienh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x80,0x31]
+# CHECK-INST-ALIAS: csrr t1, mvienh
+# uimm12
+# CHECK-INST: csrrs t2, mvienh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x31]
+# CHECK-INST-ALIAS: csrr t2, mvienh
+# name
+csrrs t1, mvienh, zero
+# uimm12
+csrrs t2, 0x318, zero
+
+# mviph
+# name
+# CHECK-INST: csrrs t1, mviph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x90,0x31]
+# CHECK-INST-ALIAS: csrr t1, mviph
+# uimm12
+# CHECK-INST: csrrs t2, mviph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x31]
+# CHECK-INST-ALIAS: csrr t2, mviph
+# name
+csrrs t1, mviph, zero
+# uimm12
+csrrs t2, 0x319, zero
+
+# miph
+# name
+# CHECK-INST: csrrs t1, miph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x35]
+# CHECK-INST-ALIAS: csrr t1, miph
+# uimm12
+# CHECK-INST: csrrs t2, miph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x35]
+# CHECK-INST-ALIAS: csrr t2, miph
+# name
+csrrs t1, miph, zero
+# uimm12
+csrrs t2, 0x354, zero
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -131,3 +131,18 @@
 
 csrrs t1, stimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
 csrrs t1, vstimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, midelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mieh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mvienh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, mviph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, miph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, sieh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, siph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hidelegh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hvienh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hviph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hviprio1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, hviprio2h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, vsieh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, vsiph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
diff --git a/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
@@ -21,3 +21,35 @@
 csrrs t1, stimecmph, zero
 # uimm12
 csrrs t2, 0x15D, zero
+
+#########################################
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#########################################
+
+# sieh
+# name
+# CHECK-INST: csrrs t1, sieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x11]
+# CHECK-INST-ALIAS: csrr t1, sieh
+# uimm12
+# CHECK-INST: csrrs t2, sieh, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x11]
+# CHECK-INST-ALIAS: csrr t2, sieh
+# name
+csrrs t1, sieh, zero
+# uimm12
+csrrs t2, 0x114, zero
+
+# siph
+# name
+# CHECK-INST: csrrs t1, siph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x15]
+# CHECK-INST-ALIAS: csrr t1, siph
+# uimm12
+# CHECK-INST: csrrs t2, siph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x15]
+# CHECK-INST-ALIAS: csrr t2, siph
+# name
+csrrs t1, siph, zero
+# uimm12
+csrrs t2, 0x154, zero
diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s
--- a/llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -207,8 +207,8 @@
 # CHECK-S-OBJ: rdtime s9
 rdtime x25
 
-# CHECK-S-OBJ-NOALIAS: csrrs  s0, 336, zero
-# CHECK-S-OBJ: csrr s0, 336
+# CHECK-S-OBJ-NOALIAS: csrrs s0, siselect, zero
+# CHECK-S-OBJ: csrr s0, siselect
 csrr x8, 0x150
 # CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1
 # CHECK-S-OBJ: csrw sscratch, s1
@@ -220,8 +220,8 @@
 # CHECK-S-OBJ: csrc 4095, s7
 csrc 0xfff, x23
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 15
-# CHECK-S-OBJ: csrwi 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 15
+# CHECK-S-OBJ: csrwi siselect, 15
 csrwi 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi zero, 4095, 16
 # CHECK-S-OBJ: csrsi 4095, 16
@@ -230,18 +230,18 @@
 # CHECK-S-OBJ: csrci sscratch, 17
 csrci 0x140, 0x11
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 7
-# CHECK-S-OBJ: csrwi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 7
+# CHECK-S-OBJ: csrwi siselect, 7
 csrw 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrsi zero, 336, 7
-# CHECK-S-OBJ: csrsi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrsi zero, siselect, 7
+# CHECK-S-OBJ: csrsi siselect, 7
 csrs 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrci zero, 336, 7
-# CHECK-S-OBJ: csrci 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrci zero, siselect, 7
+# CHECK-S-OBJ: csrci siselect, 7
 csrc 0x150, 7
 
-# CHECK-S-OBJ-NOALIAS: csrrwi t0, 336, 15
-# CHECK-S-OBJ: csrrwi t0, 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi t0, siselect, 15
+# CHECK-S-OBJ: csrrwi t0, siselect, 15
 csrrw t0, 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi t0, 4095, 16
 # CHECK-S-OBJ: csrrsi t0, 4095, 16
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -319,3 +319,63 @@
 csrrs t1, sstateen3, zero
 # uimm12
 csrrs t2, 0x10F, zero
+
+#########################################
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#########################################
+
+# siselect
+# name
+# CHECK-INST: csrrs t1, siselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t1, siselect
+# uimm12
+# CHECK-INST: csrrs t2, siselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t2, siselect
+# name
+csrrs t1, siselect, zero
+# uimm12
+csrrs t2, 0x150, zero
+
+# sireg
+# name
+# CHECK-INST: csrrs t1, sireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t1, sireg
+# uimm12
+# CHECK-INST: csrrs t2, sireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t2, sireg
+# name
+csrrs t1, sireg, zero
+# uimm12
+csrrs t2, 0x151, zero
+
+# stopei
+# name
+# CHECK-INST: csrrs t1, stopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t1, stopei
+# uimm12
+# CHECK-INST: csrrs t2, stopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t2, stopei
+# name
+csrrs t1, stopei, zero
+# uimm12
+csrrs t2, 0x15C, zero
+
+# stopi
+# name
+# CHECK-INST: csrrs t1, stopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t1, stopi
+# uimm12
+# CHECK-INST: csrrs t2, stopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t2, stopi
+# name
+csrrs t1, stopi, zero
+# uimm12
+csrrs t2, 0xDB0, zero