Index: lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1696,6 +1696,10 @@
          "i32 or i64 mask type expected!");
   unsigned BitWidth = VT.getSizeInBits() - NumberOfIgnoredHighBits;
 
+  // trivially true.
+  if (BitWidth == 0)
+    return true;
+
   APInt SignificantDstMask = APInt(BitWidth, DstMask);
   APInt SignificantBitsToBeInserted = BitsToBeInserted.zextOrTrunc(BitWidth);
 
Index: test/CodeGen/AArch64/bitfield-pr25571.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AArch64/bitfield-pr25571.ll
@@ -0,0 +1,23 @@
+; ModuleID = 'bugpoint-reduced-simplified.bc'
+;RUN: llc -verify-machineinstrs < %s | FileCheck %s
+target datalayout = "e-m:e-i64:64-i128:128-n8:16:32:64-S128"
+target triple = "aarch64--linux-gnu"
+
+define i32 @test(i8 %a, i32 %b) {
+; CHECK-LABEL: test
+; CHECK: bfi
+; CHECK: bfi
+; CHECK: bfi
+; CHECK: bfi
+  %conv = zext i8 %a to i32     ;   0 0 0 0 A
+  %shl = shl i32 %b, 8          ;   B2 B1 B0 0
+  %or = or i32 %conv, %shl      ;   B2 B1 B0 A
+  %shl.1 = shl i32 %or, 8       ;   B1 B0 A 0
+  %or.1 = or i32 %conv, %shl.1  ;   B1 B0 A A
+  %shl.2 = shl i32 %or.1, 8     ;   B0 A A 0
+  %or.2 = or i32 %conv, %shl.2  ;   B0 A A A
+  %shl.3 = shl i32 %or.2, 8     ;   A A A 0
+  %or.3 = or i32 %conv, %shl.3  ;   A A A A
+  %shl.4 = shl i32 %or.3, 8     ;   A A A 0
+  ret i32 %shl.4
+}