diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2752,6 +2752,18 @@
   let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicyScheme = NonePolicy,
       ManualCodegen = [{
       {
+        if (isa<StructType>(ResultType)) { // codegen for tuple type
+          llvm::Value *VTupleOperand = Ops[0];
+          llvm::Value *IndexOperand = Ops[1];
+          llvm::Value *VOperand = Ops[2];
+          assert(isa<ConstantInt>(IndexOperand));
+
+          unsigned Index = cast<ConstantInt>(IndexOperand)->getZExtValue();
+          unsigned MaxIndex = cast<StructType>(VTupleOperand->getType())->getNumElements();
+          Index = std::min(Index, MaxIndex);
+
+          return Builder.CreateInsertValue(VTupleOperand, VOperand, {Index});
+        }
         ID = Intrinsic::vector_insert;
         IntrinsicTypes = {ResultType, Ops[2]->getType()};
         auto *ResVecTy = cast<ScalableVectorType>(ResultType);
@@ -2772,5 +2784,9 @@
       def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
     }
+    foreach nf = [2] in {
+      defvar T = "(Tuple:" # nf # ")";
+      def : RVVBuiltin<T # "vv", T # "v" # T # "vKzv", "i", "v">;
+    }
   }
 }
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset_tuple.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset_tuple.c
new file mode 100644
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset_tuple.c
@@ -0,0 +1,20 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vget_v_i32m1x2_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[DEST_COERCE0:%.*]], <vscale x 2 x i32> [[DEST_COERCE1:%.*]], i64 noundef [[INDEX:%.*]], <vscale x 2 x i32> [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:    [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } undef, <vscale x 2 x i32> [[DEST_COERCE0]], 0
+// CHECK-RV64-NEXT:    [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[DEST_COERCE1]], 1
+// CHECK-RV64-NEXT:    [[TMP2:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], <vscale x 2 x i32> [[VAL]], 0
+// CHECK-RV64-NEXT:    ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP2]]
+//
+vint32m1x2_t test_vget_v_i32m1x2_i32m1(vint32m1x2_t dest, size_t index, vint32m1_t val) {
+  return __riscv_vset_v_i32m1x2_i32m1(dest, 0, val);
+}