diff --git a/lld/test/ELF/arm-bl-v4t.s b/lld/test/ELF/arm-bl-v4t.s --- a/lld/test/ELF/arm-bl-v4t.s +++ b/lld/test/ELF/arm-bl-v4t.s @@ -154,11 +154,11 @@ // FAR-EB-PIE-NEXT: 100002c: 04 ff ff d9 .word 0x04ffffd9 // NEAR-LABEL: <_start>: -// NEAR-NEXT: 1000000: bl 0x100000c @ imm = #4 +// NEAR-NEXT: 1000000: bl 0x1000010 @ imm = #8 // NEAR-NEXT: bx lr // NEAR-EMPTY: // NEAR-LABEL: : -// NEAR-NEXT: 1000008: bl 0x1000012 @ imm = #6 +// NEAR-NEXT: 1000008: bl 0x1000014 @ imm = #8 // NEAR-NEXT: bx lr .section .high, "ax", %progbits @@ -187,10 +187,10 @@ // FAR-PIE-NEXT: 6000004: bx lr // NEAR-LABEL: : -// NEAR-LABEL: 100000e: bx lr +// NEAR-LABEL: 1000010: bx lr // NEAR-EMPTY: // NEAR-NEXT: : -// NEAR-NEXT: 1000012: bx lr +// NEAR-NEXT: 1000014: bx lr #--- far.lds diff --git a/lld/test/ELF/arm-bl-v6-inrange.s b/lld/test/ELF/arm-bl-v6-inrange.s --- a/lld/test/ELF/arm-bl-v6-inrange.s +++ b/lld/test/ELF/arm-bl-v6-inrange.s @@ -38,8 +38,8 @@ // CHECK-NEXT: 500004: f3ff effe blx 0x900004 // CHECK-NEXT: 500008: 4770 bx lr - .arm .section .callee_high, "ax", %progbits + .arm .globl armfunc .type armfunc, %function armfunc: diff --git a/lld/test/ELF/arm-fix-cortex-a8-nopatch.s b/lld/test/ELF/arm-fix-cortex-a8-nopatch.s --- a/lld/test/ELF/arm-fix-cortex-a8-nopatch.s +++ b/lld/test/ELF/arm-fix-cortex-a8-nopatch.s @@ -75,7 +75,7 @@ // CALLSITE4: 00025002 : // CALLSITE4-NEXT: 25002: nop.w - .space 4084 + .space 4082 .type target5, %function target5: @@ -83,14 +83,15 @@ /// a 32-bit thumb instruction, but in ARM state (illegal instruction), we /// should not decode and match it as Thumb, expect no patch. .arm - .inst 0x800f3af /// nop.w encoding in Thumb + .short 0xbf00 // nop encoding in Thumb for alignment + .inst 0xf3af8000 /// nop.w encoding in Thumb .thumb .thumb_func source5: beq.w target5 // CALLSITE5: 00025ffe : -// CALLSITE5-NEXT: 25ffe: beq.w 0x25ffa +// CALLSITE5-NEXT: 25ffe: beq.w 0x25ff8 /// Edge case where two word sequence starts at offset 0xffc, check that /// we don't match. In this case the branch will be completely in the 2nd diff --git a/lld/test/ELF/arm-fix-cortex-a8-recognize.s b/lld/test/ELF/arm-fix-cortex-a8-recognize.s --- a/lld/test/ELF/arm-fix-cortex-a8-recognize.s +++ b/lld/test/ELF/arm-fix-cortex-a8-recognize.s @@ -26,7 +26,7 @@ // CHECK-RELOCATABLE-LLD-NOT: ld.lld: detected cortex-a8-657419 erratum sequence /// Basic tests for the -fix-cortex-a8 erratum fix. The full details of the -/// erratum and the patch are in ARMA8ErrataFix.cpp . The test creates an +/// erratum and the patch are in ARMErrataFix.cpp . The test creates an /// instance of the erratum every 4KiB (32-bit non-branch, followed by 32-bit /// branch instruction, where the branch instruction spans two 4 KiB regions, /// and the branch destination is in the first 4KiB region. @@ -163,7 +163,7 @@ // CALLSITE7-NEXT: 27ffe: bne.w 0x2901c <__CortexA8657417_27FFE> .section .text.6, "ax", %progbits - .space 4082 + .space 4080 .arm .global target8 .type target8, %function diff --git a/lld/test/ELF/arm-thunk-multipass.s b/lld/test/ELF/arm-thunk-multipass.s --- a/lld/test/ELF/arm-thunk-multipass.s +++ b/lld/test/ELF/arm-thunk-multipass.s @@ -4,7 +4,7 @@ // The output file is large, most of it zeroes. We dissassemble only the // parts we need to speed up the test and avoid a large output file // RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x100002 --stop-address=0x10000a | FileCheck --check-prefix=CHECK1 %s -// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1000008 --stop-address=0x1000026 | FileCheck --check-prefix=CHECK2 %s +// RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1000004 --stop-address=0x1000026 | FileCheck --check-prefix=CHECK2 %s // RUN: llvm-objdump --no-print-imm-hex -d %t2 --start-address=0x1100014 --stop-address=0x1100022 | FileCheck --check-prefix=CHECK3 %s // In this test case a branch that is in range and does not need its range // extended can be pushed out of range by another Thunk, necessitating another @@ -59,8 +59,9 @@ .type arm_target, %function arm_target: bx lr +// CHECK2: 01000004 : // CHECK2: <__Thumbv7ABSLongThunk_arm_target>: -// CHECK2-NEXT: 1000008: f240 0c02 movw r12, #2 +// CHECK2-NEXT: 1000008: f240 0c04 movw r12, #4 // CHECK2-NEXT: 100000c: f2c0 1c00 movt r12, #256 // CHECK2-NEXT: 1000010: 4760 bx r12 // CHECK2: <__Thumbv7ABSLongThunk_target>: diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -107,6 +107,9 @@ have integer MVE instructions (and therefore have FP registers) but no scalar or vector floating point computation. +- The ``.arm`` directive now aligns code to the next 4-byte boundary, and + the ``.thumb`` directive aligns code to the next 2-byte boundary. + Changes to the AVR Backend -------------------------- diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -11418,6 +11418,7 @@ SwitchMode(); getParser().getStreamer().emitAssemblerFlag(MCAF_Code16); + getParser().getStreamer().emitCodeAlignment(Align(2), &getSTI(), 0); return false; } @@ -11430,6 +11431,7 @@ if (isThumb()) SwitchMode(); getParser().getStreamer().emitAssemblerFlag(MCAF_Code32); + getParser().getStreamer().emitCodeAlignment(Align(4), &getSTI(), 0); return false; } diff --git a/llvm/test/MC/ARM/directive-arch-mode-switch.s b/llvm/test/MC/ARM/directive-arch-mode-switch.s --- a/llvm/test/MC/ARM/directive-arch-mode-switch.s +++ b/llvm/test/MC/ARM/directive-arch-mode-switch.s @@ -35,6 +35,7 @@ @ Switch to ARM mode .arm @ CHECK: .code 32 +@ CHECK: .p2align 2 @ In ARM mode, switch to a CPU which has ARM and Thumb, no warning or .code directive (stay in ARM mode) .cpu cortex-a8 diff --git a/llvm/test/MC/ARM/directive-arm-thumb-alignment.s b/llvm/test/MC/ARM/directive-arm-thumb-alignment.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/ARM/directive-arm-thumb-alignment.s @@ -0,0 +1,63 @@ +@ RUN: llvm-mc -triple armv7-elf -filetype obj -o - %s | llvm-readelf -S -s - | FileCheck %s + +@ CHECK: [Nr] Name Type Address Off Size ES Flg Lk Inf Al +@ CHECK-NEXT: [ 0] NULL 00000000 000000 000000 00 0 0 0 +@ CHECK-NEXT: [ 1] .strtab STRTAB 00000000 {{.*}} {{.*}} 00 0 0 1 +@ CHECK-NEXT: [ 2] .text PROGBITS 00000000 {{.*}} 00000d 00 AX 0 0 4 +@ CHECK-NEXT: [ 3] .arm_aligned PROGBITS 00000000 {{.*}} 000005 00 AX 0 0 4 +@ CHECK-NEXT: [ 4] .thumb_aligned PROGBITS 00000000 {{.*}} 000002 00 AX 0 0 2 + +@ CHECK: Num: Value Size Type Bind Vis Ndx Name +@ CHECK-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +@ CHECK-NEXT: 1: 00000001 0 FUNC LOCAL DEFAULT 2 aligned_thumb +@ CHECK-NEXT: 2: 00000000 0 NOTYPE LOCAL DEFAULT 2 $t.0 +@ CHECK-NEXT: 3: 00000004 0 FUNC LOCAL DEFAULT 2 thumb_to_arm +@ CHECK-NEXT: 4: 00000004 0 NOTYPE LOCAL DEFAULT 2 $a.1 +@ CHECK-NEXT: 5: 00000008 0 NOTYPE LOCAL DEFAULT 2 $d.2 +@ CHECK-NEXT: 6: 0000000b 0 FUNC LOCAL DEFAULT 2 unaligned_arm_to_thumb +@ CHECK-NEXT: 7: 0000000a 0 NOTYPE LOCAL DEFAULT 2 $t.3 + +.thumb + +.type aligned_thumb,%function +aligned_thumb: + nop + +@ Above function has size 2 (at offset 0) +@ Expect alignment of +2 (to offset 4) +.arm + +.type thumb_to_arm,%function +thumb_to_arm: + nop + +.byte 0 + +@ Above function has size 5 (at offset 4) +@ Expect alignment of +1 (to offset 10) +.thumb +.type unaligned_arm_to_thumb,%function +unaligned_arm_to_thumb: + nop + +.byte 0 + +@ Above section has size 13 (at offset 34) +@ Expect alignment of +3 (to offset 44) +.section .arm_aligned, "ax" +.arm + +.type arm_aligned_section,%function +arm_aligned_section: + nop + +.byte 0 + +@ Above section has size 5 (at offset 44) +@ Expect alignment of +1 (to offset 4a) +.section .thumb_aligned, "ax" +.thumb + +.type thumb_aligned_section,%function +thumb_aligned_section: + nop diff --git a/llvm/test/MC/ARM/misaligned-blx.s b/llvm/test/MC/ARM/misaligned-blx.s --- a/llvm/test/MC/ARM/misaligned-blx.s +++ b/llvm/test/MC/ARM/misaligned-blx.s @@ -8,6 +8,7 @@ @ A misaligned ARM destination. .arm + .byte 0x0 .globl _misaligned _misaligned: bx lr diff --git a/llvm/test/MC/ARM/thumb-function-address.s b/llvm/test/MC/ARM/thumb-function-address.s --- a/llvm/test/MC/ARM/thumb-function-address.s +++ b/llvm/test/MC/ARM/thumb-function-address.s @@ -39,4 +39,4 @@ @ CHECK-NEXT: 00000003 0 FUNC LOCAL DEFAULT 2 foo_resolver @ CHECK-NEXT: 00000003 0 IFUNC LOCAL DEFAULT 2 foo @ CHECK-NEXT: 00000004 0 FUNC LOCAL DEFAULT 2 label -@ CHECK-NEXT: 00000006 0 NOTYPE LOCAL DEFAULT 2 $a.1 +@ CHECK-NEXT: 00000008 0 NOTYPE LOCAL DEFAULT 2 $a.1 diff --git a/llvm/test/MC/ARM/thumb-types.s b/llvm/test/MC/ARM/thumb-types.s --- a/llvm/test/MC/ARM/thumb-types.s +++ b/llvm/test/MC/ARM/thumb-types.s @@ -6,15 +6,15 @@ @ CHECK-NEXT: 2: 00000000 0 NOTYPE LOCAL DEFAULT 2 $t.0 @ CHECK-NEXT: 3: 00000002 0 OBJECT LOCAL DEFAULT 2 implicit_data @ CHECK-NEXT: 4: 00000002 0 NOTYPE LOCAL DEFAULT 2 $d.1 -@ CHECK-NEXT: 5: 00000006 0 FUNC LOCAL DEFAULT 2 arm_function -@ CHECK-NEXT: 6: 00000006 0 NOTYPE LOCAL DEFAULT 2 $a.2 -@ CHECK-NEXT: 7: 0000000a 0 NOTYPE LOCAL DEFAULT 2 untyped_text_label -@ CHECK-NEXT: 8: 0000000a 0 NOTYPE LOCAL DEFAULT 2 $t.3 -@ CHECK-NEXT: 9: 0000000d 0 FUNC LOCAL DEFAULT 2 explicit_function -@ CHECK-NEXT: 10: 0000000e 0 NOTYPE LOCAL DEFAULT 2 $d.4 +@ CHECK-NEXT: 5: 00000008 0 FUNC LOCAL DEFAULT 2 arm_function +@ CHECK-NEXT: 6: 00000008 0 NOTYPE LOCAL DEFAULT 2 $a.2 +@ CHECK-NEXT: 7: 0000000c 0 NOTYPE LOCAL DEFAULT 2 untyped_text_label +@ CHECK-NEXT: 8: 0000000c 0 NOTYPE LOCAL DEFAULT 2 $t.3 +@ CHECK-NEXT: 9: 0000000f 0 FUNC LOCAL DEFAULT 2 explicit_function +@ CHECK-NEXT: 10: 00000010 0 NOTYPE LOCAL DEFAULT 2 $d.4 @ CHECK-NEXT: 11: 00000000 4 TLS LOCAL DEFAULT 5 tls -@ CHECK-NEXT: 12: 00000013 0 IFUNC LOCAL DEFAULT 2 indirect_function -@ CHECK-NEXT: 13: 00000012 0 NOTYPE LOCAL DEFAULT 2 $t.5 +@ CHECK-NEXT: 12: 00000015 0 IFUNC LOCAL DEFAULT 2 indirect_function +@ CHECK-NEXT: 13: 00000014 0 NOTYPE LOCAL DEFAULT 2 $t.5 @ CHECK-NEXT: 14: 00000000 0 NOTYPE LOCAL DEFAULT 4 untyped_data_label @ CHECK-NEXT: 15: 00000000 0 NOTYPE LOCAL DEFAULT 4 $t.6 @ CHECK-NEXT: 16: 00000002 0 OBJECT LOCAL DEFAULT 4 explicit_data