diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll --- a/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll @@ -1,5 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-NO-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -mattr=-no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-BYPASS-DELAY ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-V4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 @@ -107,10 +108,15 @@ } define <16 x float> @transform_VPERMILPSZrm(ptr %ap) nounwind { -; CHECK-ICX-LABEL: transform_VPERMILPSZrm: -; CHECK-ICX: # %bb.0: -; CHECK-ICX-NEXT: vpshufd {{.*#+}} zmm0 = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] -; CHECK-ICX-NEXT: retq +; CHECK-ICX-NO-BYPASS-DELAY-LABEL: transform_VPERMILPSZrm: +; CHECK-ICX-NO-BYPASS-DELAY: # %bb.0: +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: vpshufd {{.*#+}} zmm0 = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: retq +; +; CHECK-ICX-BYPASS-DELAY-LABEL: transform_VPERMILPSZrm: +; CHECK-ICX-BYPASS-DELAY: # %bb.0: +; CHECK-ICX-BYPASS-DELAY-NEXT: vpermilps {{.*#+}} zmm0 = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] +; CHECK-ICX-BYPASS-DELAY-NEXT: retq ; ; CHECK-V4-LABEL: transform_VPERMILPSZrm: ; CHECK-V4: # %bb.0: @@ -182,11 +188,17 @@ } define <16 x float> @transform_VPERMILPSZrmkz(ptr %ap, i16 %mask_int) nounwind { -; CHECK-ICX-LABEL: transform_VPERMILPSZrmkz: -; CHECK-ICX: # %bb.0: -; CHECK-ICX-NEXT: kmovd %esi, %k1 -; CHECK-ICX-NEXT: vpshufd {{.*#+}} zmm0 {%k1} {z} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] -; CHECK-ICX-NEXT: retq +; CHECK-ICX-NO-BYPASS-DELAY-LABEL: transform_VPERMILPSZrmkz: +; CHECK-ICX-NO-BYPASS-DELAY: # %bb.0: +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: kmovd %esi, %k1 +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: vpshufd {{.*#+}} zmm0 {%k1} {z} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: retq +; +; CHECK-ICX-BYPASS-DELAY-LABEL: transform_VPERMILPSZrmkz: +; CHECK-ICX-BYPASS-DELAY: # %bb.0: +; CHECK-ICX-BYPASS-DELAY-NEXT: kmovd %esi, %k1 +; CHECK-ICX-BYPASS-DELAY-NEXT: vpermilps {{.*#+}} zmm0 {%k1} {z} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] +; CHECK-ICX-BYPASS-DELAY-NEXT: retq ; ; CHECK-V4-LABEL: transform_VPERMILPSZrmkz: ; CHECK-V4: # %bb.0: @@ -275,11 +287,17 @@ } define <16 x float> @transform_VPERMILPSZrmk(ptr %ap, <16 x float> %b, i16 %mask_int) nounwind { -; CHECK-ICX-LABEL: transform_VPERMILPSZrmk: -; CHECK-ICX: # %bb.0: -; CHECK-ICX-NEXT: kmovd %esi, %k1 -; CHECK-ICX-NEXT: vpshufd {{.*#+}} zmm0 {%k1} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] -; CHECK-ICX-NEXT: retq +; CHECK-ICX-NO-BYPASS-DELAY-LABEL: transform_VPERMILPSZrmk: +; CHECK-ICX-NO-BYPASS-DELAY: # %bb.0: +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: kmovd %esi, %k1 +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: vpshufd {{.*#+}} zmm0 {%k1} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] +; CHECK-ICX-NO-BYPASS-DELAY-NEXT: retq +; +; CHECK-ICX-BYPASS-DELAY-LABEL: transform_VPERMILPSZrmk: +; CHECK-ICX-BYPASS-DELAY: # %bb.0: +; CHECK-ICX-BYPASS-DELAY-NEXT: kmovd %esi, %k1 +; CHECK-ICX-BYPASS-DELAY-NEXT: vpermilps {{.*#+}} zmm0 {%k1} = mem[3,2,1,0,7,6,5,4,11,10,9,8,15,14,13,12] +; CHECK-ICX-BYPASS-DELAY-NEXT: retq ; ; CHECK-V4-LABEL: transform_VPERMILPSZrmk: ; CHECK-V4: # %bb.0: diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll b/llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll --- a/llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-permilps.ll @@ -3,6 +3,8 @@ ; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx | FileCheck %s --check-prefixes=CHECK,CHECK-AVX1-DELAY ; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx2,+no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown --mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-NO-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -mattr=-no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-BYPASS-DELAY define <8 x float> @transform_VPERMILPSYrr(<8 x float> %a) nounwind { ; CHECK-LABEL: transform_VPERMILPSYrr: @@ -42,6 +44,11 @@ ; CHECK-AVX2-DELAY: # %bb.0: ; CHECK-AVX2-DELAY-NEXT: vpermilps {{.*#+}} ymm0 = mem[3,2,1,0,7,6,5,4] ; CHECK-AVX2-DELAY-NEXT: retq +; +; CHECK-ICX-LABEL: transform_VPERMILPSYrm: +; CHECK-ICX: # %bb.0: +; CHECK-ICX-NEXT: vpshufd {{.*#+}} ymm0 = mem[3,2,1,0,7,6,5,4] +; CHECK-ICX-NEXT: retq %a = load <8 x float>, ptr %ap %shufp = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> ret <8 x float> %shufp @@ -67,7 +74,15 @@ ; CHECK-AVX2-DELAY: # %bb.0: ; CHECK-AVX2-DELAY-NEXT: vpermilps {{.*#+}} xmm0 = mem[3,2,1,0] ; CHECK-AVX2-DELAY-NEXT: retq +; +; CHECK-ICX-LABEL: transform_VPERMILPSrm: +; CHECK-ICX: # %bb.0: +; CHECK-ICX-NEXT: vpshufd {{.*#+}} xmm0 = mem[3,2,1,0] +; CHECK-ICX-NEXT: retq %a = load <4 x float>, ptr %ap %shufp = shufflevector <4 x float> %a, <4 x float> poison, <4 x i32> ret <4 x float> %shufp } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-ICX-BYPASS-DELAY: {{.*}} +; CHECK-ICX-NO-BYPASS-DELAY: {{.*}} diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll --- a/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefixes=CHECK,CHECK-SKX -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-NO-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -mattr=-no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-BYPASS-DELAY ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-V4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 @@ -719,3 +720,6 @@ %res = select <2 x i1> %mask, <2 x double> %shufp, <2 x double> %c ret <2 x double> %res } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-ICX-BYPASS-DELAY: {{.*}} +; CHECK-ICX-NO-BYPASS-DELAY: {{.*}} diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll b/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll --- a/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll +++ b/llvm/test/CodeGen/X86/tuning-shuffle-unpckpd.ll @@ -1,7 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2,CHECK-SKL ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2,CHECK-V3 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-NO-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -mattr=-no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-BYPASS-DELAY define <8 x float> @transform_VUNPCKLPDYrr(<8 x float> %a, <8 x float> %b) nounwind { ; CHECK-AVX2-LABEL: transform_VUNPCKLPDYrr: @@ -99,5 +100,7 @@ ret <4 x float> %shufp } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-ICX-BYPASS-DELAY: {{.*}} +; CHECK-ICX-NO-BYPASS-DELAY: {{.*}} ; CHECK-SKL: {{.*}} ; CHECK-V3: {{.*}} diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll b/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll @@ -0,0 +1,441 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake-avx512 | FileCheck %s --check-prefixes=CHECK,CHECK-SKX +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-NO-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -mattr=-no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,CHECK-V4 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s --check-prefixes=CHECK,CHECK-AVX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,CHECK-ZNVER4 + +define <16 x float> @transform_VUNPCKLPSZrr(<16 x float> %a, <16 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSZrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] +; CHECK-NEXT: retq + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + ret <16 x float> %shufp +} + +define <16 x float> @transform_VUNPCKHPSZrr(<16 x float> %a, <16 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSZrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} zmm0 = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] +; CHECK-NEXT: retq + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + ret <16 x float> %shufp +} + +define <8 x float> @transform_VUNPCKLPSYrr(<8 x float> %a, <8 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; CHECK-NEXT: retq + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <8 x float> @transform_VUNPCKHPSYrr(<8 x float> %a, <8 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; CHECK-NEXT: retq + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <4 x float> @transform_VUNPCKLPSrr(<4 x float> %a, <4 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; CHECK-NEXT: retq + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <4 x float> @transform_VUNPCKHPSrr(<4 x float> %a, <4 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; CHECK-NEXT: retq + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <16 x float> @transform_VUNPCKLPSZrrkz(<16 x float> %a, <16 x float> %b, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSZrrkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} {z} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> zeroinitializer + ret <16 x float> %res +} + +define <16 x float> @transform_VUNPCKHPSZrrkz(<16 x float> %a, <16 x float> %b, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSZrrkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} {z} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> zeroinitializer + ret <16 x float> %res +} + +define <8 x float> @transform_VUNPCKLPSYrrkz(<8 x float> %a, <8 x float> %b, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrrkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 {%k1} {z} = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> zeroinitializer + ret <8 x float> %res +} + +define <8 x float> @transform_VUNPCKHPSYrrkz(<8 x float> %a, <8 x float> %b, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrrkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 {%k1} {z} = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> zeroinitializer + ret <8 x float> %res +} + +define <4 x float> @transform_VUNPCKLPSrrkz(<4 x float> %a, <4 x float> %b, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrrkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 {%k1} {z} = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> zeroinitializer + ret <4 x float> %res +} + +define <4 x float> @transform_VUNPCKHPSrrkz(<4 x float> %a, <4 x float> %b, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrrkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 {%k1} {z} = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> zeroinitializer + ret <4 x float> %res +} + +define <16 x float> @transform_VUNPCKLPSZrrk(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSZrrk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} zmm2 {%k1} = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[12],zmm1[12],zmm0[13],zmm1[13] +; CHECK-NEXT: vmovaps %zmm2, %zmm0 +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> %c + ret <16 x float> %res +} + +define <16 x float> @transform_VUNPCKHPSZrrk(<16 x float> %a, <16 x float> %b, <16 x float> %c, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSZrrk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} zmm2 {%k1} = zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[14],zmm1[14],zmm0[15],zmm1[15] +; CHECK-NEXT: vmovaps %zmm2, %zmm0 +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> %c + ret <16 x float> %res +} + +define <8 x float> @transform_VUNPCKLPSYrrk(<8 x float> %a, <8 x float> %b, <8 x float> %c, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrrk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} ymm2 {%k1} = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; CHECK-NEXT: vmovaps %ymm2, %ymm0 +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> %c + ret <8 x float> %res +} + +define <8 x float> @transform_VUNPCKHPSYrrk(<8 x float> %a, <8 x float> %b, <8 x float> %c, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrrk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} ymm2 {%k1} = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; CHECK-NEXT: vmovaps %ymm2, %ymm0 +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> %c + ret <8 x float> %res +} + +define <4 x float> @transform_VUNPCKLPSrrk(<4 x float> %a, <4 x float> %b, <4 x float> %c, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrrk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} xmm2 {%k1} = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; CHECK-NEXT: vmovaps %xmm2, %xmm0 +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> %c + ret <4 x float> %res +} + +define <4 x float> @transform_VUNPCKHPSrrk(<4 x float> %a, <4 x float> %b, <4 x float> %c, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrrk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %edi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} xmm2 {%k1} = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; CHECK-NEXT: vmovaps %xmm2, %xmm0 +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> %c + ret <4 x float> %res +} + +define <16 x float> @transform_VUNPCKLPSZrm(<16 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSZrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} zmm0 = zmm0[0],mem[0],zmm0[1],mem[1],zmm0[4],mem[4],zmm0[5],mem[5],zmm0[8],mem[8],zmm0[9],mem[9],zmm0[12],mem[12],zmm0[13],mem[13] +; CHECK-NEXT: retq + %b = load <16 x float>, ptr %pb + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + ret <16 x float> %shufp +} + +define <16 x float> @transform_VUNPCKHPSZrm(<16 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSZrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} zmm0 = zmm0[2],mem[2],zmm0[3],mem[3],zmm0[6],mem[6],zmm0[7],mem[7],zmm0[10],mem[10],zmm0[11],mem[11],zmm0[14],mem[14],zmm0[15],mem[15] +; CHECK-NEXT: retq + %b = load <16 x float>, ptr %pb + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + ret <16 x float> %shufp +} + +define <8 x float> @transform_VUNPCKLPSYrm(<8 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] +; CHECK-NEXT: retq + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <8 x float> @transform_VUNPCKHPSYrm(<8 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] +; CHECK-NEXT: retq + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <4 x float> @transform_VUNPCKLPSrm(<4 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] +; CHECK-NEXT: retq + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <4 x float> @transform_VUNPCKHPSrm(<4 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] +; CHECK-NEXT: retq + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <16 x float> @transform_VUNPCKLPSZrmkz(<16 x float> %a, ptr %pb, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSZrmkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} zmm0 {%k1} {z} = zmm0[0],mem[0],zmm0[1],mem[1],zmm0[4],mem[4],zmm0[5],mem[5],zmm0[8],mem[8],zmm0[9],mem[9],zmm0[12],mem[12],zmm0[13],mem[13] +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %b = load <16 x float>, ptr %pb + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> zeroinitializer + ret <16 x float> %res +} + +define <16 x float> @transform_VUNPCKHPSZrmkz(<16 x float> %a, ptr %pb, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSZrmkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} zmm0 {%k1} {z} = zmm0[2],mem[2],zmm0[3],mem[3],zmm0[6],mem[6],zmm0[7],mem[7],zmm0[10],mem[10],zmm0[11],mem[11],zmm0[14],mem[14],zmm0[15],mem[15] +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %b = load <16 x float>, ptr %pb + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> zeroinitializer + ret <16 x float> %res +} + +define <8 x float> @transform_VUNPCKLPSYrmkz(<8 x float> %a, ptr %pb, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrmkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 {%k1} {z} = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> zeroinitializer + ret <8 x float> %res +} + +define <8 x float> @transform_VUNPCKHPSYrmkz(<8 x float> %a, ptr %pb, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrmkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 {%k1} {z} = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> zeroinitializer + ret <8 x float> %res +} + +define <4 x float> @transform_VUNPCKLPSrmkz(<4 x float> %a, ptr %pb, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrmkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 {%k1} {z} = xmm0[0],mem[0],xmm0[1],mem[1] +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> zeroinitializer + ret <4 x float> %res +} + +define <4 x float> @transform_VUNPCKHPSrmkz(<4 x float> %a, ptr %pb, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrmkz: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 {%k1} {z} = xmm0[2],mem[2],xmm0[3],mem[3] +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> zeroinitializer + ret <4 x float> %res +} + +define <16 x float> @transform_VUNPCKLPSZrmk(<16 x float> %a, ptr %pb, <16 x float> %c, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSZrmk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} zmm1 {%k1} = zmm0[0],mem[0],zmm0[1],mem[1],zmm0[4],mem[4],zmm0[5],mem[5],zmm0[8],mem[8],zmm0[9],mem[9],zmm0[12],mem[12],zmm0[13],mem[13] +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %b = load <16 x float>, ptr %pb + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> %c + ret <16 x float> %res +} + +define <16 x float> @transform_VUNPCKHPSZrmk(<16 x float> %a, ptr %pb, <16 x float> %c, i16 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSZrmk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} zmm1 {%k1} = zmm0[2],mem[2],zmm0[3],mem[3],zmm0[6],mem[6],zmm0[7],mem[7],zmm0[10],mem[10],zmm0[11],mem[11],zmm0[14],mem[14],zmm0[15],mem[15] +; CHECK-NEXT: vmovaps %zmm1, %zmm0 +; CHECK-NEXT: retq + %mask = bitcast i16 %mask_int to <16 x i1> + %b = load <16 x float>, ptr %pb + %shufp = shufflevector <16 x float> %a, <16 x float> %b, <16 x i32> + %res = select <16 x i1> %mask, <16 x float> %shufp, <16 x float> %c + ret <16 x float> %res +} + +define <8 x float> @transform_VUNPCKLPSYrmk(<8 x float> %a, ptr %pb, <8 x float> %c, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrmk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} ymm1 {%k1} = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] +; CHECK-NEXT: vmovaps %ymm1, %ymm0 +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> %c + ret <8 x float> %res +} + +define <8 x float> @transform_VUNPCKHPSYrmk(<8 x float> %a, ptr %pb, <8 x float> %c, i8 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrmk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} ymm1 {%k1} = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] +; CHECK-NEXT: vmovaps %ymm1, %ymm0 +; CHECK-NEXT: retq + %mask = bitcast i8 %mask_int to <8 x i1> + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + %res = select <8 x i1> %mask, <8 x float> %shufp, <8 x float> %c + ret <8 x float> %res +} + +define <4 x float> @transform_VUNPCKLPSrmk(<4 x float> %a, ptr %pb, <4 x float> %c, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrmk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpcklps {{.*#+}} xmm1 {%k1} = xmm0[0],mem[0],xmm0[1],mem[1] +; CHECK-NEXT: vmovaps %xmm1, %xmm0 +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> %c + ret <4 x float> %res +} + +define <4 x float> @transform_VUNPCKHPSrmk(<4 x float> %a, ptr %pb, <4 x float> %c, i4 %mask_int) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrmk: +; CHECK: # %bb.0: +; CHECK-NEXT: kmovd %esi, %k1 +; CHECK-NEXT: vunpckhps {{.*#+}} xmm1 {%k1} = xmm0[2],mem[2],xmm0[3],mem[3] +; CHECK-NEXT: vmovaps %xmm1, %xmm0 +; CHECK-NEXT: retq + %mask = bitcast i4 %mask_int to <4 x i1> + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + %res = select <4 x i1> %mask, <4 x float> %shufp, <4 x float> %c + ret <4 x float> %res +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-AVX512: {{.*}} +; CHECK-ICX: {{.*}} +; CHECK-ICX-BYPASS-DELAY: {{.*}} +; CHECK-ICX-NO-BYPASS-DELAY: {{.*}} +; CHECK-SKX: {{.*}} +; CHECK-V4: {{.*}} +; CHECK-ZNVER4: {{.*}} diff --git a/llvm/test/CodeGen/X86/tuning-shuffle-unpckps.ll b/llvm/test/CodeGen/X86/tuning-shuffle-unpckps.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/tuning-shuffle-unpckps.ll @@ -0,0 +1,88 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2,CHECK-SKL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,CHECK-AVX2,CHECK-V3 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-NO-BYPASS-DELAY +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=icelake-server -mattr=-no-bypass-delay-shuffle | FileCheck %s --check-prefixes=CHECK,CHECK-ICX,CHECK-ICX-BYPASS-DELAY + +define <8 x float> @transform_VUNPCKLPSYrr(<8 x float> %a, <8 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],ymm1[0],ymm0[1],ymm1[1],ymm0[4],ymm1[4],ymm0[5],ymm1[5] +; CHECK-NEXT: retq + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <8 x float> @transform_VUNPCKHPSYrr(<8 x float> %a, <8 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],ymm1[2],ymm0[3],ymm1[3],ymm0[6],ymm1[6],ymm0[7],ymm1[7] +; CHECK-NEXT: retq + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <4 x float> @transform_VUNPCKLPSrr(<4 x float> %a, <4 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] +; CHECK-NEXT: retq + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <4 x float> @transform_VUNPCKHPSrr(<4 x float> %a, <4 x float> %b) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrr: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] +; CHECK-NEXT: retq + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <8 x float> @transform_VUNPCKLPSYrm(<8 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSYrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} ymm0 = ymm0[0],mem[0],ymm0[1],mem[1],ymm0[4],mem[4],ymm0[5],mem[5] +; CHECK-NEXT: retq + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <8 x float> @transform_VUNPCKHPSYrm(<8 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSYrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} ymm0 = ymm0[2],mem[2],ymm0[3],mem[3],ymm0[6],mem[6],ymm0[7],mem[7] +; CHECK-NEXT: retq + %b = load <8 x float>, ptr %pb + %shufp = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> + ret <8 x float> %shufp +} + +define <4 x float> @transform_VUNPCKLPSrm(<4 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKLPSrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpcklps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] +; CHECK-NEXT: retq + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} + +define <4 x float> @transform_VUNPCKHPSrm(<4 x float> %a, ptr %pb) nounwind { +; CHECK-LABEL: transform_VUNPCKHPSrm: +; CHECK: # %bb.0: +; CHECK-NEXT: vunpckhps {{.*#+}} xmm0 = xmm0[2],mem[2],xmm0[3],mem[3] +; CHECK-NEXT: retq + %b = load <4 x float>, ptr %pb + %shufp = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> + ret <4 x float> %shufp +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; CHECK-AVX2: {{.*}} +; CHECK-ICX: {{.*}} +; CHECK-ICX-BYPASS-DELAY: {{.*}} +; CHECK-ICX-NO-BYPASS-DELAY: {{.*}} +; CHECK-SKL: {{.*}} +; CHECK-V3: {{.*}}