diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1119,7 +1119,7 @@
   if (Subtarget.hasVInstructions())
     setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER,
                          ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA, ISD::SRL,
-                         ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR});
+                         ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR, ISD::CONCAT_VECTORS});
   if (Subtarget.hasVendorXTHeadMemPair())
     setTargetDAGCombine({ISD::LOAD, ISD::STORE});
   if (Subtarget.useRVVForFixedLengthVectors())
@@ -11340,6 +11340,106 @@
       return Gather;
     break;
   }
+  case ISD::CONCAT_VECTORS: {
+    SDLoc DL(N);
+    EVT VT = N->getValueType(0);
+    // Only perform this combine on legal MVT types.
+    if (!isTypeLegal(VT))
+      break;
+
+    // TODO: Potentially extend this to scalable vectors
+    if (VT.isScalableVector())
+      break;
+
+    // If we're concatenating a series of vector loads like
+    // concat_vectors (load v4i8, p+0), (load v4i8, p+n), (load v4i8, p+n*2) ...
+    // Then we can turn this into a strided load by widening the vector elements
+    // vlse32 p, n
+    auto *BaseLd = dyn_cast<LoadSDNode>(N->getOperand(0));
+    if (!BaseLd || !BaseLd->isSimple() || !SDValue(BaseLd, 0).hasOneUse())
+      break;
+
+    EVT BaseLdVT = BaseLd->getValueType(0);
+    SDValue BasePtr = BaseLd->getBasePtr();
+
+    auto IsStrided = [&BasePtr, &BaseLdVT, &N]() {
+      SDValue Stride;
+      SDValue CurPtr = BasePtr;
+      for (SDValue Op : N->ops().drop_front()) {
+        auto *Ld = dyn_cast<LoadSDNode>(Op);
+        if (!Ld || !Ld->isSimple() || !Op.hasOneUse())
+          return SDValue();
+        SDValue Ptr = Ld->getBasePtr();
+        if (Ptr.getOpcode() != ISD::ADD || Ptr.getOperand(0) != CurPtr)
+          return SDValue();
+        SDValue Offset = Ptr.getOperand(1);
+        if (!Stride)
+          Stride = Offset;
+        else if (Offset != Stride)
+          return SDValue();
+        if (Ld->getValueType(0) != BaseLdVT)
+          return SDValue();
+        CurPtr = Ptr;
+      }
+      return Stride;
+    };
+
+    SDValue Stride = IsStrided();
+    if (!Stride)
+      break;
+
+    // A special case is if the stride is exactly the width of one of the loads,
+    // in which case it's contiguous and can be combined into a regular vle
+    // without changing the element size
+    if (auto *ConstStride = dyn_cast<ConstantSDNode>(Stride)) {
+      if (ConstStride->getZExtValue() == BaseLdVT.getFixedSizeInBits() / 8) {
+        SDValue WideLoad =
+            DAG.getLoad(VT, DL, BaseLd->getChain(), BasePtr,
+                        DAG.getMachineFunction().getMachineMemOperand(
+                            BaseLd->getMemOperand(), 0, VT.getStoreSize()));
+        DAG.makeEquivalentMemoryOrdering(BaseLd, WideLoad);
+        return WideLoad;
+      }
+    }
+
+    // Get the widened scalar type, e.g. v4i8 -> i64
+    MVT WideScalarVT;
+    unsigned WideScalarBitWidth =
+        BaseLdVT.getScalarSizeInBits() * BaseLdVT.getVectorNumElements();
+    if (BaseLdVT.isInteger())
+      WideScalarVT = MVT::getIntegerVT(WideScalarBitWidth);
+    else if (BaseLdVT.isFloatingPoint())
+      WideScalarVT = MVT::getFloatingPointVT(WideScalarBitWidth);
+    else
+      break;
+
+    // Get the vector type for the strided load, e.g. 4 x v4i8 -> v4i64
+    MVT WideVecVT =
+        MVT::getVectorVT(WideScalarVT, N->getNumOperands());
+    if (!isTypeLegal(WideVecVT))
+      break;
+
+    MVT ContainerVT = getContainerForFixedLengthVector(WideVecVT);
+    SDValue VL =
+        getDefaultVLOps(WideVecVT, ContainerVT, DL, DAG, Subtarget).second;
+    SDVTList VTs = DAG.getVTList({ContainerVT, MVT::Other});
+    SDValue IntID =
+        DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, Subtarget.getXLenVT());
+    SDValue Ops[] = {BaseLd->getChain(),
+                     IntID,
+                     DAG.getUNDEF(ContainerVT),
+                     BasePtr,
+                     Stride,
+                     VL};
+    SDValue StridedLoad = DAG.getMemIntrinsicNode(
+        ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, WideVecVT,
+        DAG.getMachineFunction().getMachineMemOperand(
+            BaseLd->getMemOperand(), 0, WideVecVT.getStoreSize()));
+    DAG.makeEquivalentMemoryOrdering(BaseLd, StridedLoad);
+    return DAG.getBitcast(
+        VT, convertFromScalableVector(WideVecVT, StridedLoad, DAG, Subtarget));
+    break;
+  }
   case RISCVISD::VMV_V_X_VL: {
     // Tail agnostic VMV.V.X only demands the vector element bitwidth from the
     // scalar input.
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-combine.ll
@@ -6,12 +6,8 @@
 define void @widen_2xv4i16(ptr %x, ptr %z) {
 ; CHECK-LABEL: widen_2xv4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    addi a0, a0, 8
-; CHECK-NEXT:    vle16.v v9, (a0)
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 4
+; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vse16.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i16>, ptr %x
@@ -74,20 +70,8 @@
 define void @widen_4xv4i16(ptr %x, ptr %z) {
 ; CHECK-LABEL: widen_4xv4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    addi a2, a0, 8
-; CHECK-NEXT:    vle16.v v10, (a2)
-; CHECK-NEXT:    addi a2, a0, 16
-; CHECK-NEXT:    vle16.v v12, (a2)
-; CHECK-NEXT:    addi a0, a0, 24
-; CHECK-NEXT:    vle16.v v14, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v10, 4
-; CHECK-NEXT:    vsetivli zero, 12, e16, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v12, 8
 ; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v14, 12
+; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    vse16.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i16>, ptr %x
@@ -108,13 +92,10 @@
 define void @strided_constant(ptr %x, ptr %z) {
 ; CHECK-LABEL: strided_constant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    addi a0, a0, 16
-; CHECK-NEXT:    vle16.v v9, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 4
-; CHECK-NEXT:    vse16.v v8, (a1)
+; CHECK-NEXT:    li a2, 16
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:    vlse64.v v8, (a0), a2
+; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i16>, ptr %x
   %b.gep = getelementptr i8, ptr %x, i64 16
@@ -128,13 +109,10 @@
 define void @strided_constant_64(ptr %x, ptr %z) {
 ; CHECK-LABEL: strided_constant_64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    addi a0, a0, 64
-; CHECK-NEXT:    vle16.v v9, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 4
-; CHECK-NEXT:    vse16.v v8, (a1)
+; CHECK-NEXT:    li a2, 64
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:    vlse64.v v8, (a0), a2
+; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i16>, ptr %x
   %b.gep = getelementptr i8, ptr %x, i64 64
@@ -148,12 +126,8 @@
 define void @strided_constant_v4i32(ptr %x, ptr %z) {
 ; CHECK-LABEL: strided_constant_v4i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    addi a0, a0, 16
-; CHECK-NEXT:    vle32.v v10, (a0)
 ; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v10, 4
+; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    vse32.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i32>, ptr %x
@@ -186,13 +160,9 @@
 define void @strided_runtime(ptr %x, ptr %z, i64 %s) {
 ; CHECK-LABEL: strided_runtime:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v9, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 4
-; CHECK-NEXT:    vse16.v v8, (a1)
+; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-NEXT:    vlse64.v v8, (a0), a2
+; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i16>, ptr %x
   %b.gep = getelementptr i8, ptr %x, i64 %s
@@ -206,21 +176,9 @@
 define void @strided_runtime_4xv4i16(ptr %x, ptr %z, i64 %s) {
 ; CHECK-LABEL: strided_runtime_4xv4i16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v10, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v12, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v14, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v10, 4
-; CHECK-NEXT:    vsetivli zero, 12, e16, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v12, 8
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v14, 12
-; CHECK-NEXT:    vse16.v v8, (a1)
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT:    vlse64.v v8, (a0), a2
+; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x i16>, ptr %x
   %b.gep = getelementptr i8, ptr %x, i64 %s
@@ -239,21 +197,9 @@
 define void @strided_runtime_4xv4f16(ptr %x, ptr %z, i64 %s) {
 ; CHECK-LABEL: strided_runtime_4xv4f16:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v10, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v12, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle16.v v14, (a0)
-; CHECK-NEXT:    vsetivli zero, 8, e16, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v10, 4
-; CHECK-NEXT:    vsetivli zero, 12, e16, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v12, 8
-; CHECK-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v14, 12
-; CHECK-NEXT:    vse16.v v8, (a1)
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT:    vlse64.v v8, (a0), a2
+; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <4 x half>, ptr %x
   %b.gep = getelementptr i8, ptr %x, i64 %s
@@ -272,21 +218,9 @@
 define void @strided_runtime_4xv2f32(ptr %x, ptr %z, i64 %s) {
 ; CHECK-LABEL: strided_runtime_4xv2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vle32.v v8, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle32.v v10, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle32.v v12, (a0)
-; CHECK-NEXT:    add a0, a0, a2
-; CHECK-NEXT:    vle32.v v14, (a0)
-; CHECK-NEXT:    vsetivli zero, 4, e32, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v10, 2
-; CHECK-NEXT:    vsetivli zero, 6, e32, m2, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v12, 4
-; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT:    vslideup.vi v8, v14, 6
-; CHECK-NEXT:    vse32.v v8, (a1)
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT:    vlse64.v v8, (a0), a2
+; CHECK-NEXT:    vse64.v v8, (a1)
 ; CHECK-NEXT:    ret
   %a = load <2 x float>, ptr %x
   %b.gep = getelementptr i8, ptr %x, i64 %s