Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -18661,6 +18661,20 @@
       N->getOperand(0)->getOpcode() == ISD::SETCC)
     return performSignExtendSetCCCombine(N, DCI, DAG);
 
+  if (N->getValueType(0).isFixedLengthVector() &&
+      N->getOpcode() == ISD::ANY_EXTEND &&
+      N->getOperand(0).getOpcode() == ISD::BITCAST) {
+    SDNode *N00 = N->getOperand(0).getOperand(0)->getNode();
+
+    if (N00.getNode()->getValueType(0).isScalarInteger() &&
+        N->getValueType(0).getScalarType() == N00.getNode()->getValueType(0)) {
+      // Use SCALAR_TO_VECTOR for lane zero
+      SDValue Vec =
+          DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), N00);
+      return Vec;
+    }
+  }
+
   return SDValue();
 }
 
Index: llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
+++ llvm/test/CodeGen/AArch64/sve-fixed-length-int-extends.ll
@@ -1043,4 +1043,13 @@
   ret void
 }
 
+define <2 x i16> @bitcast_from_int(i32 %word) {
+; CHECK-LABEL: bitcast_from_int:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmov s0, w0
+; CHECK-NEXT:    ret
+    %ret = bitcast i32 %word to <2 x i16>
+    ret <2 x i16> %ret
+}
+
 attributes #0 = { nounwind "target-features"="+sve" }