Index: clang/test/Preprocessor/riscv-target-features.c =================================================================== --- clang/test/Preprocessor/riscv-target-features.c +++ clang/test/Preprocessor/riscv-target-features.c @@ -60,6 +60,7 @@ // CHECK-NOT: __riscv_zvksh {{.*$}} // CHECK-NOT: __riscv_zicond {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} +// CHECK-NOT: __riscv_zvfbfmin {{.*$}} // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ // RUN: -o - | FileCheck %s @@ -611,3 +612,9 @@ // RUN: %clang -target riscv64 -march=rv64izfbfmin -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s // CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 2000{{$}} + +// RUN: %clang -target riscv32 -march=rv32izvfbfmin -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s +// RUN: %clang -target riscv64 -march=rv64izvfbfmin -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s +// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 2000{{$}} Index: llvm/docs/RISCVUsage.rst =================================================================== --- llvm/docs/RISCVUsage.rst +++ llvm/docs/RISCVUsage.rst @@ -202,6 +202,9 @@ ``experimental-ztso`` LLVM implements the `v0.1 proposed specification `_ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware. +``experimental-zvfbfmin`` + LLVM implements assembler support for the `20230322 draft specification `_. + ``experimental-zvfh`` LLVM implements `this draft text `_. Index: llvm/docs/ReleaseNotes.rst =================================================================== --- llvm/docs/ReleaseNotes.rst +++ llvm/docs/ReleaseNotes.rst @@ -157,7 +157,7 @@ New version I2.1, F2.2, D2.2, A2.1. This should not impact code generation. Immpacts versions accepted in ``-march`` and reported in ELF attributes. * Assembly support was added for the experimental Zfbfmin (scalar BF16 - conversions) extension. + conversions) and Zvfbfmin (vector BF16 conversions) extensions. Changes to the WebAssembly Backend ---------------------------------- Index: llvm/lib/Support/RISCVISAInfo.cpp =================================================================== --- llvm/lib/Support/RISCVISAInfo.cpp +++ llvm/lib/Support/RISCVISAInfo.cpp @@ -141,6 +141,7 @@ {"zfa", RISCVExtensionVersion{0, 1}}, {"zfbfmin", RISCVExtensionVersion{0, 2}}, {"zicond", RISCVExtensionVersion{1, 0}}, + {"zvfbfmin", RISCVExtensionVersion{0, 2}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, @@ -932,6 +933,7 @@ static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"}; static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; +static const char *ImpliedExtsZvfbfmin[] = {"zve32f"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; static const char *ImpliedExtsZvkn[] = {"zvkned", "zvknhb", "zvkb"}; static const char *ImpliedExtsZvknhb[] = {"zvknha"}; @@ -973,6 +975,7 @@ {{"zve64d"}, {ImpliedExtsZve64d}}, {{"zve64f"}, {ImpliedExtsZve64f}}, {{"zve64x"}, {ImpliedExtsZve64x}}, + {{"zvfbfmin"}, {ImpliedExtsZvfbfmin}}, {{"zvfh"}, {ImpliedExtsZvfh}}, {{"zvkn"}, {ImpliedExtsZvkn}}, {{"zvknhb"}, {ImpliedExtsZvknhb}}, Index: llvm/lib/Target/RISCV/RISCVFeatures.td =================================================================== --- llvm/lib/Target/RISCV/RISCVFeatures.td +++ llvm/lib/Target/RISCV/RISCVFeatures.td @@ -421,6 +421,14 @@ "'V' (Vector Extension for Application Processors), 'Zve32f', " "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">; +def FeatureStdExtZvfbfmin + : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true", + "'Zvbfmin' (Vector BF16 Converts)", + [FeatureStdExtZve32f]>; +def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, + AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), + "'Zvfbfmin' (Vector BF16 Converts)">; + def FeatureStdExtZvfh : SubtargetFeature<"experimental-zvfh", "HasStdExtZvfh", "true", "'Zvfh' (Vector Half-Precision Floating-Point)", Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td =================================================================== --- llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1781,5 +1781,6 @@ } } // Predicates = [HasVInstructionsI64, IsRV64] +include "RISCVInstrInfoZvfbf.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoVPseudos.td" Index: llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td =================================================================== --- /dev/null +++ llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -0,0 +1,26 @@ +//===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Zvfbfmin' +// extension, providing vector conversion instructions for BFloat16. +// This version is still experimental as the 'Zvfbfmin' extension hasn't been +// ratified yet. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", + mayRaiseFPException = true in { +let RVVConstraint = WidenCvt in +defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>; +let Uses = [FRM] in +defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>; +} Index: llvm/test/CodeGen/RISCV/attributes.ll =================================================================== --- llvm/test/CodeGen/RISCV/attributes.ll +++ llvm/test/CodeGen/RISCV/attributes.ll @@ -66,6 +66,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s +; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -139,6 +140,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s +; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; CHECK: .attribute 4, 16 @@ -207,6 +209,7 @@ ; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0" ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2" +; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p2_zvl32b1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -279,6 +282,7 @@ ; RV64ZVKSH: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0" ; RV64ZICOND: .attribute 5, "rv64i2p1_zicond1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p2" +; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p2_zvl32b1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 Index: llvm/test/MC/RISCV/attribute-arch.s =================================================================== --- llvm/test/MC/RISCV/attribute-arch.s +++ llvm/test/MC/RISCV/attribute-arch.s @@ -239,3 +239,6 @@ .attribute arch, "rv32if_zfbfmin0p2" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2" + +.attribute arch, "rv32if_zvfbfmin0p2" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p2_zvl32b1p0" Index: llvm/test/MC/RISCV/rvv/zvfbfmin.s =================================================================== --- /dev/null +++ llvm/test/MC/RISCV/rvv/zvfbfmin.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4e,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 4e 48 +vfncvtbf16.f.f.w v8, v4, v0.t + +# CHECK-INST: vfncvtbf16.f.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 4e 4a +vfncvtbf16.f.f.w v8, v4 + +# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x46,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 46 48 +vfwcvtbf16.f.f.v v8, v4, v0.t + +# CHECK-INST: vfwcvtbf16.f.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x46,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 46 4a +vfwcvtbf16.f.f.v v8, v4