diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -68,6 +68,7 @@ // CHECK-NOT: __riscv_smaia {{.*$}} // CHECK-NOT: __riscv_ssaia {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} +// CHECK-NOT: __riscv_zvfbfmin {{.*$}} // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ // RUN: -o - | FileCheck %s @@ -683,3 +684,11 @@ // RUN: -march=rv64izfbfmin0p6 -x c -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s // CHECK-ZFBFMIN-EXT: __riscv_zfbfmin 6000{{$}} + +// RUN: %clang -target riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ifzvfbfmin0p6 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s +// RUN: %clang -target riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64ifzvfbfmin0p6 -x c -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZVFBFMIN-EXT %s +// CHECK-ZVFBFMIN-EXT: __riscv_zvfbfmin 6000{{$}} diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -216,6 +216,9 @@ ``experimental-ztso`` LLVM implements the `v0.1 proposed specification `__ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware. +``experimental-zvfbfmin`` + LLVM implements assembler support for the `0.6 draft specification `_. + ``experimental-zvfh`` LLVM implements `this draft text `__. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -181,7 +181,7 @@ * Zve32f is no longer allowed with Zfinx. Zve64d is no longer allowed with Zdinx. * Assembly support was added for the experimental Zfbfmin (scalar BF16 - conversions) extension. + conversions) and Zvfbfmin (vector BF16 conversions) extensions. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -149,6 +149,7 @@ {"zfa", RISCVExtensionVersion{0, 2}}, {"zfbfmin", RISCVExtensionVersion{0, 6}}, {"zicond", RISCVExtensionVersion{1, 0}}, + {"zvfbfmin", RISCVExtensionVersion{0, 6}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}}, @@ -937,6 +938,7 @@ static const char *ImpliedExtsZve64d[] = {"zve64f", "d"}; static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"}; static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"}; +static const char *ImpliedExtsZvfbfmin[] = {"zve32f"}; static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"}; static const char *ImpliedExtsZvkn[] = {"zvbb", "zvbc", "zvkned", "zvknhb", "zvkt"}; @@ -995,6 +997,7 @@ {{"zve64d"}, {ImpliedExtsZve64d}}, {{"zve64f"}, {ImpliedExtsZve64f}}, {{"zve64x"}, {ImpliedExtsZve64x}}, + {{"zvfbfmin"}, {ImpliedExtsZvfbfmin}}, {{"zvfh"}, {ImpliedExtsZvfh}}, {{"zvkn"}, {ImpliedExtsZvkn}}, {{"zvkng"}, {ImpliedExtsZvkng}}, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -451,6 +451,14 @@ def HasVInstructionsFullMultiply : Predicate<"Subtarget->hasVInstructionsFullMultiply()">; +def FeatureStdExtZvfbfmin + : SubtargetFeature<"experimental-zvfbfmin", "HasStdExtZvfbfmin", "true", + "'Zvbfmin' (Vector BF16 Converts)", + [FeatureStdExtZve32f]>; +def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">, + AssemblerPredicate<(all_of FeatureStdExtZvfbfmin), + "'Zvfbfmin' (Vector BF16 Converts)">; + def FeatureStdExtZvfh : SubtargetFeature<"experimental-zvfh", "HasStdExtZvfh", "true", "'Zvfh' (Vector Half-Precision Floating-Point)", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1776,5 +1776,6 @@ } } // Predicates = [HasVInstructionsI64, IsRV64] +include "RISCVInstrInfoZvfbf.td" include "RISCVInstrInfoZvk.td" include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td @@ -0,0 +1,26 @@ +//===-- RISCVInstrInfoZvfbf.td - 'Zvfbf*' instructions -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the RISC-V instructions from the standard 'Zvfbfmin' +// extension, providing vector conversion instructions for BFloat16. +// This version is still experimental as the 'Zvfbfmin' extension hasn't been +// ratified yet. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +let Predicates = [HasStdExtZvfbfmin], Constraints = "@earlyclobber $vd", + mayRaiseFPException = true in { +let RVVConstraint = WidenCvt in +defm VFWCVTBF16_F_F_V : VWCVTF_FV_VS2<"vfwcvtbf16.f.f.v", 0b010010, 0b01101>; +let Uses = [FRM] in +defm VFNCVTBF16_F_F_W : VNCVTF_FV_VS2<"vfncvtbf16.f.f.w", 0b010010, 0b11101>; +} diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -75,6 +75,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s +; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -157,6 +158,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s +; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; CHECK: .attribute 4, 16 @@ -234,6 +236,7 @@ ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0" ; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0" ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6" +; RV32ZVFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -315,6 +318,7 @@ ; RV64SMAIA: .attribute 5, "rv64i2p1_smaia1p0" ; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0" ; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin0p6" +; RV64ZVFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -266,3 +266,6 @@ .attribute arch, "rv32if_zfbfmin0p6" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6" + +.attribute arch, "rv32if_zvfbfmin0p6" +# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/rvv/zvfbfmin.s b/llvm/test/MC/RISCV/rvv/zvfbfmin.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rvv/zvfbfmin.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN +# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \ +# RUN: | FileCheck %s --check-prefix=CHECK-ERROR +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \ +# RUN: | FileCheck %s --check-prefix=CHECK-INST +# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \ +# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN + +# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x4e,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 4e 48 +vfncvtbf16.f.f.w v8, v4, v0.t + +# CHECK-INST: vfncvtbf16.f.f.w v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 4e 4a +vfncvtbf16.f.f.w v8, v4 + +# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t +# CHECK-ENCODING: [0x57,0x94,0x46,0x48] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 46 48 +vfwcvtbf16.f.f.v v8, v4, v0.t + +# CHECK-INST: vfwcvtbf16.f.f.v v8, v4 +# CHECK-ENCODING: [0x57,0x94,0x46,0x4a] +# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} +# CHECK-UNKNOWN: 57 94 46 4a +vfwcvtbf16.f.f.v v8, v4