diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -4627,3 +4627,321 @@
   %r = icmp ne i8 %a, 0
   ret i1 %r
 }
+
+define i1 @mul_or_positive_sgt_zero(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sgt_zero(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[ADD]], 0
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sgt i8 %add, 0
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_sgt_zero_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_sgt_zero_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[ADD]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sgt <2 x i8> %add, <i8 0, i8 0>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_sge_zero(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sge_zero(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[MUL1]], -1
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sge i8 %add, 0
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_sge_zero_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_sge_zero_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[MUL1]], <i8 -1, i8 -1>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sge <2 x i8> %add, <i8 0, i8 0>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_sge_postive(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sge_postive(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[ADD]], 23
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sge i8 %add, 24
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_sge_positive_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_sge_positive_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[ADD]], <i8 23, i8 23>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sge <2 x i8> %add, <i8 24, i8 24>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_sle_zero(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sle_zero(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ADD]], 1
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sle i8 %add, 0
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_sle_zero_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_sle_zero_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[ADD]], <i8 1, i8 1>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sle <2 x i8> %add, <i8 0, i8 0>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_slt_zero(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_slt_zero(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[MUL1]], 0
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp slt i8 %add, 0
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_slt_zero_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_slt_zero_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[MUL1]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp slt <2 x i8> %add, <i8 0, i8 0>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_slt_postive(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_slt_postive(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ADD]], 24
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp slt i8 %add, 24
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_slt_positive_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_slt_positive_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[ADD]], <i8 24, i8 24>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp slt <2 x i8> %add, <i8 24, i8 24>
+  ret <2 x i1> %cmp
+}
+
+; negative tests for icmp(X | LHS, C) --> icmp(X, 0)
+
+define i1 @mul_or_positive_sgt_neg(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sgt_neg(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[MUL1]], -1
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sgt i8 %add, -1
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_sgt_neg_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_sgt_neg_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[MUL1]], <i8 -1, i8 -1>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sgt <2 x i8> %add, <i8 -1, i8 -1>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_sge_neg(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sge_neg(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[ADD]], -2
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sge i8 %add, -1
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_sge_neg_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_sge_neg_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[ADD]], <i8 -2, i8 -2>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sge <2 x i8> %add, <i8 -1, i8 -1>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_small_sge_large(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_small_sge_large(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt i8 [[ADD]], 24
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sge i8 %add, 25
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_small_sge_large_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_small_sge_large_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp sgt <2 x i8> [[ADD]], <i8 24, i8 24>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sge <2 x i8> %add, <i8 25, i8 25>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_sle_neg(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_sle_neg(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[MUL1]], 0
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp sle i8 %add, -1
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or__sle_neg_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or__sle_neg_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[MUL1]], zeroinitializer
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp sle <2 x i8> %add, <i8 -1, i8 -1>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_positive_slt_neg(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_positive_slt_neg(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ADD]], -1
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp slt i8 %add, -1
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_postive_slt_neg_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_postive_slt_neg_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[ADD]], <i8 -1, i8 -1>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp slt <2 x i8> %add, <i8 -1, i8 -1>
+  ret <2 x i1> %cmp
+}
+
+define i1 @mul_or_small_slt_large(i8 %a, i8 %b) {
+; CHECK-LABEL: @mul_or_small_slt_large(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul i8 [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or i8 [[MUL1]], 24
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i8 [[ADD]], 25
+; CHECK-NEXT:    ret i1 [[CMP]]
+;
+  %mul1 = mul i8 %a, %b
+  %add = or i8 %mul1, 24
+  %cmp = icmp slt i8 %add, 25
+  ret i1 %cmp
+}
+
+define <2 x i1> @mul_or_small_slt_large_vec(<2 x i8> %a, <2 x i8> %b) {
+; CHECK-LABEL: @mul_or_small_slt_large_vec(
+; CHECK-NEXT:    [[MUL1:%.*]] = mul <2 x i8> [[A:%.*]], [[B:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = or <2 x i8> [[MUL1]], <i8 24, i8 24>
+; CHECK-NEXT:    [[CMP:%.*]] = icmp slt <2 x i8> [[ADD]], <i8 25, i8 25>
+; CHECK-NEXT:    ret <2 x i1> [[CMP]]
+;
+
+  %mul1 = mul <2 x i8> %a, %b
+  %add = or <2 x i8> %mul1, <i8 24, i8 24>
+  %cmp = icmp slt <2 x i8> %add, <i8 25, i8 25>
+  ret <2 x i1> %cmp
+}