Index: include/llvm/CodeGen/MachineRegisterInfo.h
===================================================================
--- include/llvm/CodeGen/MachineRegisterInfo.h
+++ include/llvm/CodeGen/MachineRegisterInfo.h
@@ -40,7 +40,7 @@
   };
 
 private:
-  const MachineFunction *MF;
+  MachineFunction *MF;
   Delegate *TheDelegate;
 
   /// IsSSA - True when the machine function is in SSA form and virtual
@@ -114,7 +114,7 @@
   MachineRegisterInfo(const MachineRegisterInfo&) = delete;
   void operator=(const MachineRegisterInfo&) = delete;
 public:
-  explicit MachineRegisterInfo(const MachineFunction *MF);
+  explicit MachineRegisterInfo(MachineFunction *MF);
 
   const TargetRegisterInfo *getTargetRegisterInfo() const {
     return MF->getSubtarget().getRegisterInfo();
@@ -539,6 +539,11 @@
   /// multiple definitions or no definition, return null.
   MachineInstr *getUniqueVRegDef(unsigned Reg) const;
 
+  /// Return the machine basic block that contains the definition of the
+  /// specified virtual register or null if none is found. This assumes that
+  /// the code is in SSA form, so there should only be one definition.
+  MachineBasicBlock *getVRegDefMBB(unsigned Reg) const;
+
   /// clearKillFlags - Iterate over all the uses of the given register and
   /// clear the kill flag from the MachineOperand. This function is used by
   /// optimization passes which extend register lifetimes and need only
Index: lib/CodeGen/LiveRangeCalc.cpp
===================================================================
--- lib/CodeGen/LiveRangeCalc.cpp
+++ lib/CodeGen/LiveRangeCalc.cpp
@@ -270,6 +270,17 @@
   for (unsigned i = 0; i != WorkList.size(); ++i) {
     MachineBasicBlock *MBB = MF->getBlockNumbered(WorkList[i]);
 
+    // For the entry block, check for the value being live-in to the function.
+    if (MBB == &MF->front() && MRI->isLiveIn(PhysReg)) {
+      assert(MBB->pred_empty());
+      SlotIndex Start = Indexes->getMBBStartIdx(&MF->front());
+      VNInfo *VNI = LR.getNextValue(Start, *Alloc);
+      if (TheVNI && TheVNI != VNI)
+        UniqueVNI = false;
+      TheVNI = VNI;
+      continue;
+    }
+
 #ifndef NDEBUG
     if (MBB->pred_empty()) {
       MBB->getParent()->verify();
Index: lib/CodeGen/LiveVariables.cpp
===================================================================
--- lib/CodeGen/LiveVariables.cpp
+++ lib/CodeGen/LiveVariables.cpp
@@ -130,7 +130,7 @@
 
 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
                                      MachineInstr *MI) {
-  assert(MRI->getVRegDef(reg) && "Register use before def!");
+  assert(MRI->getVRegDefMBB(reg) && "Register use before def!");
 
   unsigned BBNum = MBB->getNumber();
 
@@ -165,7 +165,7 @@
   // where there is a use in a PHI node that's a predecessor to the defining
   // block. We don't want to mark all predecessors as having the value "alive"
   // in this case.
-  if (MBB == MRI->getVRegDef(reg)->getParent()) return;
+  if (MBB == MRI->getVRegDefMBB(reg)) return;
 
   // Add a new kill entry for this basic block. If this virtual register is
   // already marked as alive in this basic block, that means it is alive in at
@@ -176,7 +176,7 @@
   // Update all dominating blocks to mark them as "known live".
   for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
          E = MBB->pred_end(); PI != E; ++PI)
-    MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDef(reg)->getParent(), *PI);
+    MarkVirtRegAliveInBlock(VRInfo, MRI->getVRegDefMBB(reg), *PI);
 }
 
 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) {
@@ -588,8 +588,7 @@
     for (SmallVectorImpl<unsigned>::iterator I = VarInfoVec.begin(),
            E = VarInfoVec.end(); I != E; ++I)
       // Mark it alive only in the block we are representing.
-      MarkVirtRegAliveInBlock(getVarInfo(*I),MRI->getVRegDef(*I)->getParent(),
-                              MBB);
+      MarkVirtRegAliveInBlock(getVarInfo(*I), MRI->getVRegDefMBB(*I), MBB);
   }
 
   // MachineCSE may CSE instructions which write to non-allocatable physical
@@ -724,8 +723,7 @@
     return true;
 
   // Registers defined in MBB cannot be live in.
-  const MachineInstr *Def = MRI.getVRegDef(Reg);
-  if (Def && Def->getParent() == &MBB)
+  if (MRI.getVRegDefMBB(Reg) == &MBB)
     return false;
 
  // Reg was not defined in MBB, was it killed here?
Index: lib/CodeGen/MachineCSE.cpp
===================================================================
--- lib/CodeGen/MachineCSE.cpp
+++ lib/CodeGen/MachineCSE.cpp
@@ -131,7 +131,7 @@
       continue;
     bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
     MachineInstr *DefMI = MRI->getVRegDef(Reg);
-    if (!DefMI->isCopy())
+    if (!DefMI || !DefMI->isCopy())
       continue;
     unsigned SrcReg = DefMI->getOperand(1).getReg();
     if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
Index: lib/CodeGen/MachineLICM.cpp
===================================================================
--- lib/CodeGen/MachineLICM.cpp
+++ lib/CodeGen/MachineLICM.cpp
@@ -991,12 +991,12 @@
     if (!MO.isUse())
       continue;
 
-    assert(MRI->getVRegDef(Reg) &&
+    assert(MRI->getVRegDefMBB(Reg) &&
            "Machine instr not mapped for this vreg?!");
 
     // If the loop contains the definition of an operand, then the instruction
     // isn't loop invariant.
-    if (CurLoop->contains(MRI->getVRegDef(Reg)))
+    if (CurLoop->contains(MRI->getVRegDefMBB(Reg)))
       return false;
   }
 
Index: lib/CodeGen/MachineRegisterInfo.cpp
===================================================================
--- lib/CodeGen/MachineRegisterInfo.cpp
+++ lib/CodeGen/MachineRegisterInfo.cpp
@@ -24,7 +24,7 @@
 // Pin the vtable to this file.
 void MachineRegisterInfo::Delegate::anchor() {}
 
-MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
+MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
   : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
     TracksSubRegLiveness(false) {
   VRegInfo.reserve(256);
@@ -322,6 +322,25 @@
   return &*I;
 }
 
+/// Return the machine basic block that contains the definition of the
+/// specified virtual register or null if none is found. This assumes that
+/// the code is in SSA form, so there should only be one definition.
+MachineBasicBlock *MachineRegisterInfo::getVRegDefMBB(unsigned Reg) const {
+  bool isLiveIn = false;
+  for (const auto &Pair : LiveIns)
+    if (Pair.first == Reg) {
+      isLiveIn = true;
+      break;
+    }
+
+  def_instr_iterator I = def_instr_begin(Reg);
+  assert(((!I.atEnd() && std::next(I).atEnd()) + isLiveIn <= 1) &&
+         "getVRegDefMBB assumes a single definition or no definition");
+  return !I.atEnd() ? I->getParent() :
+         isLiveIn ? &MF->front() :
+         nullptr;
+}
+
 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
   use_nodbg_iterator UI = use_nodbg_begin(RegNo);
   if (UI == use_nodbg_end())
@@ -389,7 +408,7 @@
         // Add the register to the entry block live-in set.
         EntryMBB->addLiveIn(LiveIns[i].first);
       }
-    } else {
+    } else if (TargetRegisterInfo::isPhysicalRegister(LiveIns[i].first)) {
       // Add the register to the entry block live-in set.
       EntryMBB->addLiveIn(LiveIns[i].first);
     }
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -1125,7 +1125,7 @@
         }
         if (Bad)
           report("Using an undefined physical register", MO, MONum);
-      } else if (MRI->def_empty(Reg)) {
+      } else if (MRI->def_empty(Reg) && !MRI->isLiveIn(Reg)) {
         report("Reading virtual register without a def", MO, MONum);
       } else {
         BBInfo &MInfo = MBBInfoMap[MI->getParent()];
Index: lib/CodeGen/PeepholeOptimizer.cpp
===================================================================
--- lib/CodeGen/PeepholeOptimizer.cpp
+++ lib/CodeGen/PeepholeOptimizer.cpp
@@ -1812,9 +1812,11 @@
     // definition.
     if (!TargetRegisterInfo::isPhysicalRegister(Reg) && OneRegSrc) {
       Def = MRI.getVRegDef(Reg);
-      DefIdx = MRI.def_begin(Reg).getOperandNo();
-      DefSubReg = Res.getSrcSubReg(0);
-      return Res;
+      if (Def) {
+        DefIdx = MRI.def_begin(Reg).getOperandNo();
+        DefSubReg = Res.getSrcSubReg(0);
+        return Res;
+      }
     }
   }
   // If we end up here, this means we will not be able to find another source
Index: lib/CodeGen/RegisterCoalescer.cpp
===================================================================
--- lib/CodeGen/RegisterCoalescer.cpp
+++ lib/CodeGen/RegisterCoalescer.cpp
@@ -1353,10 +1353,14 @@
       return false;
     }
   } else {
-    // When possible, let DstReg be the larger interval.
-    if (!CP.isPartial() && LIS->getInterval(CP.getSrcReg()).size() >
-                           LIS->getInterval(CP.getDstReg()).size())
-      CP.flip();
+    // When possible, let DstReg be the larger interval, or the interval for
+    // a live-in virtual register since it has no def.
+    if (!CP.isPartial()) {
+      LiveInterval &Src = LIS->getInterval(CP.getSrcReg());
+      LiveInterval &Dst = LIS->getInterval(CP.getDstReg());
+      if (Src.size() > Dst.size() || LIS->isLiveInToMBB(Src, &MF->front()))
+        CP.flip();
+    }
 
     DEBUG({
       dbgs() << "\tConsidering merging to "