diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp @@ -178,9 +178,9 @@ // Broadcast form. // Load size is word for TA map. Otherwise it is based on W-bit. if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { - assert(!(Desc.TSFlags & X86II::VEX_W) && "Unknown W-bit value!"); + assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); printwordmem(MI, CurOp--, OS); - } else if (Desc.TSFlags & X86II::VEX_W) { + } else if (Desc.TSFlags & X86II::REX_W) { printqwordmem(MI, CurOp--, OS); } else { printdwordmem(MI, CurOp--, OS); @@ -189,13 +189,13 @@ // Print the number of elements broadcasted. unsigned NumElts; if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16; else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8; else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4; if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { - assert(!(Desc.TSFlags & X86II::VEX_W) && "Unknown W-bit value!"); + assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); NumElts *= 2; } OS << "{1to" << NumElts << "}"; @@ -333,7 +333,7 @@ if (Desc.TSFlags & X86II::EVEX_B) { // Broadcast form. // Load size is based on W-bit as only D and Q are supported. - if (Desc.TSFlags & X86II::VEX_W) + if (Desc.TSFlags & X86II::REX_W) printqwordmem(MI, CurOp--, OS); else printdwordmem(MI, CurOp--, OS); @@ -341,11 +341,11 @@ // Print the number of elements broadcasted. unsigned NumElts; if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16; else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8; else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4; OS << "{1to" << NumElts << "}"; } else { if (Desc.TSFlags & X86II::EVEX_L2) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h --- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -924,15 +924,10 @@ // Opcode OpcodeShift = EncodingShift + 2, - /// VEX_W - Has a opcode specific functionality, but is used in the same - /// way as REX_W is for regular SSE instructions. - VEX_WShift = OpcodeShift + 8, - VEX_W = 1ULL << VEX_WShift, - /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 /// address instructions in SSE are represented as 3 address ones in AVX /// and the additional register is encoded in VEX_VVVV prefix. - VEX_4VShift = VEX_WShift + 1, + VEX_4VShift = OpcodeShift + 8, VEX_4V = 1ULL << VEX_4VShift, /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp @@ -168,9 +168,9 @@ // Broadcast form. // Load size is word for TA map. Otherwise it is based on W-bit. if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { - assert(!(Desc.TSFlags & X86II::VEX_W) && "Unknown W-bit value!"); + assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); printwordmem(MI, CurOp++, OS); - } else if (Desc.TSFlags & X86II::VEX_W) { + } else if (Desc.TSFlags & X86II::REX_W) { printqwordmem(MI, CurOp++, OS); } else { printdwordmem(MI, CurOp++, OS); @@ -179,13 +179,13 @@ // Print the number of elements broadcasted. unsigned NumElts; if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16; else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8; else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4; if ((Desc.TSFlags & X86II::OpMapMask) == X86II::TA) { - assert(!(Desc.TSFlags & X86II::VEX_W) && "Unknown W-bit value!"); + assert(!(Desc.TSFlags & X86II::REX_W) && "Unknown W-bit value!"); NumElts *= 2; } OS << "{1to" << NumElts << "}"; @@ -321,7 +321,7 @@ if (Desc.TSFlags & X86II::EVEX_B) { // Broadcast form. // Load size is based on W-bit as only D and Q are supported. - if (Desc.TSFlags & X86II::VEX_W) + if (Desc.TSFlags & X86II::REX_W) printqwordmem(MI, CurOp++, OS); else printdwordmem(MI, CurOp++, OS); @@ -329,11 +329,11 @@ // Print the number of elements broadcasted. unsigned NumElts; if (Desc.TSFlags & X86II::EVEX_L2) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 8 : 16; else if (Desc.TSFlags & X86II::VEX_L) - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 4 : 8; else - NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4; + NumElts = (Desc.TSFlags & X86II::REX_W) ? 2 : 4; OS << "{1to" << NumElts << "}"; } else { if (Desc.TSFlags & X86II::EVEX_L2) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -878,7 +878,7 @@ break; } - Prefix.setW(TSFlags & X86II::VEX_W); + Prefix.setW(TSFlags & X86II::REX_W); bool HasEVEX_K = TSFlags & X86II::EVEX_K; bool HasVEX_4V = TSFlags & X86II::VEX_4V; diff --git a/llvm/lib/Target/X86/X86InstrAVX512.td b/llvm/lib/Target/X86/X86InstrAVX512.td --- a/llvm/lib/Target/X86/X86InstrAVX512.td +++ b/llvm/lib/Target/X86/X86InstrAVX512.td @@ -628,7 +628,7 @@ defm NAME # "64x4Z" : vinsert_for_size, X86VectorVTInfo< 8, EltVT64, VR512>, - vinsert256_insert, sched>, VEX_W, EVEX_V512; + vinsert256_insert, sched>, REX_W, EVEX_V512; // Even with DQI we'd like to only use these instructions for masking. let Predicates = [HasVLX, HasDQI] in @@ -644,7 +644,7 @@ X86VectorVTInfo< 2, EltVT64, VR128X>, X86VectorVTInfo< 8, EltVT64, VR512>, null_frag, vinsert128_insert, sched>, - VEX_W, EVEX_V512; + REX_W, EVEX_V512; defm NAME # "32x8Z" : vinsert_for_size_split, @@ -923,7 +923,7 @@ X86VectorVTInfo< 8, EltVT64, VR512>, X86VectorVTInfo< 4, EltVT64, VR256X>, vextract256_extract, SchedRR, SchedMR>, - VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; + REX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; } let Predicates = [HasVLX] in defm NAME # "32x4Z256" : vextract_for_size, X86VectorVTInfo< 2, EltVT64, VR128X>, null_frag, vextract128_extract, SchedRR, SchedMR>, - VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; + REX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; defm NAME # "32x8Z" : vextract_for_size_split, X86VectorVTInfo< 8, EltVT32, VR256X>, @@ -1425,7 +1425,7 @@ defm VPBROADCASTDr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i32_info, X86VBroadcast, GR32, HasAVX512>; defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info, - X86VBroadcast, GR64, HasAVX512>, VEX_W; + X86VBroadcast, GR64, HasAVX512>, REX_W; multiclass avx512_int_broadcast_rm_vl opc, string OpcodeStr, AVX512VLVectorVTInfo _, Predicate prd, @@ -1520,10 +1520,10 @@ X86SubVBroadcastld128, v16f32_info, v4f32x_info>, EVEX_V512, EVEX_CD8<32, CD8VT4>; defm VBROADCASTI64X4 : avx512_subvec_broadcast_rm<0x5b, "vbroadcasti64x4", - X86SubVBroadcastld256, v8i64_info, v4i64x_info>, VEX_W, + X86SubVBroadcastld256, v8i64_info, v4i64x_info>, REX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; defm VBROADCASTF64X4 : avx512_subvec_broadcast_rm<0x1b, "vbroadcastf64x4", - X86SubVBroadcastld256, v8f64_info, v4f64x_info>, VEX_W, + X86SubVBroadcastld256, v8f64_info, v4f64x_info>, REX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; let Predicates = [HasAVX512] in { @@ -1664,13 +1664,13 @@ let Predicates = [HasDQI] in { defm VBROADCASTI64X2 : avx512_subvec_broadcast_rm_dq<0x5a, "vbroadcasti64x2", - X86SubVBroadcastld128, v8i64_info, v2i64x_info>, VEX_W, + X86SubVBroadcastld128, v8i64_info, v2i64x_info>, REX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; defm VBROADCASTI32X8 : avx512_subvec_broadcast_rm_dq<0x5b, "vbroadcasti32x8", X86SubVBroadcastld256, v16i32_info, v8i32x_info>, EVEX_V512, EVEX_CD8<32, CD8VT8>; defm VBROADCASTF64X2 : avx512_subvec_broadcast_rm_dq<0x1a, "vbroadcastf64x2", - X86SubVBroadcastld128, v8f64_info, v2f64x_info>, VEX_W, + X86SubVBroadcastld128, v8f64_info, v2f64x_info>, REX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>; defm VBROADCASTF32X8 : avx512_subvec_broadcast_rm_dq<0x1b, "vbroadcastf32x8", X86SubVBroadcastld256, v16f32_info, v8f32x_info>, @@ -1768,7 +1768,7 @@ defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", avx512vl_i32_info, VK16>; defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", - avx512vl_i64_info, VK8>, VEX_W; + avx512vl_i64_info, VK8>, REX_W; //===----------------------------------------------------------------------===// // -- VPERMI2 - 3 source operands form -- @@ -1847,17 +1847,17 @@ defm VPERMI2D : avx512_perm_i_sizes<0x76, "vpermi2d", WriteVarShuffle256, avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; defm VPERMI2Q : avx512_perm_i_sizes<0x76, "vpermi2q", WriteVarShuffle256, - avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + avx512vl_i64_info, avx512vl_i64_info>, REX_W, EVEX_CD8<64, CD8VF>; defm VPERMI2W : avx512_perm_i_sizes_bw<0x75, "vpermi2w", WriteVarShuffle256, avx512vl_i16_info, avx512vl_i16_info, HasBWI>, - VEX_W, EVEX_CD8<16, CD8VF>; + REX_W, EVEX_CD8<16, CD8VF>; defm VPERMI2B : avx512_perm_i_sizes_bw<0x75, "vpermi2b", WriteVarShuffle256, avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, EVEX_CD8<8, CD8VF>; defm VPERMI2PS : avx512_perm_i_sizes<0x77, "vpermi2ps", WriteFVarShuffle256, avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; defm VPERMI2PD : avx512_perm_i_sizes<0x77, "vpermi2pd", WriteFVarShuffle256, - avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + avx512vl_f64_info, avx512vl_i64_info>, REX_W, EVEX_CD8<64, CD8VF>; // Extra patterns to deal with extra bitcasts due to passthru and index being // different types on the fp versions. @@ -1965,17 +1965,17 @@ defm VPERMT2D : avx512_perm_t_sizes<0x7E, "vpermt2d", WriteVarShuffle256, avx512vl_i32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; defm VPERMT2Q : avx512_perm_t_sizes<0x7E, "vpermt2q", WriteVarShuffle256, - avx512vl_i64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + avx512vl_i64_info, avx512vl_i64_info>, REX_W, EVEX_CD8<64, CD8VF>; defm VPERMT2W : avx512_perm_t_sizes_bw<0x7D, "vpermt2w", WriteVarShuffle256, avx512vl_i16_info, avx512vl_i16_info, HasBWI>, - VEX_W, EVEX_CD8<16, CD8VF>; + REX_W, EVEX_CD8<16, CD8VF>; defm VPERMT2B : avx512_perm_t_sizes_bw<0x7D, "vpermt2b", WriteVarShuffle256, avx512vl_i8_info, avx512vl_i8_info, HasVBMI>, EVEX_CD8<8, CD8VF>; defm VPERMT2PS : avx512_perm_t_sizes<0x7F, "vpermt2ps", WriteFVarShuffle256, avx512vl_f32_info, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd", WriteFVarShuffle256, - avx512vl_f64_info, avx512vl_i64_info>, VEX_W, EVEX_CD8<64, CD8VF>; + avx512vl_f64_info, avx512vl_i64_info>, REX_W, EVEX_CD8<64, CD8VF>; //===----------------------------------------------------------------------===// // AVX-512 - BLEND using mask @@ -2083,15 +2083,15 @@ defm VBLENDMPS : blendmask_dq<0x65, "vblendmps", SchedWriteFVarBlend, avx512vl_f32_info>; defm VBLENDMPD : blendmask_dq<0x65, "vblendmpd", SchedWriteFVarBlend, - avx512vl_f64_info>, VEX_W; + avx512vl_f64_info>, REX_W; defm VPBLENDMD : blendmask_dq<0x64, "vpblendmd", SchedWriteVarBlend, avx512vl_i32_info>; defm VPBLENDMQ : blendmask_dq<0x64, "vpblendmq", SchedWriteVarBlend, - avx512vl_i64_info>, VEX_W; + avx512vl_i64_info>, REX_W; defm VPBLENDMB : blendmask_bw<0x66, "vpblendmb", SchedWriteVarBlend, avx512vl_i8_info>; defm VPBLENDMW : blendmask_bw<0x66, "vpblendmw", SchedWriteVarBlend, - avx512vl_i16_info>, VEX_W; + avx512vl_i16_info>, REX_W; //===----------------------------------------------------------------------===// // Compare Instructions @@ -2174,7 +2174,7 @@ let ExeDomain = SSEPackedDouble in defm VCMPSDZ : avx512_cmp_scalar, AVX512XDIi8Base, VEX_W; + SchedWriteFCmp.Scl>, AVX512XDIi8Base, REX_W; } let Predicates = [HasFP16], ExeDomain = SSEPackedSingle in defm VCMPSHZ : avx512_cmp_scalar, - T8PD, VEX_W, EVEX_CD8<64, CD8VF>; + T8PD, REX_W, EVEX_CD8<64, CD8VF>; defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", SchedWriteVecALU, avx512vl_i8_info, HasBWI>, @@ -2301,7 +2301,7 @@ defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", SchedWriteVecALU, avx512vl_i64_info, HasAVX512>, - T8PD, VEX_W, EVEX_CD8<64, CD8VF>; + T8PD, REX_W, EVEX_CD8<64, CD8VF>; } def X86pcmpm_imm : SDNodeXForm, - VEX_W, EVEX_CD8<16, CD8VF>; + REX_W, EVEX_CD8<16, CD8VF>; defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86pcmpum, X86pcmpum_su, SchedWriteVecALU, avx512vl_i16_info, HasBWI>, - VEX_W, EVEX_CD8<16, CD8VF>; + REX_W, EVEX_CD8<16, CD8VF>; defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86pcmpm, X86pcmpm_su, SchedWriteVecALU, avx512vl_i32_info, @@ -2499,10 +2499,10 @@ defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86pcmpm, X86pcmpm_su, SchedWriteVecALU, avx512vl_i64_info, - HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; + HasAVX512>, REX_W, EVEX_CD8<64, CD8VF>; defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86pcmpum, X86pcmpum_su, SchedWriteVecALU, avx512vl_i64_info, - HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>; + HasAVX512>, REX_W, EVEX_CD8<64, CD8VF>; def X86cmpm_su : PatFrag<(ops node:$src1, node:$src2, node:$cc), (X86cmpm node:$src1, node:$src2, node:$cc), [{ @@ -2656,7 +2656,7 @@ } defm VCMPPD : avx512_vcmp, - AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + AVX512PDIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, REX_W; defm VCMPPS : avx512_vcmp, AVX512PSIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; defm VCMPPH : avx512_vcmp, @@ -2835,13 +2835,13 @@ EVEX_CD8<32, CD8VF>, AVX512AIi8Base; defm PD : avx512_vector_fpclass_all, - EVEX_CD8<64, CD8VF>, AVX512AIi8Base, VEX_W; + EVEX_CD8<64, CD8VF>, AVX512AIi8Base, REX_W; defm SSZ : avx512_scalar_fpclass, VEX_LIG, EVEX_CD8<32, CD8VT1>, AVX512AIi8Base; defm SDZ : avx512_scalar_fpclass, VEX_LIG, - EVEX_CD8<64, CD8VT1>, AVX512AIi8Base, VEX_W; + EVEX_CD8<64, CD8VT1>, AVX512AIi8Base, REX_W; } defm VFPCLASS : avx512_fp_fpclass_all<"vfpclass", 0x66, 0x67, SchedWriteFCmp>, EVEX; @@ -2894,13 +2894,13 @@ let Predicates = [HasBWI] in { defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>, - VEX, PD, VEX_W; + VEX, PD, REX_W; defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>, VEX, XD; defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64mem>, - VEX, PS, VEX_W; + VEX, PS, REX_W; defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>, - VEX, XD, VEX_W; + VEX, XD, REX_W; } // GR from/to mask register @@ -3015,9 +3015,9 @@ defm W : avx512_mask_unop, VEX, PS; defm D : avx512_mask_unop, VEX, PD, VEX_W; + sched, HasBWI>, VEX, PD, REX_W; defm Q : avx512_mask_unop, VEX, PS, VEX_W; + sched, HasBWI>, VEX, PS, REX_W; } // TODO - do we need a X86SchedWriteWidths::KMASK type? @@ -3058,9 +3058,9 @@ defm W : avx512_mask_binop, VEX_4V, VEX_L, PS; defm D : avx512_mask_binop, VEX_4V, VEX_L, VEX_W, PD; + sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, REX_W, PD; defm Q : avx512_mask_binop, VEX_4V, VEX_L, VEX_W, PS; + sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, REX_W, PS; } // These nodes use 'vnot' instead of 'not' to support vectors. @@ -3124,7 +3124,7 @@ defm KUNPCKBW : avx512_mask_unpck<"bw", v16i1_info, v8i1_info, WriteShuffle, HasAVX512>, PD; defm KUNPCKWD : avx512_mask_unpck<"wd", v32i1_info, v16i1_info, WriteShuffle, HasBWI>, PS; -defm KUNPCKDQ : avx512_mask_unpck<"dq", v64i1_info, v32i1_info, WriteShuffle, HasBWI>, PS, VEX_W; +defm KUNPCKDQ : avx512_mask_unpck<"dq", v64i1_info, v32i1_info, WriteShuffle, HasBWI>, PS, REX_W; // Mask bit testing multiclass avx512_mask_testop opc, string OpcodeStr, RegisterClass KRC, @@ -3145,9 +3145,9 @@ defm W : avx512_mask_testop, VEX, PS; defm Q : avx512_mask_testop, - VEX, PS, VEX_W; + VEX, PS, REX_W; defm D : avx512_mask_testop, - VEX, PD, VEX_W; + VEX, PD, REX_W; } // TODO - do we need a X86SchedWriteWidths::KMASK type? @@ -3168,13 +3168,13 @@ multiclass avx512_mask_shiftop_w opc1, bits<8> opc2, string OpcodeStr, SDNode OpNode, X86FoldableSchedWrite sched> { defm W : avx512_mask_shiftop, VEX, TAPD, VEX_W; + sched>, VEX, TAPD, REX_W; let Predicates = [HasDQI] in defm B : avx512_mask_shiftop, VEX, TAPD; let Predicates = [HasBWI] in { defm Q : avx512_mask_shiftop, VEX, TAPD, VEX_W; + sched>, VEX, TAPD, REX_W; defm D : avx512_mask_shiftop, VEX, TAPD; } @@ -3626,7 +3626,7 @@ HasAVX512, SchedWriteFMoveLS, "VMOVAPD">, avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info, HasAVX512, SchedWriteFMoveLS, "VMOVAPD">, - PD, VEX_W, EVEX_CD8<64, CD8VF>; + PD, REX_W, EVEX_CD8<64, CD8VF>; defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512, SchedWriteFMoveLS, "VMOVUPS", 0, null_frag>, @@ -3638,7 +3638,7 @@ SchedWriteFMoveLS, "VMOVUPD", 0, null_frag>, avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512, SchedWriteFMoveLS, "VMOVUPD">, - PD, VEX_W, EVEX_CD8<64, CD8VF>; + PD, REX_W, EVEX_CD8<64, CD8VF>; defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info, HasAVX512, SchedWriteVecMoveLS, @@ -3654,7 +3654,7 @@ avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info, HasAVX512, SchedWriteVecMoveLS, "VMOVDQA">, - PD, VEX_W, EVEX_CD8<64, CD8VF>; + PD, REX_W, EVEX_CD8<64, CD8VF>; defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI, SchedWriteVecMoveLS, "VMOVDQU", 1>, @@ -3666,7 +3666,7 @@ SchedWriteVecMoveLS, "VMOVDQU", 1>, avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info, HasBWI, SchedWriteVecMoveLS, "VMOVDQU", 1>, - XD, VEX_W, EVEX_CD8<16, CD8VF>; + XD, REX_W, EVEX_CD8<16, CD8VF>; defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512, SchedWriteVecMoveLS, "VMOVDQU", 1, null_frag>, @@ -3678,7 +3678,7 @@ SchedWriteVecMoveLS, "VMOVDQU", 0, null_frag>, avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info, HasAVX512, SchedWriteVecMoveLS, "VMOVDQU">, - XS, VEX_W, EVEX_CD8<64, CD8VF>; + XS, REX_W, EVEX_CD8<64, CD8VF>; // Special instructions to help with spilling when we don't have VLX. We need // to load or store from a ZMM register instead. These are converted in @@ -4015,21 +4015,21 @@ "vmovq\t{$src, $dst|$dst, $src}", [(set VR128X:$dst, (v2i64 (scalar_to_vector GR64:$src)))]>, - EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; + EVEX, REX_W, Sched<[WriteVecMoveFromGpr]>; let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in def VMOV64toPQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i64mem:$src), "vmovq\t{$src, $dst|$dst, $src}", []>, - EVEX, VEX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>; + EVEX, REX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecLoad]>; let isCodeGenOnly = 1 in { def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64X:$dst), (ins GR64:$src), "vmovq\t{$src, $dst|$dst, $src}", [(set FR64X:$dst, (bitconvert GR64:$src))]>, - EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; + EVEX, REX_W, Sched<[WriteVecMoveFromGpr]>; def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64X:$src), "vmovq\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (bitconvert FR64X:$src))]>, - EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; + EVEX, REX_W, Sched<[WriteVecMoveFromGpr]>; } } // ExeDomain = SSEPackedInt @@ -4065,13 +4065,13 @@ "vmovq\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (extractelt (v2i64 VR128X:$src), (iPTR 0)))]>, - PD, EVEX, VEX_W, Sched<[WriteVecMoveToGpr]>, + PD, EVEX, REX_W, Sched<[WriteVecMoveToGpr]>, Requires<[HasAVX512]>; let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, VR128X:$src), "vmovq\t{$src, $dst|$dst, $src}", []>, PD, - EVEX, VEX_W, Sched<[WriteVecStore]>, + EVEX, REX_W, Sched<[WriteVecStore]>, Requires<[HasAVX512, In64BitMode]>; def VMOVPQI2QIZmr : I<0xD6, MRMDestMem, (outs), @@ -4079,14 +4079,14 @@ "vmovq\t{$src, $dst|$dst, $src}", [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), addr:$dst)]>, - EVEX, PD, VEX_W, EVEX_CD8<64, CD8VT1>, + EVEX, PD, REX_W, EVEX_CD8<64, CD8VT1>, Sched<[WriteVecStore]>, Requires<[HasAVX512]>; let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in def VMOVPQI2QIZrr : AVX512BI<0xD6, MRMDestReg, (outs VR128X:$dst), (ins VR128X:$src), "vmovq\t{$src, $dst|$dst, $src}", []>, - EVEX, VEX_W, Sched<[SchedWriteVecLogic.XMM]>; + EVEX, REX_W, Sched<[SchedWriteVecLogic.XMM]>; } // ExeDomain = SSEPackedInt def : InstAlias<"vmovq.s\t{$src, $dst|$dst, $src}", @@ -4115,7 +4115,7 @@ "vmovq\t{$src, $dst|$dst, $src}", [(set VR128X:$dst, (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, - EVEX, VEX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>; + EVEX, REX_W, EVEX_CD8<8, CD8VT8>, Sched<[WriteVecLoad]>; } // ExeDomain = SSEPackedInt // Allow "vmovd" but print "vmovq". @@ -4207,7 +4207,7 @@ VEX_LIG, XS, EVEX_CD8<32, CD8VT1>; defm VMOVSDZ : avx512_move_scalar<"vmovsd", X86Movsd, X86vzload64, f64x_info>, - VEX_LIG, XD, VEX_W, EVEX_CD8<64, CD8VT1>; + VEX_LIG, XD, REX_W, EVEX_CD8<64, CD8VT1>; defm VMOVSHZ : avx512_move_scalar<"vmovsh", X86Movsh, X86vzload16, f16x_info, HasFP16>, @@ -4586,7 +4586,7 @@ def VMOVSDZrr_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2), "vmovsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", - []>, XD, EVEX_4V, VEX_LIG, VEX_W, + []>, XD, EVEX_4V, VEX_LIG, REX_W, FoldGenData<"VMOVSDZrr">, Sched<[SchedWriteFShuffle.XMM]>; @@ -4597,7 +4597,7 @@ "vmovsd\t{$src2, $src1, $dst {${mask}}|"# "$dst {${mask}}, $src1, $src2}", []>, EVEX_K, XD, EVEX_4V, VEX_LIG, - VEX_W, FoldGenData<"VMOVSDZrrk">, + REX_W, FoldGenData<"VMOVSDZrrk">, Sched<[SchedWriteFShuffle.XMM]>; def VMOVSDZrrkz_REV: AVX512<0x11, MRMDestReg, (outs VR128X:$dst), @@ -4606,7 +4606,7 @@ "vmovsd\t{$src2, $src1, $dst {${mask}} {z}|"# "$dst {${mask}} {z}, $src1, $src2}", []>, EVEX_KZ, XD, EVEX_4V, VEX_LIG, - VEX_W, FoldGenData<"VMOVSDZrrkz">, + REX_W, FoldGenData<"VMOVSDZrrkz">, Sched<[SchedWriteFShuffle.XMM]>; } @@ -4744,7 +4744,7 @@ "vmovq\t{$src, $dst|$dst, $src}", [(set VR128X:$dst, (v2i64 (X86vzmovl (v2i64 VR128X:$src))))]>, - EVEX, VEX_W; + EVEX, REX_W; } let Predicates = [HasAVX512] in { @@ -4846,7 +4846,7 @@ defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", avx512vl_i64_info, SchedWriteVecMoveLSNT>, PD; defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", avx512vl_f64_info, - SchedWriteFMoveLSNT>, PD, VEX_W; + SchedWriteFMoveLSNT>, PD, REX_W; defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", avx512vl_f32_info, SchedWriteFMoveLSNT>, PS; @@ -4986,7 +4986,7 @@ bit IsCommutable = 0> { defm NAME : avx512_binop_rmb_vl, - VEX_W, EVEX_CD8<64, CD8VF>; + REX_W, EVEX_CD8<64, CD8VF>; } multiclass avx512_binop_rm_vl_d opc, string OpcodeStr, SDNode OpNode, @@ -5116,16 +5116,16 @@ defm NAME#Z : avx512_binop_rm2, - EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W; + EVEX_V512, EVEX_CD8<64, CD8VF>, REX_W; let Predicates = [HasVLX, prd] in { defm NAME#Z256 : avx512_binop_rm2, - EVEX_V256, EVEX_CD8<64, CD8VF>, VEX_W; + EVEX_V256, EVEX_CD8<64, CD8VF>, REX_W; defm NAME#Z128 : avx512_binop_rm2, - EVEX_V128, EVEX_CD8<64, CD8VF>, VEX_W; + EVEX_V128, EVEX_CD8<64, CD8VF>, REX_W; } } @@ -5709,7 +5709,7 @@ sched.PD.Scl, IsCommutable>, avx512_fp_scalar_round, - XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; + XD, REX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; let Predicates = [HasFP16] in defm SHZ : avx512_fp_scalar, @@ -5728,7 +5728,7 @@ defm SDZ : avx512_fp_scalar_sae, - XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; + XD, REX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; let Predicates = [HasFP16] in { defm SHZ : avx512_fp_scalar_sae, XD, - VEX_W, EVEX_4V, VEX_LIG, + REX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, SIMD_EXC; defm VMAXCSSZ : avx512_comutable_binop_s<0x5F, "vmaxss", f32x_info, X86fmaxc, @@ -5788,7 +5788,7 @@ defm VMAXCSDZ : avx512_comutable_binop_s<0x5F, "vmaxsd", f64x_info, X86fmaxc, SchedWriteFCmp.Scl, "VMAXCSD">, XD, - VEX_W, EVEX_4V, VEX_LIG, + REX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, SIMD_EXC; defm VMINCSHZ : avx512_comutable_binop_s<0x5D, "vminsh", f16x_info, X86fminc, @@ -5869,7 +5869,7 @@ sched.PS.ZMM, IsCommutable>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>; defm PDZ : avx512_fp_packed, EVEX_V512, PD, VEX_W, + sched.PD.ZMM, IsCommutable>, EVEX_V512, PD, REX_W, EVEX_CD8<64, CD8VF>; } @@ -5883,10 +5883,10 @@ EVEX_CD8<32, CD8VF>; defm PDZ128 : avx512_fp_packed, EVEX_V128, PD, VEX_W, + IsCommutable>, EVEX_V128, PD, REX_W, EVEX_CD8<64, CD8VF>; defm PDZ256 : avx512_fp_packed, EVEX_V256, PD, VEX_W, + sched.PD.YMM, IsCommutable>, EVEX_V256, PD, REX_W, EVEX_CD8<64, CD8VF>; } } @@ -5922,7 +5922,7 @@ EVEX_V512, PS, EVEX_CD8<32, CD8VF>; defm PDZ : avx512_fp_round_packed, - EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; + EVEX_V512, PD, REX_W,EVEX_CD8<64, CD8VF>; } let Uses = [MXCSR] in @@ -5938,7 +5938,7 @@ EVEX_V512, PS, EVEX_CD8<32, CD8VF>; defm PDZ : avx512_fp_sae_packed, - EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>; + EVEX_V512, PD, REX_W,EVEX_CD8<64, CD8VF>; } defm VADD : avx512_fp_binop_p<0x58, "vadd", any_fadd, fadd, HasAVX512, @@ -6039,7 +6039,7 @@ EVEX_V512, EVEX_CD8<32, CD8VF>, T8PD; defm PDZ : avx512_fp_scalef_p, avx512_fp_round_packed, - EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>, T8PD; + EVEX_V512, REX_W, EVEX_CD8<64, CD8VF>, T8PD; defm SSZ : avx512_fp_scalef_scalar, avx512_fp_scalar_round, @@ -6047,7 +6047,7 @@ defm SDZ : avx512_fp_scalef_scalar, avx512_fp_scalar_round, - EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, VEX_W, T8PD; + EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>, REX_W, T8PD; // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { @@ -6056,9 +6056,9 @@ defm PSZ256 : avx512_fp_scalef_p, EVEX_V256, EVEX_CD8<32, CD8VF>, T8PD; defm PDZ128 : avx512_fp_scalef_p, - EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>, T8PD; + EVEX_V128, REX_W, EVEX_CD8<64, CD8VF>, T8PD; defm PDZ256 : avx512_fp_scalef_p, - EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>, T8PD; + EVEX_V256, REX_W, EVEX_CD8<64, CD8VF>, T8PD; } let Predicates = [HasFP16, HasVLX] in { @@ -6127,23 +6127,23 @@ defm D : avx512_vptest_dq_sizes; defm Q : avx512_vptest_dq_sizes, VEX_W; + avx512vl_i64_info>, REX_W; } multiclass avx512_vptest_wb opc, string OpcodeStr, X86SchedWriteWidths sched> { let Predicates = [HasBWI] in { defm WZ: avx512_vptest, EVEX_V512, VEX_W; + v32i16_info>, EVEX_V512, REX_W; defm BZ: avx512_vptest, EVEX_V512; } let Predicates = [HasVLX, HasBWI] in { defm WZ256: avx512_vptest, EVEX_V256, VEX_W; + v16i16x_info>, EVEX_V256, REX_W; defm WZ128: avx512_vptest, EVEX_V128, VEX_W; + v8i16x_info>, EVEX_V128, REX_W; defm BZ256: avx512_vptest, EVEX_V256; defm BZ128: avx512_vptest; let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in defm Q : avx512_shift_sizes, VEX_W; + avx512vl_i64_info, HasAVX512>, REX_W; defm W : avx512_shift_sizes; } @@ -6288,7 +6288,7 @@ sched, avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; let notEVEX2VEXConvertible = NotEVEX2VEXConvertibleQ in defm Q: avx512_shift_rmi_sizes, EVEX_CD8<64, CD8VF>, VEX_W; + sched, avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, REX_W; } defm VPSRL : avx512_shift_rmi_dq<0x72, 0x73, MRM2r, MRM2m, "vpsrl", X86vsrli, @@ -6398,7 +6398,7 @@ defm D : avx512_var_shift_sizes; defm Q : avx512_var_shift_sizes, VEX_W; + avx512vl_i64_info>, REX_W; } // Use 512bit version to implement 128/256 bit in case NoVLX. @@ -6426,13 +6426,13 @@ SDNode OpNode, X86SchedWriteWidths sched> { let Predicates = [HasBWI] in defm WZ: avx512_var_shift, - EVEX_V512, VEX_W; + EVEX_V512, REX_W; let Predicates = [HasVLX, HasBWI] in { defm WZ256: avx512_var_shift, - EVEX_V256, VEX_W; + EVEX_V256, REX_W; defm WZ128: avx512_var_shift, - EVEX_V128, VEX_W; + EVEX_V128, REX_W; } } @@ -6601,25 +6601,25 @@ } defm VPERMW : avx512_vperm_bw<0x8D, "vpermw", HasBWI, X86VPermv, - WriteVarShuffle256, avx512vl_i16_info>, VEX_W; + WriteVarShuffle256, avx512vl_i16_info>, REX_W; defm VPERMB : avx512_vperm_bw<0x8D, "vpermb", HasVBMI, X86VPermv, WriteVarShuffle256, avx512vl_i8_info>; defm VPERMD : avx512_vperm_dq_sizes<0x36, "vpermd", X86VPermv, WriteVarShuffle256, avx512vl_i32_info>; defm VPERMQ : avx512_vperm_dq_sizes<0x36, "vpermq", X86VPermv, - WriteVarShuffle256, avx512vl_i64_info>, VEX_W; + WriteVarShuffle256, avx512vl_i64_info>, REX_W; defm VPERMPS : avx512_vperm_dq_sizes<0x16, "vpermps", X86VPermv, WriteFVarShuffle256, avx512vl_f32_info>; defm VPERMPD : avx512_vperm_dq_sizes<0x16, "vpermpd", X86VPermv, - WriteFVarShuffle256, avx512vl_f64_info>, VEX_W; + WriteFVarShuffle256, avx512vl_f64_info>, REX_W; defm VPERMQ : avx512_vpermi_dq_sizes<0x00, MRMSrcReg, MRMSrcMem, "vpermq", X86VPermi, WriteShuffle256, avx512vl_i64_info>, - EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; + EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, REX_W; defm VPERMPD : avx512_vpermi_dq_sizes<0x01, MRMSrcReg, MRMSrcMem, "vpermpd", X86VPermi, WriteFShuffle256, avx512vl_f64_info>, - EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, VEX_W; + EVEX, AVX512AIi8Base, EVEX_CD8<64, CD8VF>, REX_W; //===----------------------------------------------------------------------===// // AVX-512 - VPERMIL @@ -6761,11 +6761,11 @@ defm VMOVHPSZ128 : avx512_mov_hilo_packed<0x16, "vmovhps", null_frag, v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS; defm VMOVHPDZ128 : avx512_mov_hilo_packed<0x16, "vmovhpd", X86Unpckl, - v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W; + v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, REX_W; defm VMOVLPSZ128 : avx512_mov_hilo_packed<0x12, "vmovlps", null_frag, v4f32x_info>, EVEX_CD8<32, CD8VT2>, PS; defm VMOVLPDZ128 : avx512_mov_hilo_packed<0x12, "vmovlpd", X86Movsd, - v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, VEX_W; + v2f64x_info>, EVEX_CD8<64, CD8VT1>, PD, REX_W; let Predicates = [HasAVX512] in { // VMOVHPD patterns @@ -6789,7 +6789,7 @@ [(store (f64 (extractelt (v2f64 (X86Unpckh VR128X:$src, VR128X:$src)), (iPTR 0))), addr:$dst)]>, - EVEX, EVEX_CD8<64, CD8VT1>, VEX_W; + EVEX, EVEX_CD8<64, CD8VT1>, REX_W; let mayStore = 1, hasSideEffects = 0 in def VMOVLPSZ128mr : AVX512PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128X:$src), @@ -6800,7 +6800,7 @@ "vmovlpd\t{$src, $dst|$dst, $src}", [(store (f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))), addr:$dst)]>, - EVEX, EVEX_CD8<64, CD8VT1>, VEX_W; + EVEX, EVEX_CD8<64, CD8VT1>, REX_W; } // SchedRW let Predicates = [HasAVX512] in { @@ -6890,7 +6890,7 @@ avx512vl_f32_info>, T8PD; defm PD : avx512_fma3p_213_common, T8PD, VEX_W; + avx512vl_f64_info>, T8PD, REX_W; } defm VFMADD213 : avx512_fma3p_213_f<0xA8, "vfmadd213", any_fma, @@ -6985,7 +6985,7 @@ avx512vl_f32_info>, T8PD; defm PD : avx512_fma3p_231_common, T8PD, VEX_W; + avx512vl_f64_info>, T8PD, REX_W; } defm VFMADD231 : avx512_fma3p_231_f<0xB8, "vfmadd231", any_fma, @@ -7081,7 +7081,7 @@ avx512vl_f32_info>, T8PD; defm PD : avx512_fma3p_132_common, T8PD, VEX_W; + avx512vl_f64_info>, T8PD, REX_W; } defm VFMADD132 : avx512_fma3p_132_f<0x98, "vfmadd132", any_fma, @@ -7183,7 +7183,7 @@ EVEX_CD8<32, CD8VT1>, VEX_LIG, T8PD; defm NAME : avx512_fma3s_all, - EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W, T8PD; + EVEX_CD8<64, CD8VT1>, VEX_LIG, REX_W, T8PD; } let Predicates = [HasFP16] in { defm NAME : avx512_fma3s_all, - VEX_W; + REX_W; defm VPMADD52HUQ : avx512_pmadd52_common<0xb5, "vpmadd52huq", x86vpmadd52h, SchedWriteVecIMul, avx512vl_i64_info>, - VEX_W; + REX_W; //===----------------------------------------------------------------------===// // AVX-512 Scalar convert from sign integer to float/double @@ -7560,14 +7560,14 @@ defm VCVTSI642SSZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SS, GR64, v4f32x_info, i64mem, loadi64, "cvtsi2ss", "q">, - XS, VEX_W, EVEX_CD8<64, CD8VT1>; + XS, REX_W, EVEX_CD8<64, CD8VT1>; defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, null_frag, WriteCvtI2SD, GR32, v2f64x_info, i32mem, loadi32, "cvtsi2sd", "l", [], 0>, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCVTSI642SDZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SD, GR64, v2f64x_info, i64mem, loadi64, "cvtsi2sd", "q">, - XD, VEX_W, EVEX_CD8<64, CD8VT1>; + XD, REX_W, EVEX_CD8<64, CD8VT1>; def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", (VCVTSI2SSZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">; @@ -7599,14 +7599,14 @@ defm VCVTUSI642SSZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SS, GR64, v4f32x_info, i64mem, loadi64, "cvtusi2ss", "q">, - XS, VEX_W, EVEX_CD8<64, CD8VT1>; + XS, REX_W, EVEX_CD8<64, CD8VT1>; defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, null_frag, WriteCvtI2SD, GR32, v2f64x_info, i32mem, loadi32, "cvtusi2sd", "l", [], 0>, XD, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCVTUSI642SDZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SD, GR64, v2f64x_info, i64mem, loadi64, "cvtusi2sd", "q">, - XD, VEX_W, EVEX_CD8<64, CD8VT1>; + XD, REX_W, EVEX_CD8<64, CD8VT1>; def : InstAlias<"vcvtusi2ss\t{$src, $src1, $dst|$dst, $src1, $src}", (VCVTUSI2SSZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">; @@ -7674,25 +7674,25 @@ XS, EVEX_CD8<32, CD8VT1>; defm VCVTSS2SI64Z: avx512_cvt_s_int_round<0x2D, f32x_info, i64x_info, X86cvts2si, X86cvts2siRnd, WriteCvtSS2I, "cvtss2si", "{q}">, - XS, VEX_W, EVEX_CD8<32, CD8VT1>; + XS, REX_W, EVEX_CD8<32, CD8VT1>; defm VCVTSS2USIZ: avx512_cvt_s_int_round<0x79, f32x_info, i32x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSS2I, "cvtss2usi", "{l}">, XS, EVEX_CD8<32, CD8VT1>; defm VCVTSS2USI64Z: avx512_cvt_s_int_round<0x79, f32x_info, i64x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSS2I, "cvtss2usi", "{q}">, - XS, VEX_W, EVEX_CD8<32, CD8VT1>; + XS, REX_W, EVEX_CD8<32, CD8VT1>; defm VCVTSD2SIZ: avx512_cvt_s_int_round<0x2D, f64x_info, i32x_info, X86cvts2si, X86cvts2siRnd, WriteCvtSD2I, "cvtsd2si", "{l}">, XD, EVEX_CD8<64, CD8VT1>; defm VCVTSD2SI64Z: avx512_cvt_s_int_round<0x2D, f64x_info, i64x_info, X86cvts2si, X86cvts2siRnd, WriteCvtSD2I, "cvtsd2si", "{q}">, - XD, VEX_W, EVEX_CD8<64, CD8VT1>; + XD, REX_W, EVEX_CD8<64, CD8VT1>; defm VCVTSD2USIZ: avx512_cvt_s_int_round<0x79, f64x_info, i32x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSD2I, "cvtsd2usi", "{l}">, XD, EVEX_CD8<64, CD8VT1>; defm VCVTSD2USI64Z: avx512_cvt_s_int_round<0x79, f64x_info, i64x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSD2I, "cvtsd2usi", "{q}">, - XD, VEX_W, EVEX_CD8<64, CD8VT1>; + XD, REX_W, EVEX_CD8<64, CD8VT1>; multiclass avx512_cvt_s opc, string asm, X86VectorVTInfo SrcVT, X86VectorVTInfo DstVT, SDNode OpNode, @@ -7714,11 +7714,11 @@ defm VCVTSS2SIZ: avx512_cvt_s<0x2D, "vcvtss2si", f32x_info, i32x_info, lrint, WriteCvtSS2I>, XS, EVEX_CD8<32, CD8VT1>; defm VCVTSS2SI64Z: avx512_cvt_s<0x2D, "vcvtss2si", f32x_info, i64x_info, - llrint, WriteCvtSS2I>, VEX_W, XS, EVEX_CD8<32, CD8VT1>; + llrint, WriteCvtSS2I>, REX_W, XS, EVEX_CD8<32, CD8VT1>; defm VCVTSD2SIZ: avx512_cvt_s<0x2D, "vcvtsd2si", f64x_info, i32x_info, lrint, WriteCvtSD2I>, XD, EVEX_CD8<64, CD8VT1>; defm VCVTSD2SI64Z: avx512_cvt_s<0x2D, "vcvtsd2si", f64x_info, i64x_info, - llrint, WriteCvtSD2I>, VEX_W, XD, EVEX_CD8<64, CD8VT1>; + llrint, WriteCvtSD2I>, REX_W, XD, EVEX_CD8<64, CD8VT1>; let Predicates = [HasAVX512] in { def : Pat<(i64 (lrint FR32:$src)), (VCVTSS2SI64Zrr FR32:$src)>; @@ -7861,26 +7861,26 @@ "{l}">, XS, EVEX_CD8<32, CD8VT1>; defm VCVTTSS2SI64Z: avx512_cvt_s_all<0x2C, "vcvttss2si", f32x_info, i64x_info, any_fp_to_sint, X86cvtts2Int, X86cvtts2IntSAE, WriteCvtSS2I, - "{q}">, VEX_W, XS, EVEX_CD8<32, CD8VT1>; + "{q}">, REX_W, XS, EVEX_CD8<32, CD8VT1>; defm VCVTTSD2SIZ: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i32x_info, any_fp_to_sint, X86cvtts2Int, X86cvtts2IntSAE, WriteCvtSD2I, "{l}">, XD, EVEX_CD8<64, CD8VT1>; defm VCVTTSD2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsd2si", f64x_info, i64x_info, any_fp_to_sint, X86cvtts2Int, X86cvtts2IntSAE, WriteCvtSD2I, - "{q}">, VEX_W, XD, EVEX_CD8<64, CD8VT1>; + "{q}">, REX_W, XD, EVEX_CD8<64, CD8VT1>; defm VCVTTSS2USIZ: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i32x_info, any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I, "{l}">, XS, EVEX_CD8<32, CD8VT1>; defm VCVTTSS2USI64Z: avx512_cvt_s_all<0x78, "vcvttss2usi", f32x_info, i64x_info, any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I, - "{q}">, XS,VEX_W, EVEX_CD8<32, CD8VT1>; + "{q}">, XS,REX_W, EVEX_CD8<32, CD8VT1>; defm VCVTTSD2USIZ: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i32x_info, any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSD2I, "{l}">, XD, EVEX_CD8<64, CD8VT1>; defm VCVTTSD2USI64Z: avx512_cvt_s_all<0x78, "vcvttsd2usi", f64x_info, i64x_info, any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSD2I, - "{q}">, XD, VEX_W, EVEX_CD8<64, CD8VT1>; + "{q}">, XD, REX_W, EVEX_CD8<64, CD8VT1>; //===----------------------------------------------------------------------===// // AVX-512 Convert form float to double and back @@ -7968,13 +7968,13 @@ } defm VCVTSD2SS : avx512_cvt_fp_scalar_trunc<0x5A, "vcvtsd2ss", X86frounds, X86froundsRnd, WriteCvtSD2SS, f64x_info, - f32x_info>, XD, VEX_W; + f32x_info>, XD, REX_W; defm VCVTSS2SD : avx512_cvt_fp_scalar_extend<0x5A, "vcvtss2sd", X86fpexts, X86fpextsSAE, WriteCvtSS2SD, f32x_info, f64x_info>, XS; defm VCVTSD2SH : avx512_cvt_fp_scalar_trunc<0x5A, "vcvtsd2sh", X86frounds, X86froundsRnd, WriteCvtSD2SS, f64x_info, - f16x_info, HasFP16>, T_MAP5XD, VEX_W; + f16x_info, HasFP16>, T_MAP5XD, REX_W; defm VCVTSH2SD : avx512_cvt_fp_scalar_extend<0x5A, "vcvtsh2sd", X86fpexts, X86fpextsSAE, WriteCvtSS2SD, f16x_info, f64x_info, HasFP16>, T_MAP5XS; @@ -8245,7 +8245,7 @@ defm VCVTPD2PS : avx512_cvt_trunc<0x5A, "vcvtpd2ps", avx512vl_f32_info, avx512vl_f64_info, SchedWriteCvtPD2PS>, - VEX_W, PD, EVEX_CD8<64, CD8VF>; + REX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTPS2PD : avx512_cvt_extend<0x5A, "vcvtps2pd", avx512vl_f64_info, avx512vl_f32_info, SchedWriteCvtPS2PD>, PS, EVEX_CD8<32, CD8VH>; @@ -8362,7 +8362,7 @@ avx512vl_f16_info, SchedWriteCvtPS2PD, HasFP16>, T_MAP6PD, EVEX_CD8<16, CD8VH>; defm VCVTPD2PH : avx512_cvtpd2ph<0x5A, "vcvtpd2ph", SchedWriteCvtPD2PS>, - VEX_W, T_MAP5PD, EVEX_CD8<64, CD8VF>; + REX_W, T_MAP5PD, EVEX_CD8<64, CD8VF>; defm VCVTPH2PD : avx512_cvtph2pd<0x5A, "vcvtph2pd", SchedWriteCvtPS2PD>, T_MAP5PS, EVEX_CD8<16, CD8VQ>; @@ -8858,7 +8858,7 @@ defm VCVTTPD2DQ : avx512_cvttpd2dq<0xE6, "vcvttpd2dq", X86any_cvttp2si, X86cvttp2si, X86cvttp2siSAE, SchedWriteCvtPD2DQ>, - PD, VEX_W, EVEX_CD8<64, CD8VF>; + PD, REX_W, EVEX_CD8<64, CD8VF>; defm VCVTTPS2UDQ : avx512_cvttps2dq<0x78, "vcvttps2udq", X86any_cvttp2ui, X86cvttp2ui, X86cvttp2uiSAE, @@ -8867,7 +8867,7 @@ defm VCVTTPD2UDQ : avx512_cvttpd2dq<0x78, "vcvttpd2udq", X86any_cvttp2ui, X86cvttp2ui, X86cvttp2uiSAE, SchedWriteCvtPD2DQ>, - PS, VEX_W, EVEX_CD8<64, CD8VF>; + PS, REX_W, EVEX_CD8<64, CD8VF>; defm VCVTUDQ2PD : avx512_cvtdq2pd<0x7A, "vcvtudq2pd", any_uint_to_fp, uint_to_fp, X86any_VUintToFP, X86VUintToFP, @@ -8883,18 +8883,18 @@ defm VCVTPD2DQ : avx512_cvtpd2dq<0xE6, "vcvtpd2dq", X86cvtp2Int, X86cvtp2Int, X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, XD, - VEX_W, EVEX_CD8<64, CD8VF>; + REX_W, EVEX_CD8<64, CD8VF>; defm VCVTPS2UDQ : avx512_cvtps2dq<0x79, "vcvtps2udq", X86cvtp2UInt, X86cvtp2UInt, X86cvtp2UIntRnd, SchedWriteCvtPS2DQ>, PS, EVEX_CD8<32, CD8VF>; defm VCVTPD2UDQ : avx512_cvtpd2dq<0x79, "vcvtpd2udq", X86cvtp2UInt, X86cvtp2UInt, - X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, + X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, REX_W, PS, EVEX_CD8<64, CD8VF>; defm VCVTPD2QQ : avx512_cvtpd2qq<0x7B, "vcvtpd2qq", X86cvtp2Int, X86cvtp2Int, - X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, VEX_W, + X86cvtp2IntRnd, SchedWriteCvtPD2DQ>, REX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTPS2QQ : avx512_cvtps2qq<0x7B, "vcvtps2qq", X86cvtp2Int, X86cvtp2Int, @@ -8902,7 +8902,7 @@ EVEX_CD8<32, CD8VH>; defm VCVTPD2UQQ : avx512_cvtpd2qq<0x79, "vcvtpd2uqq", X86cvtp2UInt, X86cvtp2UInt, - X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, VEX_W, + X86cvtp2UIntRnd, SchedWriteCvtPD2DQ>, REX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTPS2UQQ : avx512_cvtps2qq<0x79, "vcvtps2uqq", X86cvtp2UInt, X86cvtp2UInt, @@ -8911,7 +8911,7 @@ defm VCVTTPD2QQ : avx512_cvttpd2qq<0x7A, "vcvttpd2qq", X86any_cvttp2si, X86cvttp2si, X86cvttp2siSAE, - SchedWriteCvtPD2DQ>, VEX_W, + SchedWriteCvtPD2DQ>, REX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTTPS2QQ : avx512_cvttps2qq<0x7A, "vcvttps2qq", X86any_cvttp2si, @@ -8921,7 +8921,7 @@ defm VCVTTPD2UQQ : avx512_cvttpd2qq<0x78, "vcvttpd2uqq", X86any_cvttp2ui, X86cvttp2ui, X86cvttp2uiSAE, - SchedWriteCvtPD2DQ>, VEX_W, + SchedWriteCvtPD2DQ>, REX_W, PD, EVEX_CD8<64, CD8VF>; defm VCVTTPS2UQQ : avx512_cvttps2qq<0x78, "vcvttps2uqq", X86any_cvttp2ui, @@ -8931,11 +8931,11 @@ defm VCVTQQ2PD : avx512_cvtqq2pd<0xE6, "vcvtqq2pd", any_sint_to_fp, sint_to_fp, X86VSintToFpRnd, - SchedWriteCvtDQ2PD>, VEX_W, XS, EVEX_CD8<64, CD8VF>; + SchedWriteCvtDQ2PD>, REX_W, XS, EVEX_CD8<64, CD8VF>; defm VCVTUQQ2PD : avx512_cvtqq2pd<0x7A, "vcvtuqq2pd", any_uint_to_fp, uint_to_fp, X86VUintToFpRnd, SchedWriteCvtDQ2PD>, - VEX_W, XS, EVEX_CD8<64, CD8VF>; + REX_W, XS, EVEX_CD8<64, CD8VF>; defm VCVTDQ2PH : avx512_cvtqq2ps_dq2ph<0x5B, "vcvtdq2ph", any_sint_to_fp, sint_to_fp, X86any_VSintToFP, X86VMSintToFP, @@ -8952,13 +8952,13 @@ defm VCVTQQ2PS : avx512_cvtqq2ps_dq2ph<0x5B, "vcvtqq2ps", any_sint_to_fp, sint_to_fp, X86any_VSintToFP, X86VMSintToFP, X86VSintToFpRnd, avx512vl_f32_info, avx512vl_i64_info, - SchedWriteCvtDQ2PS>, VEX_W, PS, + SchedWriteCvtDQ2PS>, REX_W, PS, EVEX_CD8<64, CD8VF>; defm VCVTUQQ2PS : avx512_cvtqq2ps_dq2ph<0x7A, "vcvtuqq2ps", any_uint_to_fp, uint_to_fp, X86any_VUintToFP, X86VMUintToFP, X86VUintToFpRnd, avx512vl_f32_info, avx512vl_i64_info, - SchedWriteCvtDQ2PS>, VEX_W, XD, + SchedWriteCvtDQ2PS>, REX_W, XD, EVEX_CD8<64, CD8VF>; let Predicates = [HasVLX] in { @@ -9308,11 +9308,11 @@ defm VUCOMISSZ : avx512_ord_cmp_sae<0x2E, v4f32x_info, "vucomiss", SSEPackedSingle>, AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>; defm VUCOMISDZ : avx512_ord_cmp_sae<0x2E, v2f64x_info, "vucomisd", SSEPackedDouble>, - AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>; + AVX512PDIi8Base, REX_W, EVEX_CD8<64, CD8VT1>; defm VCOMISSZ : avx512_ord_cmp_sae<0x2F, v4f32x_info, "vcomiss", SSEPackedSingle>, AVX512PSIi8Base, EVEX_CD8<32, CD8VT1>; defm VCOMISDZ : avx512_ord_cmp_sae<0x2F, v2f64x_info, "vcomisd", SSEPackedDouble>, - AVX512PDIi8Base, VEX_W, EVEX_CD8<64, CD8VT1>; + AVX512PDIi8Base, REX_W, EVEX_CD8<64, CD8VT1>; } let Defs = [EFLAGS], Predicates = [HasAVX512] in { @@ -9321,27 +9321,27 @@ EVEX_CD8<32, CD8VT1>; defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86any_fcmp, f64, f64mem, loadf64, "ucomisd", SSEPackedDouble>, PD, EVEX, - VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; defm VCOMISSZ : sse12_ord_cmp<0x2F, FR32X, X86strict_fcmps, f32, f32mem, loadf32, "comiss", SSEPackedSingle>, PS, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCOMISDZ : sse12_ord_cmp<0x2F, FR64X, X86strict_fcmps, f64, f64mem, loadf64, "comisd", SSEPackedDouble>, PD, EVEX, - VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; let isCodeGenOnly = 1 in { defm VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem, sse_load_f32, "ucomiss", SSEPackedSingle>, PS, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem, sse_load_f64, "ucomisd", SSEPackedDouble>, PD, EVEX, - VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; defm VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem, sse_load_f32, "comiss", SSEPackedSingle>, PS, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>; defm VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem, sse_load_f64, "comisd", SSEPackedDouble>, PD, EVEX, - VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>; + VEX_LIG, REX_W, EVEX_CD8<64, CD8VT1>; } } @@ -9399,13 +9399,13 @@ f32x_info>, EVEX_CD8<32, CD8VT1>, T8PD; defm VRCP14SDZ : avx512_fp14_s<0x4D, "vrcp14sd", X86rcp14s, SchedWriteFRcp.Scl, - f64x_info>, VEX_W, EVEX_CD8<64, CD8VT1>, + f64x_info>, REX_W, EVEX_CD8<64, CD8VT1>, T8PD; defm VRSQRT14SSZ : avx512_fp14_s<0x4F, "vrsqrt14ss", X86rsqrt14s, SchedWriteFRsqrt.Scl, f32x_info>, EVEX_CD8<32, CD8VT1>, T8PD; defm VRSQRT14SDZ : avx512_fp14_s<0x4F, "vrsqrt14sd", X86rsqrt14s, - SchedWriteFRsqrt.Scl, f64x_info>, VEX_W, + SchedWriteFRsqrt.Scl, f64x_info>, REX_W, EVEX_CD8<64, CD8VT1>, T8PD; } @@ -9437,7 +9437,7 @@ defm 14PSZ : avx512_fp14_p, EVEX_V512, EVEX_CD8<32, CD8VF>; defm 14PDZ : avx512_fp14_p, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; + v8f64_info>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VF>; } let Predicates = [HasFP16] in defm PHZ : avx512_fp14_p; defm 14PDZ128 : avx512_fp14_p, - EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>; + EVEX_V128, REX_W, EVEX_CD8<64, CD8VF>; defm 14PDZ256 : avx512_fp14_p, - EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>; + EVEX_V256, REX_W, EVEX_CD8<64, CD8VF>; } let Predicates = [HasFP16, HasVLX] in { defm PHZ128 : avx512_fp14_p, EVEX_CD8<32, CD8VT1>, VEX_LIG, T8PD, EVEX_4V; defm SDZ : avx512_fp28_s, EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W, T8PD, EVEX_4V; + sched>, EVEX_CD8<64, CD8VT1>, VEX_LIG, REX_W, T8PD, EVEX_4V; } multiclass avx512_vgetexpsh opc, string OpcodeStr, SDNode OpNode, @@ -9563,7 +9563,7 @@ T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>; defm PDZ : avx512_fp28_p, avx512_fp28_p_sae, - T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>; + T8PD, EVEX_V512, REX_W, EVEX_CD8<64, CD8VF>; } multiclass avx512_fp_unaryop_packed opc, string OpcodeStr, @@ -9578,10 +9578,10 @@ EVEX_V256, T8PD, EVEX_CD8<32, CD8VF>; defm PDZ128 : avx512_fp28_p, - EVEX_V128, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; + EVEX_V128, REX_W, T8PD, EVEX_CD8<64, CD8VF>; defm PDZ256 : avx512_fp28_p, - EVEX_V256, VEX_W, T8PD, EVEX_CD8<64, CD8VF>; + EVEX_V256, REX_W, T8PD, EVEX_CD8<64, CD8VF>; } } @@ -9664,7 +9664,7 @@ EVEX_V512, PS, EVEX_CD8<32, CD8VF>; defm PDZ : avx512_sqrt_packed, - EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; + EVEX_V512, REX_W, PD, EVEX_CD8<64, CD8VF>; // Define only if AVX512VL feature is present. let Predicates = [HasVLX] in { defm PSZ128 : avx512_sqrt_packed; defm PDZ128 : avx512_sqrt_packed, - EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>; + EVEX_V128, REX_W, PD, EVEX_CD8<64, CD8VF>; defm PDZ256 : avx512_sqrt_packed, - EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>; + EVEX_V256, REX_W, PD, EVEX_CD8<64, CD8VF>; } } @@ -9694,7 +9694,7 @@ EVEX_V512, PS, EVEX_CD8<32, CD8VF>; defm PDZ : avx512_sqrt_packed_round, - EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>; + EVEX_V512, REX_W, PD, EVEX_CD8<64, CD8VF>; } multiclass avx512_sqrt_scalar opc, string OpcodeStr, X86FoldableSchedWrite sched, @@ -9754,7 +9754,7 @@ defm SSZ : avx512_sqrt_scalar, EVEX_CD8<32, CD8VT1>, EVEX_4V, XS; defm SDZ : avx512_sqrt_scalar, - EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, VEX_W; + EVEX_CD8<64, CD8VT1>, EVEX_4V, XD, REX_W; } defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, @@ -9828,7 +9828,7 @@ defm VRNDSCALESDZ : avx512_rndscale_scalar<0x0B, "vrndscalesd", SchedWriteFRnd.Scl, f64x_info>, - VEX_W, AVX512AIi8Base, EVEX_4V, VEX_LIG, + REX_W, AVX512AIi8Base, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>; multiclass avx512_masked_scalar dopc, bits<8> qopc, AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { defm NAME#D#SUFF#Z: avx512_gather, EVEX_V512, VEX_W; + vy512xmem>, EVEX_V512, REX_W; defm NAME#Q#SUFF#Z: avx512_gather, EVEX_V512, VEX_W; + vz512mem>, EVEX_V512, REX_W; let Predicates = [HasVLX] in { defm NAME#D#SUFF#Z256: avx512_gather, EVEX_V256, VEX_W; + vx256xmem>, EVEX_V256, REX_W; defm NAME#Q#SUFF#Z256: avx512_gather, EVEX_V256, VEX_W; + vy256xmem>, EVEX_V256, REX_W; defm NAME#D#SUFF#Z128: avx512_gather, EVEX_V128, VEX_W; + vx128xmem>, EVEX_V128, REX_W; defm NAME#Q#SUFF#Z128: avx512_gather, EVEX_V128, VEX_W; + vx128xmem>, EVEX_V128, REX_W; } } @@ -10510,18 +10510,18 @@ multiclass avx512_scatter_q_pd dopc, bits<8> qopc, AVX512VLVectorVTInfo _, string OpcodeStr, string SUFF> { defm NAME#D#SUFF#Z: avx512_scatter, EVEX_V512, VEX_W; + vy512xmem>, EVEX_V512, REX_W; defm NAME#Q#SUFF#Z: avx512_scatter, EVEX_V512, VEX_W; + vz512mem>, EVEX_V512, REX_W; let Predicates = [HasVLX] in { defm NAME#D#SUFF#Z256: avx512_scatter, EVEX_V256, VEX_W; + vx256xmem>, EVEX_V256, REX_W; defm NAME#Q#SUFF#Z256: avx512_scatter, EVEX_V256, VEX_W; + vy256xmem>, EVEX_V256, REX_W; defm NAME#D#SUFF#Z128: avx512_scatter, EVEX_V128, VEX_W; + vx128xmem>, EVEX_V128, REX_W; defm NAME#Q#SUFF#Z128: avx512_scatter, EVEX_V128, VEX_W; + vx128xmem>, EVEX_V128, REX_W; } } @@ -10565,10 +10565,10 @@ VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd", - VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<32, CD8VT1>; defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd", - VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>; defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps", VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; @@ -10577,10 +10577,10 @@ VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd", - VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<32, CD8VT1>; defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd", - VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>; defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps", VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; @@ -10589,10 +10589,10 @@ VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd", - VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<32, CD8VT1>; defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd", - VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>; defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps", VK16WM, vz512mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>; @@ -10601,10 +10601,10 @@ VK8WM, vz256mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>; defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd", - VK8WM, vy512xmem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>; + VK8WM, vy512xmem>, EVEX_V512, REX_W, EVEX_CD8<32, CD8VT1>; defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd", - VK8WM, vz512mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>; + VK8WM, vz512mem>, EVEX_V512, REX_W, EVEX_CD8<64, CD8VT1>; multiclass cvt_by_vec_width opc, X86VectorVTInfo Vec, string OpcodeStr, SchedWrite Sched> { def rr : AVX512XS8I; -defm VPMOVM2W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, "vpmovm2", HasBWI> , VEX_W; +defm VPMOVM2W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, "vpmovm2", HasBWI> , REX_W; defm VPMOVM2D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, "vpmovm2", HasDQI>; -defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI> , VEX_W; +defm VPMOVM2Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, "vpmovm2", HasDQI> , REX_W; multiclass convert_vector_to_mask_common opc, X86VectorVTInfo _, string OpcodeStr > { def rr : AVX512XS8I; defm VPMOVW2M : avx512_convert_vector_to_mask<0x29, "vpmovw2m", - avx512vl_i16_info, HasBWI>, VEX_W; + avx512vl_i16_info, HasBWI>, REX_W; defm VPMOVD2M : avx512_convert_vector_to_mask<0x39, "vpmovd2m", avx512vl_i32_info, HasDQI>; defm VPMOVQ2M : avx512_convert_vector_to_mask<0x39, "vpmovq2m", - avx512vl_i64_info, HasDQI>, VEX_W; + avx512vl_i64_info, HasDQI>, REX_W; // Patterns for handling sext from a mask register to v16i8/v16i16 when DQI // is available, but BWI is not. We can't handle this in lowering because @@ -10750,11 +10750,11 @@ defm VPCOMPRESSD : compress_by_elt_width <0x8B, "vpcompressd", WriteVarShuffle256, avx512vl_i32_info>, EVEX, NotMemoryFoldable; defm VPCOMPRESSQ : compress_by_elt_width <0x8B, "vpcompressq", WriteVarShuffle256, - avx512vl_i64_info>, EVEX, VEX_W, NotMemoryFoldable; + avx512vl_i64_info>, EVEX, REX_W, NotMemoryFoldable; defm VCOMPRESSPS : compress_by_elt_width <0x8A, "vcompressps", WriteVarShuffle256, avx512vl_f32_info>, EVEX, NotMemoryFoldable; defm VCOMPRESSPD : compress_by_elt_width <0x8A, "vcompresspd", WriteVarShuffle256, - avx512vl_f64_info>, EVEX, VEX_W, NotMemoryFoldable; + avx512vl_f64_info>, EVEX, REX_W, NotMemoryFoldable; // expand multiclass expand_by_vec_width opc, X86VectorVTInfo _, @@ -10814,11 +10814,11 @@ defm VPEXPANDD : expand_by_elt_width <0x89, "vpexpandd", WriteVarShuffle256, avx512vl_i32_info>, EVEX; defm VPEXPANDQ : expand_by_elt_width <0x89, "vpexpandq", WriteVarShuffle256, - avx512vl_i64_info>, EVEX, VEX_W; + avx512vl_i64_info>, EVEX, REX_W; defm VEXPANDPS : expand_by_elt_width <0x88, "vexpandps", WriteVarShuffle256, avx512vl_f32_info>, EVEX; defm VEXPANDPD : expand_by_elt_width <0x88, "vexpandpd", WriteVarShuffle256, - avx512vl_f64_info>, EVEX, VEX_W; + avx512vl_f64_info>, EVEX, REX_W; //handle instruction reg_vec1 = op(reg_vec,imm) // op(mem_vec,imm) @@ -11081,7 +11081,7 @@ AVX512AIi8Base, EVEX, EVEX_CD8<32, CD8VF>; defm PD : avx512_common_unary_fp_sae_packed_imm, - AVX512AIi8Base, EVEX, EVEX_CD8<64, CD8VF>, VEX_W; + AVX512AIi8Base, EVEX, EVEX_CD8<64, CD8VF>, REX_W; } defm VREDUCE : avx512_common_unary_fp_sae_packed_imm_all<"vreduce", 0x56, 0x56, @@ -11097,7 +11097,7 @@ defm VRANGEPD : avx512_common_fp_sae_packed_imm<"vrangepd", avx512vl_f64_info, 0x50, X86VRange, X86VRangeSAE, SchedWriteFAdd, HasDQI>, - AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, REX_W; defm VRANGEPS : avx512_common_fp_sae_packed_imm<"vrangeps", avx512vl_f32_info, 0x50, X86VRange, X86VRangeSAE, SchedWriteFAdd, HasDQI>, @@ -11105,14 +11105,14 @@ defm VRANGESD: avx512_common_fp_sae_scalar_imm<"vrangesd", f64x_info, 0x51, X86Ranges, X86RangesSAE, SchedWriteFAdd, HasDQI>, - AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, REX_W; defm VRANGESS: avx512_common_fp_sae_scalar_imm<"vrangess", f32x_info, 0x51, X86Ranges, X86RangesSAE, SchedWriteFAdd, HasDQI>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; defm VREDUCESD: avx512_common_fp_sae_scalar_imm<"vreducesd", f64x_info, 0x57, X86Reduces, X86ReducesSAE, SchedWriteFRnd, HasDQI>, - AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, REX_W; defm VREDUCESS: avx512_common_fp_sae_scalar_imm<"vreducess", f32x_info, 0x57, X86Reduces, X86ReducesSAE, SchedWriteFRnd, HasDQI>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; @@ -11122,7 +11122,7 @@ defm VGETMANTSD: avx512_common_fp_sae_scalar_imm<"vgetmantsd", f64x_info, 0x27, X86GetMants, X86GetMantsSAE, SchedWriteFRnd, HasAVX512>, - AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, REX_W; defm VGETMANTSS: avx512_common_fp_sae_scalar_imm<"vgetmantss", f32x_info, 0x27, X86GetMants, X86GetMantsSAE, SchedWriteFRnd, HasAVX512>, AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; @@ -11184,11 +11184,11 @@ defm VSHUFF32X4 : avx512_shuff_packed_128<"vshuff32x4", WriteFShuffle256, avx512vl_f32_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; defm VSHUFF64X2 : avx512_shuff_packed_128<"vshuff64x2", WriteFShuffle256, - avx512vl_f64_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + avx512vl_f64_info, avx512vl_f64_info, 0x23, "VPERM2F128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, REX_W; defm VSHUFI32X4 : avx512_shuff_packed_128<"vshufi32x4", WriteFShuffle256, avx512vl_i32_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; defm VSHUFI64X2 : avx512_shuff_packed_128<"vshufi64x2", WriteFShuffle256, - avx512vl_i64_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + avx512vl_i64_info, avx512vl_i64_info, 0x43, "VPERM2I128">, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, REX_W; multiclass avx512_valign opc, string OpcodeStr, X86FoldableSchedWrite sched, X86VectorVTInfo _>{ @@ -11240,7 +11240,7 @@ avx512vl_i32_info>, EVEX_CD8<32, CD8VF>; defm VALIGNQ: avx512_valign_common<"valignq", SchedWriteShuffle, avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, - VEX_W; + REX_W; defm VPALIGNR: avx512_common_3Op_rm_imm8<0x0F, X86PAlignr, "vpalignr", SchedWriteShuffle, avx512vl_i8_info, @@ -11428,7 +11428,7 @@ SDNode OpNode, X86SchedWriteWidths sched, Predicate prd> { defm Q : avx512_unary_rmb_vl, VEX_W; + avx512vl_i64_info, prd>, REX_W; defm D : avx512_unary_rmb_vl; } @@ -11563,7 +11563,7 @@ multiclass avx512_movddup opc, string OpcodeStr, X86SchedWriteWidths sched> { defm NAME: avx512_movddup_common, XD, VEX_W; + avx512vl_f64_info>, XD, REX_W; } defm VMOVDDUP : avx512_movddup<0x12, "vmovddup", SchedWriteFShuffle>; @@ -11680,7 +11680,7 @@ defm VPEXTRBZ : avx512_extract_elt_b<"vpextrb", v16i8x_info>, VEX_WIG; defm VPEXTRWZ : avx512_extract_elt_w<"vpextrw", v8i16x_info>, VEX_WIG; defm VPEXTRDZ : avx512_extract_elt_dq<"vpextrd", v4i32x_info, GR32>; -defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, VEX_W; +defm VPEXTRQZ : avx512_extract_elt_dq<"vpextrq", v2i64x_info, GR64>, REX_W; multiclass avx512_insert_elt_m opc, string OpcodeStr, SDNode OpNode, X86VectorVTInfo _, PatFrag LdFrag, @@ -11727,7 +11727,7 @@ defm VPINSRWZ : avx512_insert_elt_bw<0xC4, "vpinsrw", X86pinsrw, v8i16x_info, extloadi16>, PD, VEX_WIG; defm VPINSRDZ : avx512_insert_elt_dq<0x22, "vpinsrd", v4i32x_info, GR32>; -defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, VEX_W; +defm VPINSRQZ : avx512_insert_elt_dq<0x22, "vpinsrq", v2i64x_info, GR64>, REX_W; let Predicates = [HasAVX512, NoBWI] in { def : Pat<(X86pinsrb VR128:$src1, @@ -11768,7 +11768,7 @@ } defm VSHUFPS: avx512_shufp<"vshufps", avx512vl_f32_info>, PS; -defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_f64_info>, PD, VEX_W; +defm VSHUFPD: avx512_shufp<"vshufpd", avx512vl_f64_info>, PD, REX_W; //===----------------------------------------------------------------------===// // AVX-512 - Byte shift Left/Right @@ -12073,7 +12073,7 @@ defm VPTERNLOGD : avx512_common_ternlog<"vpternlogd", SchedWriteVecALU, avx512vl_i32_info>; defm VPTERNLOGQ : avx512_common_ternlog<"vpternlogq", SchedWriteVecALU, - avx512vl_i64_info>, VEX_W; + avx512vl_i64_info>, REX_W; // Patterns to implement vnot using vpternlog instead of creating all ones // using pcmpeq or vpternlog and then xoring with that. The value 15 is chosen @@ -12281,11 +12281,11 @@ AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<32, CD8VT1>; defm VFIXUPIMMSDZ : avx512_fixupimm_scalar<0x55, "vfixupimm", SchedWriteFAdd.Scl, f64x_info, v2i64x_info>, - AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W; + AVX512AIi8Base, VEX_LIG, EVEX_4V, EVEX_CD8<64, CD8VT1>, REX_W; defm VFIXUPIMMPS : avx512_fixupimm_packed_all, EVEX_CD8<32, CD8VF>; defm VFIXUPIMMPD : avx512_fixupimm_packed_all, EVEX_CD8<64, CD8VF>, VEX_W; + avx512vl_i64_info>, EVEX_CD8<64, CD8VF>, REX_W; // Patterns used to select SSE scalar fp arithmetic instructions from // either: @@ -12534,22 +12534,22 @@ multiclass VBMI2_shift_var wOp, bits<8> dqOp, string Prefix, SDNode OpNode, X86SchedWriteWidths sched> { defm W : VBMI2_shift_var_rm_common, VEX_W, EVEX_CD8<16, CD8VF>; + avx512vl_i16_info>, REX_W, EVEX_CD8<16, CD8VF>; defm D : VBMI2_shift_var_rmb_common, EVEX_CD8<32, CD8VF>; defm Q : VBMI2_shift_var_rmb_common, VEX_W, EVEX_CD8<64, CD8VF>; + avx512vl_i64_info>, REX_W, EVEX_CD8<64, CD8VF>; } multiclass VBMI2_shift_imm wOp, bits<8> dqOp, string Prefix, SDNode OpNode, X86SchedWriteWidths sched> { defm W : avx512_common_3Op_rm_imm8, - VEX_W, EVEX_CD8<16, CD8VF>; + REX_W, EVEX_CD8<16, CD8VF>; defm D : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VF>; defm Q : avx512_common_3Op_imm8, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, VEX_W; + sched, HasVBMI2>, AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VF>, REX_W; } // Concat & Shift @@ -12563,13 +12563,13 @@ avx512vl_i8_info, HasVBMI2>, EVEX, NotMemoryFoldable; defm VPCOMPRESSW : compress_by_elt_width <0x63, "vpcompressw", WriteVarShuffle256, - avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W, + avx512vl_i16_info, HasVBMI2>, EVEX, REX_W, NotMemoryFoldable; // Expand defm VPEXPANDB : expand_by_elt_width <0x62, "vpexpandb", WriteVarShuffle256, avx512vl_i8_info, HasVBMI2>, EVEX; defm VPEXPANDW : expand_by_elt_width <0x62, "vpexpandw", WriteVarShuffle256, - avx512vl_i16_info, HasVBMI2>, EVEX, VEX_W; + avx512vl_i16_info, HasVBMI2>, EVEX, REX_W; //===----------------------------------------------------------------------===// // VNNI @@ -12656,7 +12656,7 @@ defm VPOPCNTB : avx512_unary_rm_vl<0x54, "vpopcntb", ctpop, SchedWriteVecALU, avx512vl_i8_info, HasBITALG>; defm VPOPCNTW : avx512_unary_rm_vl<0x54, "vpopcntw", ctpop, SchedWriteVecALU, - avx512vl_i16_info, HasBITALG>, VEX_W; + avx512vl_i16_info, HasBITALG>, REX_W; defm : avx512_unary_lowering<"VPOPCNTB", ctpop, avx512vl_i8_info, HasBITALG>; defm : avx512_unary_lowering<"VPOPCNTW", ctpop, avx512vl_i16_info, HasBITALG>; @@ -12751,10 +12751,10 @@ defm VGF2P8AFFINEINVQB : GF2P8AFFINE_avx512_common<0xCF, "vgf2p8affineinvqb", X86GF2P8affineinvqb, SchedWriteVecIMul>, - EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; + EVEX_4V, EVEX_CD8<8, CD8VF>, REX_W, AVX512AIi8Base; defm VGF2P8AFFINEQB : GF2P8AFFINE_avx512_common<0xCE, "vgf2p8affineqb", X86GF2P8affineqb, SchedWriteVecIMul>, - EVEX_4V, EVEX_CD8<8, CD8VF>, VEX_W, AVX512AIi8Base; + EVEX_4V, EVEX_CD8<8, CD8VF>, REX_W, AVX512AIi8Base; //===----------------------------------------------------------------------===// @@ -12860,7 +12860,7 @@ } defm VP2INTERSECTD : avx512_vp2intersect; -defm VP2INTERSECTQ : avx512_vp2intersect, VEX_W; +defm VP2INTERSECTQ : avx512_vp2intersect, REX_W; multiclass avx512_binop_all2 opc, string OpcodeStr, X86SchedWriteWidths sched, @@ -13107,9 +13107,9 @@ // Allow "vmovw" to use GR64 let hasSideEffects = 0 in { def VMOVW64toSHrr : AVX512<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src), - "vmovw\t{$src, $dst|$dst, $src}", []>, T_MAP5PD, EVEX, VEX_W, Sched<[WriteVecMoveFromGpr]>; + "vmovw\t{$src, $dst|$dst, $src}", []>, T_MAP5PD, EVEX, REX_W, Sched<[WriteVecMoveFromGpr]>; def VMOVSHtoW64rr : AVX512<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src), - "vmovw\t{$src, $dst|$dst, $src}", []>, T_MAP5PD, EVEX, VEX_W, Sched<[WriteVecMoveToGpr]>; + "vmovw\t{$src, $dst|$dst, $src}", []>, T_MAP5PD, EVEX, REX_W, Sched<[WriteVecMoveToGpr]>; } } @@ -13389,11 +13389,11 @@ } defm VCVTQQ2PH : avx512_cvtqq2ph<0x5B, "vcvtqq2ph", any_sint_to_fp, sint_to_fp, - X86VSintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, T_MAP5PS, + X86VSintToFpRnd, SchedWriteCvtDQ2PS>, REX_W, T_MAP5PS, EVEX_CD8<64, CD8VF>; defm VCVTUQQ2PH : avx512_cvtqq2ph<0x7A, "vcvtuqq2ph", any_uint_to_fp, uint_to_fp, - X86VUintToFpRnd, SchedWriteCvtDQ2PS>, VEX_W, T_MAP5XD, + X86VUintToFpRnd, SchedWriteCvtDQ2PS>, REX_W, T_MAP5XD, EVEX_CD8<64, CD8VF>; // Convert half to signed/unsigned int 32/64 @@ -13402,26 +13402,26 @@ T_MAP5XS, EVEX_CD8<16, CD8VT1>; defm VCVTSH2SI64Z: avx512_cvt_s_int_round<0x2D, f16x_info, i64x_info, X86cvts2si, X86cvts2siRnd, WriteCvtSS2I, "cvtsh2si", "{q}", HasFP16>, - T_MAP5XS, VEX_W, EVEX_CD8<16, CD8VT1>; + T_MAP5XS, REX_W, EVEX_CD8<16, CD8VT1>; defm VCVTSH2USIZ: avx512_cvt_s_int_round<0x79, f16x_info, i32x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSS2I, "cvtsh2usi", "{l}", HasFP16>, T_MAP5XS, EVEX_CD8<16, CD8VT1>; defm VCVTSH2USI64Z: avx512_cvt_s_int_round<0x79, f16x_info, i64x_info, X86cvts2usi, X86cvts2usiRnd, WriteCvtSS2I, "cvtsh2usi", "{q}", HasFP16>, - T_MAP5XS, VEX_W, EVEX_CD8<16, CD8VT1>; + T_MAP5XS, REX_W, EVEX_CD8<16, CD8VT1>; defm VCVTTSH2SIZ: avx512_cvt_s_all<0x2C, "vcvttsh2si", f16x_info, i32x_info, any_fp_to_sint, X86cvtts2Int, X86cvtts2IntSAE, WriteCvtSS2I, "{l}", HasFP16>, T_MAP5XS, EVEX_CD8<16, CD8VT1>; defm VCVTTSH2SI64Z: avx512_cvt_s_all<0x2C, "vcvttsh2si", f16x_info, i64x_info, any_fp_to_sint, X86cvtts2Int, X86cvtts2IntSAE, WriteCvtSS2I, - "{q}", HasFP16>, VEX_W, T_MAP5XS, EVEX_CD8<16, CD8VT1>; + "{q}", HasFP16>, REX_W, T_MAP5XS, EVEX_CD8<16, CD8VT1>; defm VCVTTSH2USIZ: avx512_cvt_s_all<0x78, "vcvttsh2usi", f16x_info, i32x_info, any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I, "{l}", HasFP16>, T_MAP5XS, EVEX_CD8<16, CD8VT1>; defm VCVTTSH2USI64Z: avx512_cvt_s_all<0x78, "vcvttsh2usi", f16x_info, i64x_info, any_fp_to_uint, X86cvtts2UInt, X86cvtts2UIntSAE, WriteCvtSS2I, - "{q}", HasFP16>, T_MAP5XS, VEX_W, EVEX_CD8<16, CD8VT1>; + "{q}", HasFP16>, T_MAP5XS, REX_W, EVEX_CD8<16, CD8VT1>; let Predicates = [HasFP16] in { defm VCVTSI2SHZ : avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SS, GR32, @@ -13429,13 +13429,13 @@ T_MAP5XS, EVEX_CD8<32, CD8VT1>; defm VCVTSI642SHZ: avx512_vcvtsi_common<0x2A, X86SintToFp, X86SintToFpRnd, WriteCvtI2SS, GR64, v8f16x_info, i64mem, loadi64, "cvtsi2sh","q">, - T_MAP5XS, VEX_W, EVEX_CD8<64, CD8VT1>; + T_MAP5XS, REX_W, EVEX_CD8<64, CD8VT1>; defm VCVTUSI2SHZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SS, GR32, v8f16x_info, i32mem, loadi32, "cvtusi2sh","l">, T_MAP5XS, EVEX_CD8<32, CD8VT1>; defm VCVTUSI642SHZ : avx512_vcvtsi_common<0x7B, X86UintToFp, X86UintToFpRnd, WriteCvtI2SS, GR64, v8f16x_info, i64mem, loadi64, "cvtusi2sh", "q">, - T_MAP5XS, VEX_W, EVEX_CD8<64, CD8VT1>; + T_MAP5XS, REX_W, EVEX_CD8<64, CD8VT1>; def : InstAlias<"vcvtsi2sh\t{$src, $src1, $dst|$dst, $src1, $src}", (VCVTSI2SHZrm_Int VR128X:$dst, VR128X:$src1, i32mem:$src), 0, "att">; diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -1397,7 +1397,7 @@ // Complexity is reduced to give and with immediate a chance to match first. let Predicates = [HasBMI], Defs = [EFLAGS], AddedComplexity = -6 in { defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32, WriteALU>, T8PS, VEX_4V; - defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, VEX_W; + defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64, WriteALU>, T8PS, VEX_4V, REX_W; } let Predicates = [HasBMI], AddedComplexity = -6 in { @@ -1446,7 +1446,7 @@ let Uses = [EDX] in defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem, WriteMULX32>; let Uses = [RDX] in - defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, VEX_W; + defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem, WriteMULX64>, REX_W; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86InstrFMA.td b/llvm/lib/Target/X86/X86InstrFMA.td --- a/llvm/lib/Target/X86/X86InstrFMA.td +++ b/llvm/lib/Target/X86/X86InstrFMA.td @@ -139,16 +139,16 @@ let ExeDomain = SSEPackedDouble in { defm VFMADD : fma3p_forms<0x98, 0xA8, 0xB8, "vfmadd", "pd", "PD", loadv2f64, loadv4f64, any_fma, v2f64, - v4f64, SchedWriteFMA>, VEX_W; + v4f64, SchedWriteFMA>, REX_W; defm VFMSUB : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "pd", "PD", loadv2f64, loadv4f64, X86any_Fmsub, v2f64, - v4f64, SchedWriteFMA>, VEX_W; + v4f64, SchedWriteFMA>, REX_W; defm VFMADDSUB : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "pd", "PD", loadv2f64, loadv4f64, X86Fmaddsub, - v2f64, v4f64, SchedWriteFMA>, VEX_W; + v2f64, v4f64, SchedWriteFMA>, REX_W; defm VFMSUBADD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd", "PD", loadv2f64, loadv4f64, X86Fmsubadd, - v2f64, v4f64, SchedWriteFMA>, VEX_W; + v2f64, v4f64, SchedWriteFMA>, REX_W; } // Fused Negative Multiply-Add @@ -160,9 +160,9 @@ } let ExeDomain = SSEPackedDouble in { defm VFNMADD : fma3p_forms<0x9C, 0xAC, 0xBC, "vfnmadd", "pd", "PD", loadv2f64, - loadv4f64, X86any_Fnmadd, v2f64, v4f64, SchedWriteFMA>, VEX_W; + loadv4f64, X86any_Fnmadd, v2f64, v4f64, SchedWriteFMA>, REX_W; defm VFNMSUB : fma3p_forms<0x9E, 0xAE, 0xBE, "vfnmsub", "pd", "PD", loadv2f64, - loadv4f64, X86any_Fnmsub, v2f64, v4f64, SchedWriteFMA>, VEX_W; + loadv4f64, X86any_Fnmsub, v2f64, v4f64, SchedWriteFMA>, REX_W; } // All source register operands of FMA opcodes defined in fma3s_rm multiclass @@ -316,7 +316,7 @@ defm NAME : fma3s_forms, fma3s_int_forms, VEX_W; + VR128, sdmem, sched>, REX_W; } defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", any_fma, @@ -396,14 +396,14 @@ !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), [(set RC:$dst, - (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, VEX_W, VEX_LIG, + (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>, REX_W, VEX_LIG, Sched<[sched]>; def rm : FMA4S, VEX_W, VEX_LIG, + (mem_frag addr:$src3)))]>, REX_W, VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; def mr : FMA4S, VEX_W, VEX_LIG, Sched<[sched]>; + []>, REX_W, VEX_LIG, Sched<[sched]>; let mayLoad = 1 in def rm_Int : FMA4S_Int, VEX_W, VEX_LIG, + []>, REX_W, VEX_LIG, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; let mayLoad = 1 in def mr_Int : FMA4S_Int, - VEX_W, Sched<[sched.XMM]>; + REX_W, Sched<[sched.XMM]>; def rm : FMA4, VEX_W, + (ld_frag128 addr:$src3)))]>, REX_W, Sched<[sched.XMM.Folded, sched.XMM.ReadAfterFold, sched.XMM.ReadAfterFold]>; def mr : FMA4, - VEX_W, VEX_L, Sched<[sched.YMM]>; + REX_W, VEX_L, Sched<[sched.YMM]>; def Yrm : FMA4, VEX_W, VEX_L, + (ld_frag256 addr:$src3)))]>, REX_W, VEX_L, Sched<[sched.YMM.Folded, sched.YMM.ReadAfterFold, sched.YMM.ReadAfterFold]>; def Ymr : FMA4 OpEncBits = OpEnc.Value; - bit HasVEX_W = 0; // Does this inst set the VEX_W field? - bit IgnoresVEX_W = 0; // Does this inst ignore VEX_W field? + bit IgnoresVEX_W = 0; // Does this inst ignore REX_W field? bit EVEX_W1_VEX_W0 = 0; // This EVEX inst with VEX.W==1 can become a VEX // instruction with VEX.W == 0. bit hasVEX_4V = 0; // Does this inst require the VEX.VVVV field? @@ -385,18 +383,17 @@ let TSFlags{30-29} = OpEncBits; let TSFlags{38-31} = Opcode; // Currently no need for second bit in TSFlags - W Ignore is equivalent to 0. - let TSFlags{39} = HasVEX_W; - let TSFlags{40} = hasVEX_4V; - let TSFlags{41} = hasVEX_L; - let TSFlags{42} = hasEVEX_K; - let TSFlags{43} = hasEVEX_Z; - let TSFlags{44} = hasEVEX_L2; - let TSFlags{45} = hasEVEX_B; + let TSFlags{39} = hasVEX_4V; + let TSFlags{40} = hasVEX_L; + let TSFlags{41} = hasEVEX_K; + let TSFlags{42} = hasEVEX_Z; + let TSFlags{43} = hasEVEX_L2; + let TSFlags{44} = hasEVEX_B; // If we run out of TSFlags bits, it's possible to encode this in 3 bits. - let TSFlags{52-46} = CD8_Scale; - let TSFlags{53} = hasEVEX_RC; - let TSFlags{54} = hasNoTrackPrefix; - let TSFlags{55} = ExplicitVEXPrefix; + let TSFlags{51-45} = CD8_Scale; + let TSFlags{52} = hasEVEX_RC; + let TSFlags{53} = hasNoTrackPrefix; + let TSFlags{54} = ExplicitVEXPrefix; } class PseudoI pattern> @@ -990,7 +987,7 @@ : S2I, REX_W; class VRS2I o, Format F, dag outs, dag ins, string asm, list pattern> - : VS2I, VEX_W; + : VS2I, REX_W; // MMX Instruction templates // diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1235,11 +1235,11 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in { defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>; - defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W; + defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, REX_W; defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>; - defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W; + defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, REX_W; defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>; - defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, VEX_W; + defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, REX_W; } //===----------------------------------------------------------------------===// @@ -1322,7 +1322,7 @@ defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, X86bextr, loadi32, WriteBEXTR>; defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, - X86bextr, loadi64, WriteBEXTR>, VEX_W; + X86bextr, loadi64, WriteBEXTR>, REX_W; } multiclass bmi_bzhi opc, string mnemonic, RegisterClass RC, @@ -1348,7 +1348,7 @@ defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, X86bzhi, loadi32, WriteBZHI>; defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, - X86bzhi, loadi64, WriteBZHI>, VEX_W; + X86bzhi, loadi64, WriteBZHI>, REX_W; } def CountTrailingOnes : SDNodeXForm, T8XD; defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, - X86pdep, loadi64>, T8XD, VEX_W; + X86pdep, loadi64>, T8XD, REX_W; defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, X86pext, loadi32>, T8XS; defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, - X86pext, loadi64>, T8XS, VEX_W; + X86pext, loadi64>, T8XS, REX_W; } //===----------------------------------------------------------------------===// @@ -1424,9 +1424,9 @@ [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", - [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; + [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, REX_W; def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", - [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; + [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, REX_W; multiclass lwpins_intr { def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), @@ -1442,7 +1442,7 @@ let Defs = [EFLAGS] in { defm LWPINS32 : lwpins_intr; - defm LWPINS64 : lwpins_intr, VEX_W; + defm LWPINS64 : lwpins_intr, REX_W; } // EFLAGS multiclass lwpval_intr { @@ -1457,7 +1457,7 @@ } defm LWPVAL32 : lwpval_intr; -defm LWPVAL64 : lwpval_intr, VEX_W; +defm LWPVAL64 : lwpval_intr, REX_W; } // HasLWP, SchedRW @@ -1674,7 +1674,7 @@ "cmp${cond}xadd\t{$src3, $dst, $dstsrc2|$dstsrc2, $dst, $src3}", [(set GR64:$dst, (X86cmpccxadd addr:$dstsrc2, GR64:$dstsrc1, GR64:$src3, timm:$cond))]>, - VEX_4V, VEX_W, T8PD, Sched<[WriteXCHG]>; + VEX_4V, REX_W, T8PD, Sched<[WriteXCHG]>; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -913,7 +913,7 @@ defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, any_fp_to_sint, f32mem, loadf32, "cvttss2si", "cvttss2si", WriteCvtSS2I, SSEPackedSingle>, - XS, VEX, VEX_W, VEX_LIG; + XS, VEX, REX_W, VEX_LIG; defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, any_fp_to_sint, f64mem, loadf64, "cvttsd2si", "cvttsd2si", WriteCvtSD2I, SSEPackedDouble>, @@ -921,7 +921,7 @@ defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, any_fp_to_sint, f64mem, loadf64, "cvttsd2si", "cvttsd2si", WriteCvtSD2I, SSEPackedDouble>, - XD, VEX, VEX_W, VEX_LIG; + XD, VEX, REX_W, VEX_LIG; defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, lrint, f32mem, loadf32, "cvtss2si", "cvtss2si", @@ -930,7 +930,7 @@ defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, llrint, f32mem, loadf32, "cvtss2si", "cvtss2si", WriteCvtSS2I, SSEPackedSingle>, - XS, VEX, VEX_W, VEX_LIG; + XS, VEX, REX_W, VEX_LIG; defm VCVTSD2SI : sse12_cvt_s<0x2D, FR64, GR32, lrint, f64mem, loadf64, "cvtsd2si", "cvtsd2si", WriteCvtSD2I, SSEPackedDouble>, @@ -938,7 +938,7 @@ defm VCVTSD2SI64 : sse12_cvt_s<0x2D, FR64, GR64, llrint, f64mem, loadf64, "cvtsd2si", "cvtsd2si", WriteCvtSD2I, SSEPackedDouble>, - XD, VEX, VEX_W, VEX_LIG; + XD, VEX, REX_W, VEX_LIG; } // The assembler can recognize rr 64-bit instructions by seeing a rxx @@ -951,13 +951,13 @@ VEX_LIG, SIMD_EXC; defm VCVTSI642SS : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss", "q", WriteCvtI2SS, SSEPackedSingle>, XS, VEX_4V, - VEX_W, VEX_LIG, SIMD_EXC; + REX_W, VEX_LIG, SIMD_EXC; defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd", "l", WriteCvtI2SD, SSEPackedDouble>, XD, VEX_4V, VEX_LIG; defm VCVTSI642SD : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd", "q", WriteCvtI2SD, SSEPackedDouble>, XD, VEX_4V, - VEX_W, VEX_LIG, SIMD_EXC; + REX_W, VEX_LIG, SIMD_EXC; } // isCodeGenOnly = 1 let Predicates = [UseAVX] in { @@ -1083,7 +1083,7 @@ WriteCvtSD2I, SSEPackedDouble>, XD, VEX, VEX_LIG; defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v2f64, X86cvts2si, sdmem, sse_load_f64, "cvtsd2si", - WriteCvtSD2I, SSEPackedDouble>, XD, VEX, VEX_W, VEX_LIG; + WriteCvtSD2I, SSEPackedDouble>, XD, VEX, REX_W, VEX_LIG; } defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, i32, v2f64, X86cvts2si, sdmem, sse_load_f64, "cvtsd2si", WriteCvtSD2I, @@ -1099,13 +1099,13 @@ XS, VEX_4V, VEX_LIG, SIMD_EXC; defm VCVTSI642SS : sse12_cvt_sint_3addr<0x2A, GR64, VR128, i64mem, "cvtsi2ss", "q", WriteCvtI2SS, SSEPackedSingle, 0>, - XS, VEX_4V, VEX_LIG, VEX_W, SIMD_EXC; + XS, VEX_4V, VEX_LIG, REX_W, SIMD_EXC; defm VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128, i32mem, "cvtsi2sd", "l", WriteCvtI2SD, SSEPackedDouble, 0>, XD, VEX_4V, VEX_LIG; defm VCVTSI642SD : sse12_cvt_sint_3addr<0x2A, GR64, VR128, i64mem, "cvtsi2sd", "q", WriteCvtI2SD, SSEPackedDouble, 0>, - XD, VEX_4V, VEX_LIG, VEX_W, SIMD_EXC; + XD, VEX_4V, VEX_LIG, REX_W, SIMD_EXC; } let Constraints = "$src1 = $dst" in { defm CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128, @@ -1160,14 +1160,14 @@ defm VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v4f32, X86cvtts2Int, ssmem, sse_load_f32, "cvttss2si", WriteCvtSS2I, SSEPackedSingle>, - XS, VEX, VEX_LIG, VEX_W; + XS, VEX, VEX_LIG, REX_W; defm VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v2f64, X86cvtts2Int, sdmem, sse_load_f64, "cvttsd2si", WriteCvtSS2I, SSEPackedDouble>, XD, VEX, VEX_LIG; defm VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64, i64, v2f64, X86cvtts2Int, sdmem, sse_load_f64, "cvttsd2si", WriteCvtSS2I, SSEPackedDouble>, - XD, VEX, VEX_LIG, VEX_W; + XD, VEX, VEX_LIG, REX_W; } let Uses = [MXCSR], mayRaiseFPException = 1 in { defm CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, i32, v4f32, X86cvtts2Int, @@ -1226,7 +1226,7 @@ WriteCvtSS2I, SSEPackedSingle>, XS, VEX, VEX_LIG; defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, i64, v4f32, X86cvts2si, ssmem, sse_load_f32, "cvtss2si", - WriteCvtSS2I, SSEPackedSingle>, XS, VEX, VEX_W, VEX_LIG; + WriteCvtSS2I, SSEPackedSingle>, XS, VEX, REX_W, VEX_LIG; } let Uses = [MXCSR], mayRaiseFPException = 1 in { defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, i32, v4f32, X86cvts2si, @@ -5320,7 +5320,7 @@ } let Predicates = [HasAVX, NoDQI] in - defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W; + defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, REX_W; defm PEXTRQ : SS41I_extract64<0x16, "pextrq">, REX_W; @@ -5431,7 +5431,7 @@ } let Predicates = [HasAVX, NoDQI] in - defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W; + defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, REX_W; let Constraints = "$src1 = $dst" in defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W; @@ -7826,10 +7826,10 @@ } defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64, - WriteShuffle256, i256mem>, VEX_W; + WriteShuffle256, i256mem>, REX_W; let ExeDomain = SSEPackedDouble in defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64, - WriteFShuffle256, f256mem>, VEX_W; + WriteFShuffle256, f256mem>, REX_W; //===----------------------------------------------------------------------===// // VPERM2I128 - Permute Integer vector Values in 128-bit chunks @@ -7940,7 +7940,7 @@ int_x86_avx2_maskload_q_256, int_x86_avx2_maskstore_q, int_x86_avx2_maskstore_q_256, - WriteVecMaskMove64, WriteVecMaskMove64Y>, VEX_W; + WriteVecMaskMove64, WriteVecMaskMove64Y>, REX_W; multiclass maskmov_lowering { @@ -8011,9 +8011,9 @@ let Predicates = [HasAVX2, NoVLX] in { defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", X86vshlv, v4i32, v8i32>; - defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", X86vshlv, v2i64, v4i64>, VEX_W; + defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", X86vshlv, v2i64, v4i64>, REX_W; defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", X86vsrlv, v4i32, v8i32>; - defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", X86vsrlv, v2i64, v4i64>, VEX_W; + defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", X86vsrlv, v2i64, v4i64>, REX_W; defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", X86vsrav, v4i32, v8i32>; } @@ -8042,9 +8042,9 @@ = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb" in { defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", - VR256, vx128mem, vx256mem>, VEX_W; + VR256, vx128mem, vx256mem>, REX_W; defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", - VR256, vx128mem, vy256mem>, VEX_W; + VR256, vx128mem, vy256mem>, REX_W; defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx128mem, vy256mem>; defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", @@ -8052,9 +8052,9 @@ let ExeDomain = SSEPackedDouble in { defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", - VR256, vx128mem, vx256mem>, VEX_W; + VR256, vx128mem, vx256mem>, REX_W; defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", - VR256, vx128mem, vy256mem>, VEX_W; + VR256, vx128mem, vy256mem>, REX_W; } let ExeDomain = SSEPackedSingle in { @@ -8118,10 +8118,10 @@ let Predicates = [HasGFNI, HasAVX, NoVLX] in { defm V#NAME : GF2P8AFFINE_rmi, - VEX_4V, VEX_W; + VEX_4V, REX_W; defm V#NAME#Y : GF2P8AFFINE_rmi, - VEX_4V, VEX_L, VEX_W; + VEX_4V, VEX_L, REX_W; } } @@ -8180,8 +8180,8 @@ VEX_4V, VEX_L, Sched<[SchedWriteVecIMul.YMM]>; } -defm VPMADD52HUQ : avx_ifma_rm<0xb5, "vpmadd52huq", x86vpmadd52h>, VEX_W, ExplicitVEXPrefix; -defm VPMADD52LUQ : avx_ifma_rm<0xb4, "vpmadd52luq", x86vpmadd52l>, VEX_W, ExplicitVEXPrefix; +defm VPMADD52HUQ : avx_ifma_rm<0xb5, "vpmadd52huq", x86vpmadd52h>, REX_W, ExplicitVEXPrefix; +defm VPMADD52LUQ : avx_ifma_rm<0xb4, "vpmadd52luq", x86vpmadd52l>, REX_W, ExplicitVEXPrefix; // AVX-VNNI-INT8 let Constraints = "$src1 = $dst" in diff --git a/llvm/lib/Target/X86/X86InstrShiftRotate.td b/llvm/lib/Target/X86/X86InstrShiftRotate.td --- a/llvm/lib/Target/X86/X86InstrShiftRotate.td +++ b/llvm/lib/Target/X86/X86InstrShiftRotate.td @@ -913,13 +913,13 @@ let Predicates = [HasBMI2] in { defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>; - defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W; + defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, REX_W; defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS; - defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W; + defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, REX_W; defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD; - defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W; + defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, REX_W; defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD; - defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W; + defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, REX_W; // Prefer RORX which is non-destructive and doesn't update EFLAGS. let AddedComplexity = 10 in { diff --git a/llvm/lib/Target/X86/X86InstrTBM.td b/llvm/lib/Target/X86/X86InstrTBM.td --- a/llvm/lib/Target/X86/X86InstrTBM.td +++ b/llvm/lib/Target/X86/X86InstrTBM.td @@ -38,7 +38,7 @@ let ImmT = Imm32S in defm BEXTRI64 : tbm_bextri<0x10, GR64, "bextr{q}", i64mem, loadi64, X86bextri, i64i32imm, - i64timmSExt32, WriteBEXTR>, VEX_W; + i64timmSExt32, WriteBEXTR>, REX_W; multiclass tbm_binary_rm opc, Format FormReg, Format FormMem, RegisterClass RC, string OpcodeStr, @@ -60,7 +60,7 @@ defm NAME#32 : tbm_binary_rm; defm NAME#64 : tbm_binary_rm, VEX_W; + i64mem, Sched>, REX_W; } defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; diff --git a/llvm/lib/Target/X86/X86InstrXOP.td b/llvm/lib/Target/X86/X86InstrXOP.td --- a/llvm/lib/Target/X86/X86InstrXOP.td +++ b/llvm/lib/Target/X86/X86InstrXOP.td @@ -105,7 +105,7 @@ [(set VR128:$dst, (vt128 (OpNode (vt128 VR128:$src1), (vt128 (load addr:$src2)))))]>, - XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold]>; + XOP_4V, REX_W, Sched<[sched.Folded, sched.ReadAfterFold]>; def mr : IXOP, - XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; + XOP_4V, REX_W, Sched<[sched]>, FoldGenData; } let ExeDomain = SSEPackedInt in { @@ -296,7 +296,7 @@ [(set VR128:$dst, (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2), (vt128 (load addr:$src3)))))]>, - XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; + XOP_4V, REX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; def rmr : IXOPi8Reg, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; + []>, XOP_4V, REX_W, Sched<[sched]>, FoldGenData; } let ExeDomain = SSEPackedInt in { @@ -342,7 +342,7 @@ !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), []>, - XOP_4V, VEX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; + XOP_4V, REX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; def rmr : IXOPi8Reg, XOP_4V, VEX_W, Sched<[sched]>, FoldGenData; + []>, XOP_4V, REX_W, Sched<[sched]>, FoldGenData; } let ExeDomain = SSEPackedInt in { @@ -430,7 +430,7 @@ "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), [(set RC:$dst, (VT (X86vpermil2 RC:$src1, RC:$src2, (IntLdFrag addr:$src3), - (i8 timm:$src4))))]>, VEX_W, + (i8 timm:$src4))))]>, REX_W, Sched<[sched.Folded, sched.ReadAfterFold, sched.ReadAfterFold]>; def mr : IXOP5, VEX_W, Sched<[sched]>, FoldGenData; + []>, REX_W, Sched<[sched]>, FoldGenData; } let ExeDomain = SSEPackedDouble in { diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -975,7 +975,7 @@ (TSFlags & X86II::EncodingMask) == X86II::VEX && (TSFlags & X86II::OpMapMask) == X86II::TB && (TSFlags & X86II::FormMask) == X86II::MRMSrcReg && - !(TSFlags & X86II::VEX_W) && (TSFlags & X86II::VEX_4V) && + !(TSFlags & X86II::REX_W) && (TSFlags & X86II::VEX_4V) && OutMI.getNumOperands() == 3) { if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg()) && X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) diff --git a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp --- a/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86EVEX2VEXTablesEmitter.cpp @@ -114,8 +114,8 @@ bool operator()(const CodeGenInstruction *VEXInst) { RecognizableInstrBase VEXRI(*VEXInst); RecognizableInstrBase EVEXRI(*EVEXInst); - bool VEX_W = VEXRI.HasVEX_W; - bool EVEX_W = EVEXRI.HasVEX_W; + bool VEX_W = VEXRI.HasREX_W; + bool EVEX_W = EVEXRI.HasREX_W; bool VEX_WIG = VEXRI.IgnoresVEX_W; bool EVEX_WIG = EVEXRI.IgnoresVEX_W; bool EVEX_W1_VEX_W0 = EVEXInst->TheDef->getValueAsBit("EVEX_W1_VEX_W0"); diff --git a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp --- a/llvm/utils/TableGen/X86FoldTablesEmitter.cpp +++ b/llvm/utils/TableGen/X86FoldTablesEmitter.cpp @@ -273,7 +273,6 @@ RegRI.HasREX_W != MemRI.HasREX_W || RegRI.HasVEX_4V != MemRI.HasVEX_4V || RegRI.HasVEX_L != MemRI.HasVEX_L || - RegRI.HasVEX_W != MemRI.HasVEX_W || RegRI.IgnoresVEX_L != MemRI.IgnoresVEX_L || RegRI.IgnoresVEX_W != MemRI.IgnoresVEX_W || RegRI.HasEVEX_K != MemRI.HasEVEX_K || diff --git a/llvm/utils/TableGen/X86RecognizableInstr.h b/llvm/utils/TableGen/X86RecognizableInstr.h --- a/llvm/utils/TableGen/X86RecognizableInstr.h +++ b/llvm/utils/TableGen/X86RecognizableInstr.h @@ -182,8 +182,6 @@ bool HasREX_W; /// The hasVEX_4V field from the record bool HasVEX_4V; - /// The HasVEX_WPrefix field from the record - bool HasVEX_W; /// The IgnoresVEX_W field from the record bool IgnoresVEX_W; /// The hasVEX_L field from the record diff --git a/llvm/utils/TableGen/X86RecognizableInstr.cpp b/llvm/utils/TableGen/X86RecognizableInstr.cpp --- a/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -118,7 +118,6 @@ AdSize = byteFromRec(Rec, "AdSizeBits"); HasREX_W = Rec->getValueAsBit("hasREX_W"); HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); - HasVEX_W = Rec->getValueAsBit("HasVEX_W"); IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); @@ -189,7 +188,7 @@ llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); } // VEX_L & VEX_W - if (!EncodeRC && HasVEX_L && HasVEX_W) { + if (!EncodeRC && HasVEX_L && HasREX_W) { if (OpPrefix == X86Local::PD) insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); else if (OpPrefix == X86Local::XS) @@ -216,7 +215,7 @@ errs() << "Instruction does not use a prefix: " << Name << "\n"; llvm_unreachable("Invalid prefix"); } - } else if (!EncodeRC && HasEVEX_L2 && HasVEX_W) { + } else if (!EncodeRC && HasEVEX_L2 && HasREX_W) { // EVEX_L2 & VEX_W if (OpPrefix == X86Local::PD) insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); @@ -245,7 +244,7 @@ llvm_unreachable("Invalid prefix"); } } - else if (HasVEX_W) { + else if (HasREX_W) { // VEX_W if (OpPrefix == X86Local::PD) insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); @@ -275,7 +274,7 @@ } /// eof EVEX } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { - if (HasVEX_L && HasVEX_W) { + if (HasVEX_L && HasREX_W) { if (OpPrefix == X86Local::PD) insnContext = IC_VEX_L_W_OPSIZE; else if (OpPrefix == X86Local::XS) @@ -290,7 +289,7 @@ } } else if (OpPrefix == X86Local::PD && HasVEX_L) insnContext = IC_VEX_L_OPSIZE; - else if (OpPrefix == X86Local::PD && HasVEX_W) + else if (OpPrefix == X86Local::PD && HasREX_W) insnContext = IC_VEX_W_OPSIZE; else if (OpPrefix == X86Local::PD) insnContext = IC_VEX_OPSIZE; @@ -298,11 +297,11 @@ insnContext = IC_VEX_L_XS; else if (HasVEX_L && OpPrefix == X86Local::XD) insnContext = IC_VEX_L_XD; - else if (HasVEX_W && OpPrefix == X86Local::XS) + else if (HasREX_W && OpPrefix == X86Local::XS) insnContext = IC_VEX_W_XS; - else if (HasVEX_W && OpPrefix == X86Local::XD) + else if (HasREX_W && OpPrefix == X86Local::XD) insnContext = IC_VEX_W_XD; - else if (HasVEX_W && OpPrefix == X86Local::PS) + else if (HasREX_W && OpPrefix == X86Local::PS) insnContext = IC_VEX_W; else if (HasVEX_L && OpPrefix == X86Local::PS) insnContext = IC_VEX_L;