diff --git a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
--- a/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vhadd.ll
@@ -1191,6 +1191,221 @@
   ret <8 x i8> %result
 }
 
+define <8 x i8> @shadd_v8i8(<8 x i8> %x) {
+; CHECK-LABEL: shadd_v8i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shadd.8b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %x, <8 x i8> %x)
+  ret <8 x i8> %r
+}
+
+define <4 x i16> @shadd_v4i16(<4 x i16> %x) {
+; CHECK-LABEL: shadd_v4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shadd.4h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i16> @llvm.aarch64.neon.shadd.v4i16(<4 x i16> %x, <4 x i16> %x)
+  ret <4 x i16> %r
+}
+
+define <2 x i32> @shadd_v2i32(<2 x i32> %x) {
+; CHECK-LABEL: shadd_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shadd.2s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <2 x i32> @llvm.aarch64.neon.shadd.v2i32(<2 x i32> %x, <2 x i32> %x)
+  ret <2 x i32> %r
+}
+
+define <16 x i8> @shadd_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: shadd_v16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shadd.16b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <16 x i8> @llvm.aarch64.neon.shadd.v16i8(<16 x i8> %x, <16 x i8> %x)
+  ret <16 x i8> %r
+}
+
+define <8 x i16> @shadd_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: shadd_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shadd.8h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x, <8 x i16> %x)
+  ret <8 x i16> %r
+}
+
+define <4 x i32> @shadd_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: shadd_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    shadd.4s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i32> @llvm.aarch64.neon.shadd.v4i32(<4 x i32> %x, <4 x i32> %x)
+  ret <4 x i32> %r
+}
+
+define <8 x i8> @uhadd_v8i8(<8 x i8> %x) {
+; CHECK-LABEL: uhadd_v8i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uhadd.8b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
+  ret <8 x i8> %r
+}
+
+define <4 x i16> @uhadd_v4i16(<4 x i16> %x) {
+; CHECK-LABEL: uhadd_v4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uhadd.4h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i16> @llvm.aarch64.neon.uhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
+  ret <4 x i16> %r
+}
+
+define <2 x i32> @uhadd_v2i32(<2 x i32> %x) {
+; CHECK-LABEL: uhadd_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uhadd.2s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <2 x i32> @llvm.aarch64.neon.uhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
+  ret <2 x i32> %r
+}
+
+define <16 x i8> @uhadd_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: uhadd_v16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uhadd.16b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <16 x i8> @llvm.aarch64.neon.uhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
+  ret <16 x i8> %r
+}
+
+define <8 x i16> @uhadd_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: uhadd_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uhadd.8h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
+  ret <8 x i16> %r
+}
+
+define <4 x i32> @uhadd_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: uhadd_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    uhadd.4s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i32> @llvm.aarch64.neon.uhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
+  ret <4 x i32> %r
+}
+define <8 x i8> @srhadd_v8i8(<8 x i8> %x) {
+; CHECK-LABEL: srhadd_v8i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    srhadd.8b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
+  ret <8 x i8> %r
+}
+
+define <4 x i16> @srhadd_v4i16(<4 x i16> %x) {
+; CHECK-LABEL: srhadd_v4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    srhadd.4h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
+  ret <4 x i16> %r
+}
+
+define <2 x i32> @srhadd_v2i32(<2 x i32> %x) {
+; CHECK-LABEL: srhadd_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    srhadd.2s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
+  ret <2 x i32> %r
+}
+
+define <16 x i8> @srhadd_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: srhadd_v16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    srhadd.16b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <16 x i8> @llvm.aarch64.neon.srhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
+  ret <16 x i8> %r
+}
+
+define <8 x i16> @srhadd_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: srhadd_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    srhadd.8h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
+  ret <8 x i16> %r
+}
+
+define <4 x i32> @srhadd_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: srhadd_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    srhadd.4s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i32> @llvm.aarch64.neon.srhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
+  ret <4 x i32> %r
+}
+
+define <8 x i8> @urhadd_v8i8(<8 x i8> %x) {
+; CHECK-LABEL: urhadd_v8i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    urhadd.8b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %x, <8 x i8> %x)
+  ret <8 x i8> %r
+}
+
+define <4 x i16> @urhadd_v4i16(<4 x i16> %x) {
+; CHECK-LABEL: urhadd_v4i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    urhadd.4h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i16> @llvm.aarch64.neon.urhadd.v4i16(<4 x i16> %x, <4 x i16> %x)
+  ret <4 x i16> %r
+}
+
+define <2 x i32> @urhadd_v2i32(<2 x i32> %x) {
+; CHECK-LABEL: urhadd_v2i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    urhadd.2s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <2 x i32> @llvm.aarch64.neon.urhadd.v2i32(<2 x i32> %x, <2 x i32> %x)
+  ret <2 x i32> %r
+}
+
+define <16 x i8> @urhadd_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: urhadd_v16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    urhadd.16b v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <16 x i8> @llvm.aarch64.neon.urhadd.v16i8(<16 x i8> %x, <16 x i8> %x)
+  ret <16 x i8> %r
+}
+
+define <8 x i16> @urhadd_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: urhadd_v8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    urhadd.8h v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x, <8 x i16> %x)
+  ret <8 x i16> %r
+}
+
+define <4 x i32> @urhadd_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: urhadd_v4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    urhadd.4s v0, v0, v0
+; CHECK-NEXT:    ret
+  %r = tail call <4 x i32> @llvm.aarch64.neon.urhadd.v4i32(<4 x i32> %x, <4 x i32> %x)
+  ret <4 x i32> %r
+}
+
 declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>)
 declare <4 x i16> @llvm.aarch64.neon.srhadd.v4i16(<4 x i16>, <4 x i16>)
 declare <2 x i32> @llvm.aarch64.neon.srhadd.v2i32(<2 x i32>, <2 x i32>)