Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp =================================================================== --- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -505,6 +505,11 @@ /// Fix the vectorized code, taking care of header phi's, live-outs, and more. void fixVectorizedLoop(VPTransformState &State, VPlan &Plan); + /// Replace the symbolic stride with const value in vector region. + void + replaceSCEVChecks(VPlan &Plan, + SmallDenseMap &VPBB2IRBB); + // Return true if any runtime check is added. bool areSafetyChecksAdded() { return AddedSafetyChecks; } @@ -1933,6 +1938,7 @@ SCEVExpander MemCheckExp; bool CostTooHigh = false; + bool HasSCEVChecks = false; public: GeneratedRTChecks(ScalarEvolution &SE, DominatorTree *DT, LoopInfo *LI, @@ -1970,6 +1976,7 @@ SCEVCheckCond = SCEVExp.expandCodeForPredicate( &UnionPred, SCEVCheckBlock->getTerminator()); + HasSCEVChecks = true; } const auto &RtPtrChecking = *LAI.getRuntimePointerChecking(); @@ -2031,6 +2038,8 @@ } } + bool hasSCEVChecks() { return HasSCEVChecks; } + InstructionCost getCost() { if (SCEVCheckBlock || MemCheckBlock) LLVM_DEBUG(dbgs() << "Calculating cost of runtime checks:\n"); @@ -3768,6 +3777,30 @@ VF.getKnownMinValue() * UF); } +void InnerLoopVectorizer::replaceSCEVChecks( + VPlan &Plan, SmallDenseMap &VPBB2IRBB) { + const SCEVPredicate &Pred = PSE.getPredicate(); + assert(Pred.getKind() == SCEVPredicate::P_Union && + "Expected Union predicate for SCEV checks"); + const SCEVUnionPredicate &Union = cast(Pred); + SCEVExpander Exp(*PSE.getSE(), PSE.getSE()->getDataLayout(), "SCEV checks"); + for (const auto *Check : Union.getPredicates()) + if (const SCEVComparePredicate *Compare = + dyn_cast(Check)) { + // The symbolic stride is compared with constant value in LAA. + if (Compare->getLHS()->getSCEVType() == scUnknown && + Compare->getRHS()->getSCEVType() == scConstant) { + Value *StrideVal = + Exp.expandCodeFor(Compare->getLHS(), Compare->getLHS()->getType(), + LoopVectorPreHeader->getTerminator()); + Value *CT = + Exp.expandCodeFor(Compare->getRHS(), Compare->getRHS()->getType(), + LoopVectorPreHeader->getTerminator()); + Plan.getVectorLoopRegion()->replaceAllUses(StrideVal, CT, VPBB2IRBB); + } + } +} + void InnerLoopVectorizer::fixCrossIterationPHIs(VPTransformState &State) { // In order to support recurrences we need to be able to vectorize Phi nodes. // Phi nodes have cycles, so we need to vectorize them in two stages. This is @@ -7750,6 +7783,11 @@ // predication, updating analyses. ILV.fixVectorizedLoop(State, BestVPlan); + // 4. Replace the symbolic stride with const value in vector region. This + // depends on the GVN pass, but it is run before LV pass. So, do it here. + if (ILV.RTChecks.hasSCEVChecks()) + ILV.replaceSCEVChecks(BestVPlan, State.CFG.VPBB2IRBB); + ILV.printDebugTracesAtEnd(); } Index: llvm/lib/Transforms/Vectorize/VPlan.h =================================================================== --- llvm/lib/Transforms/Vectorize/VPlan.h +++ llvm/lib/Transforms/Vectorize/VPlan.h @@ -2154,6 +2154,9 @@ /// this VPRegionBlock, thereby "executing" the VPlan. void execute(VPTransformState *State) override; + void replaceAllUses(Value *OldValue, Value *NewValue, + SmallDenseMap &VPBB2IRBB); + void dropAllReferences(VPValue *NewValue) override; #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) Index: llvm/lib/Transforms/Vectorize/VPlan.cpp =================================================================== --- llvm/lib/Transforms/Vectorize/VPlan.cpp +++ llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -513,6 +513,18 @@ Block->dropAllReferences(NewValue); } +void VPRegionBlock::replaceAllUses( + Value *OldValue, Value *NewValue, + SmallDenseMap &VPBB2IRBB) { + for (VPBlockBase *Block : vp_depth_first_shallow(Entry)) { + BasicBlock *BB = VPBB2IRBB[cast(Block)]; + OldValue->replaceUsesWithIf(NewValue, [BB](Use &U) { + auto *I = dyn_cast(U.getUser()); + return I && I->getParent() == BB; + }); + } +} + void VPRegionBlock::execute(VPTransformState *State) { ReversePostOrderTraversal> RPOT(Entry); Index: llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll =================================================================== --- llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll +++ llvm/test/Transforms/LoopVectorize/ARM/mve-gather-scatter-tailpred.ll @@ -341,7 +341,7 @@ ; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0 ; CHECK-NEXT: [[ACTIVE_LANE_MASK:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 [[TMP0]], i32 [[N]]) -; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[TMP0]], [[STRIDE]] +; CHECK-NEXT: [[TMP1:%.*]] = mul nuw nsw i32 [[TMP0]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[DATA:%.*]], i32 [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i32 0 Index: llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll =================================================================== --- llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll +++ llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll @@ -222,7 +222,7 @@ ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP6:%.*]] = mul nuw nsw i64 [[TMP5]], [[STRIDE]] +; CHECK-NEXT: [[TMP6:%.*]] = mul nuw nsw i64 [[TMP5]], 1 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP8]], align 4 @@ -290,8 +290,8 @@ ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[STRIDE]] -; CHECK-NEXT: [[TMP5:%.*]] = mul i64 0, [[STRIDE]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = mul i64 0, 1 ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 0 @@ -408,7 +408,7 @@ ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw i64 [[TMP9]], [[STRIDE]] +; CHECK-NEXT: [[TMP10:%.*]] = mul nuw nsw i64 [[TMP9]], 1 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[P]], i64 [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[TMP11]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP12]], align 4 @@ -480,8 +480,8 @@ ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[STRIDE]] -; CHECK-NEXT: [[TMP5:%.*]] = mul i64 0, [[STRIDE]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP5:%.*]] = mul i64 0, 1 ; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], [[TMP5]] ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[P:%.*]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i32, ptr [[TMP7]], i32 0 Index: llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll =================================================================== --- llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll +++ llvm/test/Transforms/LoopVectorize/runtime-check-needed-but-empty.ll @@ -17,12 +17,12 @@ ; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32 -; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], [[X]] +; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[TMP4]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64 ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[A:%.*]], i64 [[TMP6]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[TMP7]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP8]], align 4 -; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP1]], [[X]] +; CHECK-NEXT: [[TMP9:%.*]] = mul i32 [[TMP1]], 1 ; CHECK-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP10]] ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[TMP11]], i32 0 Index: llvm/test/Transforms/LoopVectorize/version-mem-access.ll =================================================================== --- llvm/test/Transforms/LoopVectorize/version-mem-access.ll +++ llvm/test/Transforms/LoopVectorize/version-mem-access.ll @@ -16,6 +16,7 @@ %cmp13 = icmp eq i32 %N, 0 br i1 %cmp13, label %for.end, label %for.body.preheader +; CHECK: vector.scevcheck ; CHECK-DAG: icmp ne i64 %AStride, 1 ; CHECK-DAG: icmp ne i32 %BStride, 1 ; CHECK-DAG: icmp ne i64 %CStride, 1 @@ -24,7 +25,17 @@ ; CHECK: br ; CHECK: vector.body +; CHECK: mul i32 %{{.*}}, 1 ; CHECK: load <2 x i32> +; CHECK: mul nsw i64 %{{.*}}, 1 +; CHECK: load <2 x i32> +; CHECK: mul nsw i64 %{{.*}}, 1 +; CHECK: store <2 x i32> + +; CHECK: for.body +; CHECK-DAG: mul i32 %{{.*}}, %BStride +; CHECK-DAG: mul nsw i64 %{{.*}}, %CStride +; CHECK-DAG: mul nsw i64 %{{.*}}, %AStride for.body.preheader: br label %for.body @@ -60,8 +71,16 @@ ; PR18480 ; CHECK-LABEL: fn1 +; CHECK: vector.scevcheck +; CHECK: icmp ne i32 %[[conv:.*]], 1 + +; CHECK: vector.body +; CHECK: mul nsw i32 %{{.*}}, 1 ; CHECK: load <2 x double> +; CHECK: for.body +; CHECK: mul nsw i32 %{{.*}}, %[[conv]] + define void @fn1(ptr noalias %x, ptr noalias %c, double %a) { entry: %conv = fptosi double %a to i32