[clang-format] Handle Verilog struct literals

[sstwcw]

Summary

Previously isVerilogIdentifier was mistaking the apostrophe used in
struct literals as an identifier. It is fixed.

clang/lib/Format/Format.cpp

FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) {
   case FormatStyle::LK_TableGen:
     LLVMStyle.SpacesInContainerLiterals = false;
     break;
   case FormatStyle::LK_Json:
     LLVMStyle.ColumnLimit = 0;
     break;
   case FormatStyle::LK_Verilog:
     LLVMStyle.IndentCaseLabels = true;
+    LLVMStyle.SpacesInContainerLiterals = false;
     break;
   default:
     break;
   }
 
   return LLVMStyle;
 }
 

clang/lib/Format/FormatToken.h

bool isVerilogIdentifier(const FormatToken &Tok) const {
     case tok::kw_struct:
     case tok::kw_typedef:
     case tok::kw_union:
     case tok::kw_unsigned:
     case tok::kw_virtual:
     case tok::kw_while:
       return false;
     case tok::identifier:
-      return VerilogExtraKeywords.find(Tok.Tok.getIdentifierInfo()) ==
+      return isWordLike(Tok) &&
+             VerilogExtraKeywords.find(Tok.Tok.getIdentifierInfo()) ==
                  VerilogExtraKeywords.end();
     default:
       // getIdentifierInfo returns non-null for both identifiers and keywords.
       return Tok.Tok.getIdentifierInfo();
     }
   }
 
   /// Returns whether \p Tok is a Verilog preprocessor directive.  This is
   /// needed because macro expansions start with a backtick as well and they

clang/unittests/Format/FormatTestVerilog.cpp

TEST_F(FormatTestVerilog, Streaming) {
   verifyFormat("{>>{a, b, c}} = 23'b1;");
   verifyFormat("{>>{a, b, c}} = x;");
   verifyFormat("{>>{j}} = x;");
   verifyFormat("{>>byte{j}} = x;");
   verifyFormat("{<<{j}} = x;");
   verifyFormat("{<<byte{j}} = x;");
 }
 
+TEST_F(FormatTestVerilog, StructLiteral) {
+  verifyFormat("c = '{0, 0.0};");
+  verifyFormat("c = '{'{1, 1.0}, '{2, 2.0}};");
+  verifyFormat("c = '{a: 0, b: 0.0};");
+  verifyFormat("c = '{a: 0, b: 0.0, default: 0};");
+  verifyFormat("c = ab'{a: 0, b: 0.0};");
+  verifyFormat("c = ab'{cd: cd'{1, 1.0}, ef: ef'{2, 2.0}};");
+  verifyFormat("c = ab'{cd'{1, 1.0}, ef'{2, 2.0}};");
+  verifyFormat("d = {int: 1, shortreal: 1.0};");
+  verifyFormat("d = ab'{int: 1, shortreal: 1.0};");
+  verifyFormat("c = '{default: 0};");
+  auto Style = getDefaultStyle();
+  Style.SpacesInContainerLiterals = true;
+  verifyFormat("c = '{a : 0, b : 0.0};", Style);
+  verifyFormat("c = '{a : 0, b : 0.0, default : 0};", Style);
+  verifyFormat("c = ab'{a : 0, b : 0.0};", Style);
+  verifyFormat("c = ab'{cd : cd'{1, 1.0}, ef : ef'{2, 2.0}};", Style);
+}
+
 TEST_F(FormatTestVerilog, StructuredProcedure) {
   // Blocks should be indented correctly.
   verifyFormat("initial begin\n"
                "end");
   verifyFormat("initial begin\n"
                "  x <= x;\n"
                "  x <= x;\n"
                "end");