diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -156,23 +156,24 @@ let PseudoInstr = opName # offsets.Variant; } -multiclass SM_Pseudo_Loads { + defvar opName = !tolower(NAME); def _IMM : SM_Load_Pseudo ; def _SGPR : SM_Load_Pseudo ; def _SGPR_IMM : SM_Load_Pseudo ; } -multiclass SM_Pseudo_Stores { +multiclass SM_Pseudo_Stores { + defvar opName = !tolower(NAME); def _IMM : SM_Store_Pseudo ; def _SGPR : SM_Store_Pseudo ; def _SGPR_IMM : SM_Store_Pseudo ; } -multiclass SM_Pseudo_Discards { +multiclass SM_Pseudo_Discards { + defvar opName = !tolower(NAME); def _IMM : SM_Discard_Pseudo ; def _SGPR : SM_Discard_Pseudo ; def _SGPR_IMM : SM_Discard_Pseudo ; @@ -197,7 +198,8 @@ let has_sbase = 0; } -multiclass SM_Pseudo_Probe { +multiclass SM_Pseudo_Probe { + defvar opName = !tolower(NAME); def _IMM : SM_Probe_Pseudo ; def _SGPR : SM_Probe_Pseudo ; def _SGPR_IMM : SM_Probe_Pseudo ; @@ -263,9 +265,9 @@ let DisableEncoding = !if(isRet, "$sdata", ""); } -multiclass SM_Pseudo_Atomics { + defvar opName = !tolower(NAME); def _IMM : SM_Pseudo_Atomic ; def _SGPR : SM_Pseudo_Atomic ; def _SGPR_IMM : SM_Pseudo_Atomic ; @@ -284,53 +286,31 @@ // XXX - SMEM instructions do not allow exec for data operand, but // does sdst for SMRD on SI/CI? -defm S_LOAD_DWORD : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0_XEXEC>; -defm S_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64_XEXEC>; -defm S_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>; -defm S_LOAD_DWORDX8 : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>; -defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>; +defm S_LOAD_DWORD : SM_Pseudo_Loads ; +defm S_LOAD_DWORDX2 : SM_Pseudo_Loads ; +defm S_LOAD_DWORDX4 : SM_Pseudo_Loads ; +defm S_LOAD_DWORDX8 : SM_Pseudo_Loads ; +defm S_LOAD_DWORDX16 : SM_Pseudo_Loads ; let is_buffer = 1 in { -defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads < - "s_buffer_load_dword", SReg_128, SReg_32_XM0_XEXEC ->; - +defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads ; // FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on // SI/CI, bit disallowed for SMEM on VI. -defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads < - "s_buffer_load_dwordx2", SReg_128, SReg_64_XEXEC ->; - -defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads < - "s_buffer_load_dwordx4", SReg_128, SReg_128 ->; - -defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads < - "s_buffer_load_dwordx8", SReg_128, SReg_256 ->; - -defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads < - "s_buffer_load_dwordx16", SReg_128, SReg_512 ->; +defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads ; +defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads ; +defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads ; +defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads ; } let SubtargetPredicate = HasScalarStores in { -defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>; -defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>; -defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>; +defm S_STORE_DWORD : SM_Pseudo_Stores ; +defm S_STORE_DWORDX2 : SM_Pseudo_Stores ; +defm S_STORE_DWORDX4 : SM_Pseudo_Stores ; let is_buffer = 1 in { -defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores < - "s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC ->; - -defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores < - "s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC ->; - -defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores < - "s_buffer_store_dwordx4", SReg_128, SReg_128 ->; +defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores ; +defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores ; +defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores ; } } // End SubtargetPredicate = HasScalarStores @@ -348,9 +328,9 @@ def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>; } // End OtherPredicates = [HasScalarStores] -defm S_ATC_PROBE : SM_Pseudo_Probe <"s_atc_probe", SReg_64>; +defm S_ATC_PROBE : SM_Pseudo_Probe ; let is_buffer = 1 in { -defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe <"s_atc_probe_buffer", SReg_128>; +defm S_ATC_PROBE_BUFFER : SM_Pseudo_Probe ; } } // SubtargetPredicate = isGFX8Plus @@ -364,80 +344,80 @@ let SubtargetPredicate = HasScalarFlatScratchInsts, Uses = [FLAT_SCR] in { -defm S_SCRATCH_LOAD_DWORD : SM_Pseudo_Loads <"s_scratch_load_dword", SReg_64, SReg_32_XM0_XEXEC>; -defm S_SCRATCH_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_scratch_load_dwordx2", SReg_64, SReg_64_XEXEC>; -defm S_SCRATCH_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_scratch_load_dwordx4", SReg_64, SReg_128>; +defm S_SCRATCH_LOAD_DWORD : SM_Pseudo_Loads < SReg_64, SReg_32_XM0_XEXEC>; +defm S_SCRATCH_LOAD_DWORDX2 : SM_Pseudo_Loads ; +defm S_SCRATCH_LOAD_DWORDX4 : SM_Pseudo_Loads ; -defm S_SCRATCH_STORE_DWORD : SM_Pseudo_Stores <"s_scratch_store_dword", SReg_64, SReg_32_XM0_XEXEC>; -defm S_SCRATCH_STORE_DWORDX2 : SM_Pseudo_Stores <"s_scratch_store_dwordx2", SReg_64, SReg_64_XEXEC>; -defm S_SCRATCH_STORE_DWORDX4 : SM_Pseudo_Stores <"s_scratch_store_dwordx4", SReg_64, SReg_128>; +defm S_SCRATCH_STORE_DWORD : SM_Pseudo_Stores < SReg_64, SReg_32_XM0_XEXEC>; +defm S_SCRATCH_STORE_DWORDX2 : SM_Pseudo_Stores ; +defm S_SCRATCH_STORE_DWORDX4 : SM_Pseudo_Stores ; } // SubtargetPredicate = HasScalarFlatScratchInsts let SubtargetPredicate = HasScalarAtomics in { let is_buffer = 1 in { -defm S_BUFFER_ATOMIC_SWAP : SM_Pseudo_Atomics <"s_buffer_atomic_swap", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_CMPSWAP : SM_Pseudo_Atomics <"s_buffer_atomic_cmpswap", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_ADD : SM_Pseudo_Atomics <"s_buffer_atomic_add", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_SUB : SM_Pseudo_Atomics <"s_buffer_atomic_sub", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_SMIN : SM_Pseudo_Atomics <"s_buffer_atomic_smin", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_UMIN : SM_Pseudo_Atomics <"s_buffer_atomic_umin", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_SMAX : SM_Pseudo_Atomics <"s_buffer_atomic_smax", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_UMAX : SM_Pseudo_Atomics <"s_buffer_atomic_umax", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_AND : SM_Pseudo_Atomics <"s_buffer_atomic_and", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_OR : SM_Pseudo_Atomics <"s_buffer_atomic_or", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_XOR : SM_Pseudo_Atomics <"s_buffer_atomic_xor", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_INC : SM_Pseudo_Atomics <"s_buffer_atomic_inc", SReg_128, SReg_32_XM0_XEXEC>; -defm S_BUFFER_ATOMIC_DEC : SM_Pseudo_Atomics <"s_buffer_atomic_dec", SReg_128, SReg_32_XM0_XEXEC>; - -defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_swap_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_cmpswap_x2", SReg_128, SReg_128>; -defm S_BUFFER_ATOMIC_ADD_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_add_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_SUB_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_sub_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_smin_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_umin_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_smax_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_umax_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_AND_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_and_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_OR_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_or_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_XOR_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_xor_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_INC_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_inc_x2", SReg_128, SReg_64_XEXEC>; -defm S_BUFFER_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_buffer_atomic_dec_x2", SReg_128, SReg_64_XEXEC>; +defm S_BUFFER_ATOMIC_SWAP : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_CMPSWAP : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_ADD : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_SUB : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_SMIN : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_UMIN : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_SMAX : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_UMAX : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_AND : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_OR : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_XOR : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_INC : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_DEC : SM_Pseudo_Atomics ; + +defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_ADD_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_SUB_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_AND_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_OR_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_XOR_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_INC_X2 : SM_Pseudo_Atomics ; +defm S_BUFFER_ATOMIC_DEC_X2 : SM_Pseudo_Atomics ; } -defm S_ATOMIC_SWAP : SM_Pseudo_Atomics <"s_atomic_swap", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_CMPSWAP : SM_Pseudo_Atomics <"s_atomic_cmpswap", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_ADD : SM_Pseudo_Atomics <"s_atomic_add", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_SUB : SM_Pseudo_Atomics <"s_atomic_sub", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_SMIN : SM_Pseudo_Atomics <"s_atomic_smin", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_UMIN : SM_Pseudo_Atomics <"s_atomic_umin", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_SMAX : SM_Pseudo_Atomics <"s_atomic_smax", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_UMAX : SM_Pseudo_Atomics <"s_atomic_umax", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_AND : SM_Pseudo_Atomics <"s_atomic_and", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_OR : SM_Pseudo_Atomics <"s_atomic_or", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_XOR : SM_Pseudo_Atomics <"s_atomic_xor", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_INC : SM_Pseudo_Atomics <"s_atomic_inc", SReg_64, SReg_32_XM0_XEXEC>; -defm S_ATOMIC_DEC : SM_Pseudo_Atomics <"s_atomic_dec", SReg_64, SReg_32_XM0_XEXEC>; - -defm S_ATOMIC_SWAP_X2 : SM_Pseudo_Atomics <"s_atomic_swap_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_CMPSWAP_X2 : SM_Pseudo_Atomics <"s_atomic_cmpswap_x2", SReg_64, SReg_128>; -defm S_ATOMIC_ADD_X2 : SM_Pseudo_Atomics <"s_atomic_add_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_SUB_X2 : SM_Pseudo_Atomics <"s_atomic_sub_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_SMIN_X2 : SM_Pseudo_Atomics <"s_atomic_smin_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_UMIN_X2 : SM_Pseudo_Atomics <"s_atomic_umin_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_SMAX_X2 : SM_Pseudo_Atomics <"s_atomic_smax_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_UMAX_X2 : SM_Pseudo_Atomics <"s_atomic_umax_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_AND_X2 : SM_Pseudo_Atomics <"s_atomic_and_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_OR_X2 : SM_Pseudo_Atomics <"s_atomic_or_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_XOR_X2 : SM_Pseudo_Atomics <"s_atomic_xor_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_INC_X2 : SM_Pseudo_Atomics <"s_atomic_inc_x2", SReg_64, SReg_64_XEXEC>; -defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics <"s_atomic_dec_x2", SReg_64, SReg_64_XEXEC>; +defm S_ATOMIC_SWAP : SM_Pseudo_Atomics ; +defm S_ATOMIC_CMPSWAP : SM_Pseudo_Atomics ; +defm S_ATOMIC_ADD : SM_Pseudo_Atomics ; +defm S_ATOMIC_SUB : SM_Pseudo_Atomics ; +defm S_ATOMIC_SMIN : SM_Pseudo_Atomics ; +defm S_ATOMIC_UMIN : SM_Pseudo_Atomics ; +defm S_ATOMIC_SMAX : SM_Pseudo_Atomics ; +defm S_ATOMIC_UMAX : SM_Pseudo_Atomics ; +defm S_ATOMIC_AND : SM_Pseudo_Atomics ; +defm S_ATOMIC_OR : SM_Pseudo_Atomics ; +defm S_ATOMIC_XOR : SM_Pseudo_Atomics ; +defm S_ATOMIC_INC : SM_Pseudo_Atomics ; +defm S_ATOMIC_DEC : SM_Pseudo_Atomics ; + +defm S_ATOMIC_SWAP_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_CMPSWAP_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_ADD_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_SUB_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_SMIN_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_UMIN_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_SMAX_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_UMAX_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_AND_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_OR_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_XOR_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_INC_X2 : SM_Pseudo_Atomics ; +defm S_ATOMIC_DEC_X2 : SM_Pseudo_Atomics ; } // let SubtargetPredicate = HasScalarAtomics let SubtargetPredicate = HasScalarAtomics in { -defm S_DCACHE_DISCARD : SM_Pseudo_Discards <"s_dcache_discard">; -defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards <"s_dcache_discard_x2">; +defm S_DCACHE_DISCARD : SM_Pseudo_Discards; +defm S_DCACHE_DISCARD_X2 : SM_Pseudo_Discards; } //===----------------------------------------------------------------------===// @@ -464,7 +444,8 @@ let Inst{31-27} = 0x18; //encoding } -multiclass SM_Real_Loads_si op, string ps> { +multiclass SM_Real_Loads_si op> { + defvar ps = NAME; defvar immPs = !cast(ps#_IMM); def _IMM_si : SMRD_Real_si { let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, CPol:$cpol); @@ -474,16 +455,16 @@ def _SGPR_si : SMRD_Real_si ; } -defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">; -defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">; -defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">; -defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">; -defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">; -defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">; -defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">; -defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">; -defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">; -defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">; +defm S_LOAD_DWORD : SM_Real_Loads_si <0x00>; +defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01>; +defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02>; +defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03>; +defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04>; +defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08>; +defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09>; +defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a>; +defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b>; +defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c>; def S_MEMTIME_si : SMRD_Real_si <0x1e, S_MEMTIME>; def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>; @@ -551,7 +532,8 @@ string AsmVariantName = "NonParsable"; } -multiclass SM_Real_Loads_vi op, string ps> { +multiclass SM_Real_Loads_vi op> { + defvar ps = NAME; def _IMM_vi : SMEM_Real_Load_vi ; def _SGPR_vi : SMEM_Real_Load_vi ; def _SGPR_alt_gfx9 : SMEM_Real_Load_vi , @@ -571,7 +553,8 @@ class SMEM_Real_Store_vi op, string ps, OffsetMode offsets> : SMEM_Real_Store_Base_vi (ps # offsets.Variant)>; -multiclass SM_Real_Stores_vi op, string ps> { +multiclass SM_Real_Stores_vi op> { + defvar ps = NAME; def _IMM_vi : SMEM_Real_Store_vi ; def _SGPR_vi : SMEM_Real_Store_vi ; def _SGPR_alt_gfx9 : SMEM_Real_Store_vi , @@ -580,7 +563,8 @@ def _SGPR_IMM_gfx9 : SMEM_Real_Store_vi ; } -multiclass SM_Real_Probe_vi op, string ps> { +multiclass SM_Real_Probe_vi op> { + defvar ps = NAME; def _IMM_vi : SMEM_Real_Store_Base_vi (ps#_IMM)>; def _SGPR_vi : SMEM_Real_Store_Base_vi (ps#_SGPR)>; def _SGPR_alt_gfx9 @@ -591,24 +575,24 @@ : SMEM_Real_Store_Base_vi (ps#_SGPR_IMM)>; } -defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">; -defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">; -defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">; -defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">; -defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">; -defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">; -defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">; -defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">; -defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">; -defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">; - -defm S_STORE_DWORD : SM_Real_Stores_vi <0x10, "S_STORE_DWORD">; -defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11, "S_STORE_DWORDX2">; -defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12, "S_STORE_DWORDX4">; - -defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">; -defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">; -defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">; +defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00>; +defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01>; +defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02>; +defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03>; +defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04>; +defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08>; +defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09>; +defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a>; +defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b>; +defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c>; + +defm S_STORE_DWORD : SM_Real_Stores_vi <0x10>; +defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11>; +defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12>; + +defm S_BUFFER_STORE_DWORD : SM_Real_Stores_vi <0x18>; +defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_vi <0x19>; +defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_vi <0x1a>; // These instructions use same encoding def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>; @@ -618,16 +602,16 @@ def S_MEMTIME_vi : SMEM_Real_vi <0x24, S_MEMTIME>; def S_MEMREALTIME_vi : SMEM_Real_vi <0x25, S_MEMREALTIME>; -defm S_SCRATCH_LOAD_DWORD : SM_Real_Loads_vi <0x05, "S_SCRATCH_LOAD_DWORD">; -defm S_SCRATCH_LOAD_DWORDX2 : SM_Real_Loads_vi <0x06, "S_SCRATCH_LOAD_DWORDX2">; -defm S_SCRATCH_LOAD_DWORDX4 : SM_Real_Loads_vi <0x07, "S_SCRATCH_LOAD_DWORDX4">; +defm S_SCRATCH_LOAD_DWORD : SM_Real_Loads_vi <0x05>; +defm S_SCRATCH_LOAD_DWORDX2 : SM_Real_Loads_vi <0x06>; +defm S_SCRATCH_LOAD_DWORDX4 : SM_Real_Loads_vi <0x07>; -defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_vi <0x15, "S_SCRATCH_STORE_DWORD">; -defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_vi <0x16, "S_SCRATCH_STORE_DWORDX2">; -defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_vi <0x17, "S_SCRATCH_STORE_DWORDX4">; +defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_vi <0x15>; +defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_vi <0x16>; +defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_vi <0x17>; -defm S_ATC_PROBE : SM_Real_Probe_vi <0x26, "S_ATC_PROBE">; -defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27, "S_ATC_PROBE_BUFFER">; +defm S_ATC_PROBE : SM_Real_Probe_vi <0x26>; +defm S_ATC_PROBE_BUFFER : SM_Real_Probe_vi <0x27>; //===----------------------------------------------------------------------===// // GFX9 @@ -646,7 +630,8 @@ let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0}); } -multiclass SM_Real_Atomics_vi op, string ps> { +multiclass SM_Real_Atomics_vi op> { + defvar ps = NAME; def _IMM_vi : SMEM_Atomic_Real_vi (ps#_IMM)>; def _SGPR_vi : SMEM_Atomic_Real_vi (ps#_SGPR)>; def _SGPR_alt_gfx9 @@ -665,63 +650,64 @@ : SMEM_Atomic_Real_vi (ps#_SGPR_IMM_RTN)>; } -defm S_BUFFER_ATOMIC_SWAP : SM_Real_Atomics_vi <0x40, "S_BUFFER_ATOMIC_SWAP">; -defm S_BUFFER_ATOMIC_CMPSWAP : SM_Real_Atomics_vi <0x41, "S_BUFFER_ATOMIC_CMPSWAP">; -defm S_BUFFER_ATOMIC_ADD : SM_Real_Atomics_vi <0x42, "S_BUFFER_ATOMIC_ADD">; -defm S_BUFFER_ATOMIC_SUB : SM_Real_Atomics_vi <0x43, "S_BUFFER_ATOMIC_SUB">; -defm S_BUFFER_ATOMIC_SMIN : SM_Real_Atomics_vi <0x44, "S_BUFFER_ATOMIC_SMIN">; -defm S_BUFFER_ATOMIC_UMIN : SM_Real_Atomics_vi <0x45, "S_BUFFER_ATOMIC_UMIN">; -defm S_BUFFER_ATOMIC_SMAX : SM_Real_Atomics_vi <0x46, "S_BUFFER_ATOMIC_SMAX">; -defm S_BUFFER_ATOMIC_UMAX : SM_Real_Atomics_vi <0x47, "S_BUFFER_ATOMIC_UMAX">; -defm S_BUFFER_ATOMIC_AND : SM_Real_Atomics_vi <0x48, "S_BUFFER_ATOMIC_AND">; -defm S_BUFFER_ATOMIC_OR : SM_Real_Atomics_vi <0x49, "S_BUFFER_ATOMIC_OR">; -defm S_BUFFER_ATOMIC_XOR : SM_Real_Atomics_vi <0x4a, "S_BUFFER_ATOMIC_XOR">; -defm S_BUFFER_ATOMIC_INC : SM_Real_Atomics_vi <0x4b, "S_BUFFER_ATOMIC_INC">; -defm S_BUFFER_ATOMIC_DEC : SM_Real_Atomics_vi <0x4c, "S_BUFFER_ATOMIC_DEC">; - -defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Real_Atomics_vi <0x60, "S_BUFFER_ATOMIC_SWAP_X2">; -defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_vi <0x61, "S_BUFFER_ATOMIC_CMPSWAP_X2">; -defm S_BUFFER_ATOMIC_ADD_X2 : SM_Real_Atomics_vi <0x62, "S_BUFFER_ATOMIC_ADD_X2">; -defm S_BUFFER_ATOMIC_SUB_X2 : SM_Real_Atomics_vi <0x63, "S_BUFFER_ATOMIC_SUB_X2">; -defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Real_Atomics_vi <0x64, "S_BUFFER_ATOMIC_SMIN_X2">; -defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Real_Atomics_vi <0x65, "S_BUFFER_ATOMIC_UMIN_X2">; -defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Real_Atomics_vi <0x66, "S_BUFFER_ATOMIC_SMAX_X2">; -defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Real_Atomics_vi <0x67, "S_BUFFER_ATOMIC_UMAX_X2">; -defm S_BUFFER_ATOMIC_AND_X2 : SM_Real_Atomics_vi <0x68, "S_BUFFER_ATOMIC_AND_X2">; -defm S_BUFFER_ATOMIC_OR_X2 : SM_Real_Atomics_vi <0x69, "S_BUFFER_ATOMIC_OR_X2">; -defm S_BUFFER_ATOMIC_XOR_X2 : SM_Real_Atomics_vi <0x6a, "S_BUFFER_ATOMIC_XOR_X2">; -defm S_BUFFER_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0x6b, "S_BUFFER_ATOMIC_INC_X2">; -defm S_BUFFER_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0x6c, "S_BUFFER_ATOMIC_DEC_X2">; - -defm S_ATOMIC_SWAP : SM_Real_Atomics_vi <0x80, "S_ATOMIC_SWAP">; -defm S_ATOMIC_CMPSWAP : SM_Real_Atomics_vi <0x81, "S_ATOMIC_CMPSWAP">; -defm S_ATOMIC_ADD : SM_Real_Atomics_vi <0x82, "S_ATOMIC_ADD">; -defm S_ATOMIC_SUB : SM_Real_Atomics_vi <0x83, "S_ATOMIC_SUB">; -defm S_ATOMIC_SMIN : SM_Real_Atomics_vi <0x84, "S_ATOMIC_SMIN">; -defm S_ATOMIC_UMIN : SM_Real_Atomics_vi <0x85, "S_ATOMIC_UMIN">; -defm S_ATOMIC_SMAX : SM_Real_Atomics_vi <0x86, "S_ATOMIC_SMAX">; -defm S_ATOMIC_UMAX : SM_Real_Atomics_vi <0x87, "S_ATOMIC_UMAX">; -defm S_ATOMIC_AND : SM_Real_Atomics_vi <0x88, "S_ATOMIC_AND">; -defm S_ATOMIC_OR : SM_Real_Atomics_vi <0x89, "S_ATOMIC_OR">; -defm S_ATOMIC_XOR : SM_Real_Atomics_vi <0x8a, "S_ATOMIC_XOR">; -defm S_ATOMIC_INC : SM_Real_Atomics_vi <0x8b, "S_ATOMIC_INC">; -defm S_ATOMIC_DEC : SM_Real_Atomics_vi <0x8c, "S_ATOMIC_DEC">; - -defm S_ATOMIC_SWAP_X2 : SM_Real_Atomics_vi <0xa0, "S_ATOMIC_SWAP_X2">; -defm S_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_vi <0xa1, "S_ATOMIC_CMPSWAP_X2">; -defm S_ATOMIC_ADD_X2 : SM_Real_Atomics_vi <0xa2, "S_ATOMIC_ADD_X2">; -defm S_ATOMIC_SUB_X2 : SM_Real_Atomics_vi <0xa3, "S_ATOMIC_SUB_X2">; -defm S_ATOMIC_SMIN_X2 : SM_Real_Atomics_vi <0xa4, "S_ATOMIC_SMIN_X2">; -defm S_ATOMIC_UMIN_X2 : SM_Real_Atomics_vi <0xa5, "S_ATOMIC_UMIN_X2">; -defm S_ATOMIC_SMAX_X2 : SM_Real_Atomics_vi <0xa6, "S_ATOMIC_SMAX_X2">; -defm S_ATOMIC_UMAX_X2 : SM_Real_Atomics_vi <0xa7, "S_ATOMIC_UMAX_X2">; -defm S_ATOMIC_AND_X2 : SM_Real_Atomics_vi <0xa8, "S_ATOMIC_AND_X2">; -defm S_ATOMIC_OR_X2 : SM_Real_Atomics_vi <0xa9, "S_ATOMIC_OR_X2">; -defm S_ATOMIC_XOR_X2 : SM_Real_Atomics_vi <0xaa, "S_ATOMIC_XOR_X2">; -defm S_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0xab, "S_ATOMIC_INC_X2">; -defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0xac, "S_ATOMIC_DEC_X2">; - -multiclass SM_Real_Discard_vi op, string ps> { +defm S_BUFFER_ATOMIC_SWAP : SM_Real_Atomics_vi <0x40>; +defm S_BUFFER_ATOMIC_CMPSWAP : SM_Real_Atomics_vi <0x41>; +defm S_BUFFER_ATOMIC_ADD : SM_Real_Atomics_vi <0x42>; +defm S_BUFFER_ATOMIC_SUB : SM_Real_Atomics_vi <0x43>; +defm S_BUFFER_ATOMIC_SMIN : SM_Real_Atomics_vi <0x44>; +defm S_BUFFER_ATOMIC_UMIN : SM_Real_Atomics_vi <0x45>; +defm S_BUFFER_ATOMIC_SMAX : SM_Real_Atomics_vi <0x46>; +defm S_BUFFER_ATOMIC_UMAX : SM_Real_Atomics_vi <0x47>; +defm S_BUFFER_ATOMIC_AND : SM_Real_Atomics_vi <0x48>; +defm S_BUFFER_ATOMIC_OR : SM_Real_Atomics_vi <0x49>; +defm S_BUFFER_ATOMIC_XOR : SM_Real_Atomics_vi <0x4a>; +defm S_BUFFER_ATOMIC_INC : SM_Real_Atomics_vi <0x4b>; +defm S_BUFFER_ATOMIC_DEC : SM_Real_Atomics_vi <0x4c>; + +defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Real_Atomics_vi <0x60>; +defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_vi <0x61>; +defm S_BUFFER_ATOMIC_ADD_X2 : SM_Real_Atomics_vi <0x62>; +defm S_BUFFER_ATOMIC_SUB_X2 : SM_Real_Atomics_vi <0x63>; +defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Real_Atomics_vi <0x64>; +defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Real_Atomics_vi <0x65>; +defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Real_Atomics_vi <0x66>; +defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Real_Atomics_vi <0x67>; +defm S_BUFFER_ATOMIC_AND_X2 : SM_Real_Atomics_vi <0x68>; +defm S_BUFFER_ATOMIC_OR_X2 : SM_Real_Atomics_vi <0x69>; +defm S_BUFFER_ATOMIC_XOR_X2 : SM_Real_Atomics_vi <0x6a>; +defm S_BUFFER_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0x6b>; +defm S_BUFFER_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0x6c>; + +defm S_ATOMIC_SWAP : SM_Real_Atomics_vi <0x80>; +defm S_ATOMIC_CMPSWAP : SM_Real_Atomics_vi <0x81>; +defm S_ATOMIC_ADD : SM_Real_Atomics_vi <0x82>; +defm S_ATOMIC_SUB : SM_Real_Atomics_vi <0x83>; +defm S_ATOMIC_SMIN : SM_Real_Atomics_vi <0x84>; +defm S_ATOMIC_UMIN : SM_Real_Atomics_vi <0x85>; +defm S_ATOMIC_SMAX : SM_Real_Atomics_vi <0x86>; +defm S_ATOMIC_UMAX : SM_Real_Atomics_vi <0x87>; +defm S_ATOMIC_AND : SM_Real_Atomics_vi <0x88>; +defm S_ATOMIC_OR : SM_Real_Atomics_vi <0x89>; +defm S_ATOMIC_XOR : SM_Real_Atomics_vi <0x8a>; +defm S_ATOMIC_INC : SM_Real_Atomics_vi <0x8b>; +defm S_ATOMIC_DEC : SM_Real_Atomics_vi <0x8c>; + +defm S_ATOMIC_SWAP_X2 : SM_Real_Atomics_vi <0xa0>; +defm S_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_vi <0xa1>; +defm S_ATOMIC_ADD_X2 : SM_Real_Atomics_vi <0xa2>; +defm S_ATOMIC_SUB_X2 : SM_Real_Atomics_vi <0xa3>; +defm S_ATOMIC_SMIN_X2 : SM_Real_Atomics_vi <0xa4>; +defm S_ATOMIC_UMIN_X2 : SM_Real_Atomics_vi <0xa5>; +defm S_ATOMIC_SMAX_X2 : SM_Real_Atomics_vi <0xa6>; +defm S_ATOMIC_UMAX_X2 : SM_Real_Atomics_vi <0xa7>; +defm S_ATOMIC_AND_X2 : SM_Real_Atomics_vi <0xa8>; +defm S_ATOMIC_OR_X2 : SM_Real_Atomics_vi <0xa9>; +defm S_ATOMIC_XOR_X2 : SM_Real_Atomics_vi <0xaa>; +defm S_ATOMIC_INC_X2 : SM_Real_Atomics_vi <0xab>; +defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_vi <0xac>; + +multiclass SM_Real_Discard_vi op> { + defvar ps = NAME; def _IMM_vi : SMEM_Real_vi (ps#_IMM)>; def _SGPR_vi : SMEM_Real_vi (ps#_SGPR)>; def _SGPR_alt_gfx9 : SMEM_Real_vi (ps#_SGPR)>, @@ -730,8 +716,8 @@ def _SGPR_IMM_gfx9 : SMEM_Real_vi (ps#_SGPR_IMM)>; } -defm S_DCACHE_DISCARD : SM_Real_Discard_vi <0x28, "S_DCACHE_DISCARD">; -defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_vi <0x29, "S_DCACHE_DISCARD_X2">; +defm S_DCACHE_DISCARD : SM_Real_Discard_vi <0x28>; +defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_vi <0x29>; //===----------------------------------------------------------------------===// // CI @@ -971,7 +957,8 @@ class SMEM_Real_Load_gfx10 op, string ps, OffsetMode offsets> : SMEM_Real_gfx10(ps # offsets.Variant)>; -multiclass SM_Real_Loads_gfx10 op, string ps> { +multiclass SM_Real_Loads_gfx10 op> { + defvar ps = NAME; def _IMM_gfx10 : SMEM_Real_Load_gfx10; def _SGPR_gfx10 : SMEM_Real_Load_gfx10; def _SGPR_IMM_gfx10 : SMEM_Real_Load_gfx10; @@ -984,7 +971,8 @@ let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?); } -multiclass SM_Real_Stores_gfx10 op, string ps> { +multiclass SM_Real_Stores_gfx10 op> { + defvar ps = NAME; defvar immPs = !cast(ps#_IMM); def _IMM_gfx10 : SMEM_Real_Store_gfx10 ; @@ -995,36 +983,36 @@ def _SGPR_IMM_gfx10 : SMEM_Real_Store_gfx10 ; } -defm S_LOAD_DWORD : SM_Real_Loads_gfx10<0x000, "S_LOAD_DWORD">; -defm S_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x001, "S_LOAD_DWORDX2">; -defm S_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x002, "S_LOAD_DWORDX4">; -defm S_LOAD_DWORDX8 : SM_Real_Loads_gfx10<0x003, "S_LOAD_DWORDX8">; -defm S_LOAD_DWORDX16 : SM_Real_Loads_gfx10<0x004, "S_LOAD_DWORDX16">; +defm S_LOAD_DWORD : SM_Real_Loads_gfx10<0x000>; +defm S_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x001>; +defm S_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x002>; +defm S_LOAD_DWORDX8 : SM_Real_Loads_gfx10<0x003>; +defm S_LOAD_DWORDX16 : SM_Real_Loads_gfx10<0x004>; let SubtargetPredicate = HasScalarFlatScratchInsts in { -defm S_SCRATCH_LOAD_DWORD : SM_Real_Loads_gfx10<0x005, "S_SCRATCH_LOAD_DWORD">; -defm S_SCRATCH_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x006, "S_SCRATCH_LOAD_DWORDX2">; -defm S_SCRATCH_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x007, "S_SCRATCH_LOAD_DWORDX4">; +defm S_SCRATCH_LOAD_DWORD : SM_Real_Loads_gfx10<0x005>; +defm S_SCRATCH_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x006>; +defm S_SCRATCH_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x007>; } // End SubtargetPredicate = HasScalarFlatScratchInsts -defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_gfx10<0x008, "S_BUFFER_LOAD_DWORD">; -defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x009, "S_BUFFER_LOAD_DWORDX2">; -defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x00a, "S_BUFFER_LOAD_DWORDX4">; -defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_gfx10<0x00b, "S_BUFFER_LOAD_DWORDX8">; -defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_gfx10<0x00c, "S_BUFFER_LOAD_DWORDX16">; +defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_gfx10<0x008>; +defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_gfx10<0x009>; +defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_gfx10<0x00a>; +defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_gfx10<0x00b>; +defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_gfx10<0x00c>; let SubtargetPredicate = HasScalarStores in { -defm S_STORE_DWORD : SM_Real_Stores_gfx10<0x010, "S_STORE_DWORD">; -defm S_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x011, "S_STORE_DWORDX2">; -defm S_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x012, "S_STORE_DWORDX4">; +defm S_STORE_DWORD : SM_Real_Stores_gfx10<0x010>; +defm S_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x011>; +defm S_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x012>; let OtherPredicates = [HasScalarFlatScratchInsts] in { -defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_gfx10<0x015, "S_SCRATCH_STORE_DWORD">; -defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x016, "S_SCRATCH_STORE_DWORDX2">; -defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x017, "S_SCRATCH_STORE_DWORDX4">; +defm S_SCRATCH_STORE_DWORD : SM_Real_Stores_gfx10<0x015>; +defm S_SCRATCH_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x016>; +defm S_SCRATCH_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x017>; } // End OtherPredicates = [HasScalarFlatScratchInsts] -defm S_BUFFER_STORE_DWORD : SM_Real_Stores_gfx10<0x018, "S_BUFFER_STORE_DWORD">; -defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x019, "S_BUFFER_STORE_DWORDX2">; -defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x01a, "S_BUFFER_STORE_DWORDX4">; +defm S_BUFFER_STORE_DWORD : SM_Real_Stores_gfx10<0x018>; +defm S_BUFFER_STORE_DWORDX2 : SM_Real_Stores_gfx10<0x019>; +defm S_BUFFER_STORE_DWORDX4 : SM_Real_Stores_gfx10<0x01a>; } // End SubtargetPredicate = HasScalarStores def S_MEMREALTIME_gfx10 : SMEM_Real_gfx10<0x025, S_MEMREALTIME>; @@ -1037,15 +1025,16 @@ def S_DCACHE_WB_gfx10 : SMEM_Real_gfx10<0x021, S_DCACHE_WB>; } // End SubtargetPredicate = HasScalarStores -multiclass SM_Real_Probe_gfx10 op, string ps> { +multiclass SM_Real_Probe_gfx10 op> { + defvar ps = NAME; def _IMM_gfx10 : SMEM_Real_Store_gfx10 (ps#_IMM)>; def _SGPR_gfx10 : SMEM_Real_Store_gfx10 (ps#_SGPR)>; def _SGPR_IMM_gfx10 : SMEM_Real_Store_gfx10 (ps#_SGPR_IMM)>; } -defm S_ATC_PROBE : SM_Real_Probe_gfx10 <0x26, "S_ATC_PROBE">; -defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx10 <0x27, "S_ATC_PROBE_BUFFER">; +defm S_ATC_PROBE : SM_Real_Probe_gfx10 <0x26>; +defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx10 <0x27>; class SMEM_Atomic_Real_gfx10 op, SM_Atomic_Pseudo ps> : SMEM_Real_gfx10 , @@ -1062,7 +1051,8 @@ let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0}); } -multiclass SM_Real_Atomics_gfx10 op, string ps> { +multiclass SM_Real_Atomics_gfx10 op> { + defvar ps = NAME; def _IMM_gfx10 : SMEM_Atomic_Real_gfx10 (ps#_IMM)>; def _SGPR_gfx10 : SMEM_Atomic_Real_gfx10 (ps#_SGPR)>; def _SGPR_IMM_gfx10 : SMEM_Atomic_Real_gfx10 (ps#_SGPR_IMM)>; @@ -1073,70 +1063,71 @@ let SubtargetPredicate = HasScalarAtomics in { -defm S_BUFFER_ATOMIC_SWAP : SM_Real_Atomics_gfx10 <0x40, "S_BUFFER_ATOMIC_SWAP">; -defm S_BUFFER_ATOMIC_CMPSWAP : SM_Real_Atomics_gfx10 <0x41, "S_BUFFER_ATOMIC_CMPSWAP">; -defm S_BUFFER_ATOMIC_ADD : SM_Real_Atomics_gfx10 <0x42, "S_BUFFER_ATOMIC_ADD">; -defm S_BUFFER_ATOMIC_SUB : SM_Real_Atomics_gfx10 <0x43, "S_BUFFER_ATOMIC_SUB">; -defm S_BUFFER_ATOMIC_SMIN : SM_Real_Atomics_gfx10 <0x44, "S_BUFFER_ATOMIC_SMIN">; -defm S_BUFFER_ATOMIC_UMIN : SM_Real_Atomics_gfx10 <0x45, "S_BUFFER_ATOMIC_UMIN">; -defm S_BUFFER_ATOMIC_SMAX : SM_Real_Atomics_gfx10 <0x46, "S_BUFFER_ATOMIC_SMAX">; -defm S_BUFFER_ATOMIC_UMAX : SM_Real_Atomics_gfx10 <0x47, "S_BUFFER_ATOMIC_UMAX">; -defm S_BUFFER_ATOMIC_AND : SM_Real_Atomics_gfx10 <0x48, "S_BUFFER_ATOMIC_AND">; -defm S_BUFFER_ATOMIC_OR : SM_Real_Atomics_gfx10 <0x49, "S_BUFFER_ATOMIC_OR">; -defm S_BUFFER_ATOMIC_XOR : SM_Real_Atomics_gfx10 <0x4a, "S_BUFFER_ATOMIC_XOR">; -defm S_BUFFER_ATOMIC_INC : SM_Real_Atomics_gfx10 <0x4b, "S_BUFFER_ATOMIC_INC">; -defm S_BUFFER_ATOMIC_DEC : SM_Real_Atomics_gfx10 <0x4c, "S_BUFFER_ATOMIC_DEC">; - -defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Real_Atomics_gfx10 <0x60, "S_BUFFER_ATOMIC_SWAP_X2">; -defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_gfx10 <0x61, "S_BUFFER_ATOMIC_CMPSWAP_X2">; -defm S_BUFFER_ATOMIC_ADD_X2 : SM_Real_Atomics_gfx10 <0x62, "S_BUFFER_ATOMIC_ADD_X2">; -defm S_BUFFER_ATOMIC_SUB_X2 : SM_Real_Atomics_gfx10 <0x63, "S_BUFFER_ATOMIC_SUB_X2">; -defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Real_Atomics_gfx10 <0x64, "S_BUFFER_ATOMIC_SMIN_X2">; -defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Real_Atomics_gfx10 <0x65, "S_BUFFER_ATOMIC_UMIN_X2">; -defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Real_Atomics_gfx10 <0x66, "S_BUFFER_ATOMIC_SMAX_X2">; -defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Real_Atomics_gfx10 <0x67, "S_BUFFER_ATOMIC_UMAX_X2">; -defm S_BUFFER_ATOMIC_AND_X2 : SM_Real_Atomics_gfx10 <0x68, "S_BUFFER_ATOMIC_AND_X2">; -defm S_BUFFER_ATOMIC_OR_X2 : SM_Real_Atomics_gfx10 <0x69, "S_BUFFER_ATOMIC_OR_X2">; -defm S_BUFFER_ATOMIC_XOR_X2 : SM_Real_Atomics_gfx10 <0x6a, "S_BUFFER_ATOMIC_XOR_X2">; -defm S_BUFFER_ATOMIC_INC_X2 : SM_Real_Atomics_gfx10 <0x6b, "S_BUFFER_ATOMIC_INC_X2">; -defm S_BUFFER_ATOMIC_DEC_X2 : SM_Real_Atomics_gfx10 <0x6c, "S_BUFFER_ATOMIC_DEC_X2">; - -defm S_ATOMIC_SWAP : SM_Real_Atomics_gfx10 <0x80, "S_ATOMIC_SWAP">; -defm S_ATOMIC_CMPSWAP : SM_Real_Atomics_gfx10 <0x81, "S_ATOMIC_CMPSWAP">; -defm S_ATOMIC_ADD : SM_Real_Atomics_gfx10 <0x82, "S_ATOMIC_ADD">; -defm S_ATOMIC_SUB : SM_Real_Atomics_gfx10 <0x83, "S_ATOMIC_SUB">; -defm S_ATOMIC_SMIN : SM_Real_Atomics_gfx10 <0x84, "S_ATOMIC_SMIN">; -defm S_ATOMIC_UMIN : SM_Real_Atomics_gfx10 <0x85, "S_ATOMIC_UMIN">; -defm S_ATOMIC_SMAX : SM_Real_Atomics_gfx10 <0x86, "S_ATOMIC_SMAX">; -defm S_ATOMIC_UMAX : SM_Real_Atomics_gfx10 <0x87, "S_ATOMIC_UMAX">; -defm S_ATOMIC_AND : SM_Real_Atomics_gfx10 <0x88, "S_ATOMIC_AND">; -defm S_ATOMIC_OR : SM_Real_Atomics_gfx10 <0x89, "S_ATOMIC_OR">; -defm S_ATOMIC_XOR : SM_Real_Atomics_gfx10 <0x8a, "S_ATOMIC_XOR">; -defm S_ATOMIC_INC : SM_Real_Atomics_gfx10 <0x8b, "S_ATOMIC_INC">; -defm S_ATOMIC_DEC : SM_Real_Atomics_gfx10 <0x8c, "S_ATOMIC_DEC">; - -defm S_ATOMIC_SWAP_X2 : SM_Real_Atomics_gfx10 <0xa0, "S_ATOMIC_SWAP_X2">; -defm S_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_gfx10 <0xa1, "S_ATOMIC_CMPSWAP_X2">; -defm S_ATOMIC_ADD_X2 : SM_Real_Atomics_gfx10 <0xa2, "S_ATOMIC_ADD_X2">; -defm S_ATOMIC_SUB_X2 : SM_Real_Atomics_gfx10 <0xa3, "S_ATOMIC_SUB_X2">; -defm S_ATOMIC_SMIN_X2 : SM_Real_Atomics_gfx10 <0xa4, "S_ATOMIC_SMIN_X2">; -defm S_ATOMIC_UMIN_X2 : SM_Real_Atomics_gfx10 <0xa5, "S_ATOMIC_UMIN_X2">; -defm S_ATOMIC_SMAX_X2 : SM_Real_Atomics_gfx10 <0xa6, "S_ATOMIC_SMAX_X2">; -defm S_ATOMIC_UMAX_X2 : SM_Real_Atomics_gfx10 <0xa7, "S_ATOMIC_UMAX_X2">; -defm S_ATOMIC_AND_X2 : SM_Real_Atomics_gfx10 <0xa8, "S_ATOMIC_AND_X2">; -defm S_ATOMIC_OR_X2 : SM_Real_Atomics_gfx10 <0xa9, "S_ATOMIC_OR_X2">; -defm S_ATOMIC_XOR_X2 : SM_Real_Atomics_gfx10 <0xaa, "S_ATOMIC_XOR_X2">; -defm S_ATOMIC_INC_X2 : SM_Real_Atomics_gfx10 <0xab, "S_ATOMIC_INC_X2">; -defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_gfx10 <0xac, "S_ATOMIC_DEC_X2">; - -multiclass SM_Real_Discard_gfx10 op, string ps> { +defm S_BUFFER_ATOMIC_SWAP : SM_Real_Atomics_gfx10 <0x40>; +defm S_BUFFER_ATOMIC_CMPSWAP : SM_Real_Atomics_gfx10 <0x41>; +defm S_BUFFER_ATOMIC_ADD : SM_Real_Atomics_gfx10 <0x42>; +defm S_BUFFER_ATOMIC_SUB : SM_Real_Atomics_gfx10 <0x43>; +defm S_BUFFER_ATOMIC_SMIN : SM_Real_Atomics_gfx10 <0x44>; +defm S_BUFFER_ATOMIC_UMIN : SM_Real_Atomics_gfx10 <0x45>; +defm S_BUFFER_ATOMIC_SMAX : SM_Real_Atomics_gfx10 <0x46>; +defm S_BUFFER_ATOMIC_UMAX : SM_Real_Atomics_gfx10 <0x47>; +defm S_BUFFER_ATOMIC_AND : SM_Real_Atomics_gfx10 <0x48>; +defm S_BUFFER_ATOMIC_OR : SM_Real_Atomics_gfx10 <0x49>; +defm S_BUFFER_ATOMIC_XOR : SM_Real_Atomics_gfx10 <0x4a>; +defm S_BUFFER_ATOMIC_INC : SM_Real_Atomics_gfx10 <0x4b>; +defm S_BUFFER_ATOMIC_DEC : SM_Real_Atomics_gfx10 <0x4c>; + +defm S_BUFFER_ATOMIC_SWAP_X2 : SM_Real_Atomics_gfx10 <0x60>; +defm S_BUFFER_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_gfx10 <0x61>; +defm S_BUFFER_ATOMIC_ADD_X2 : SM_Real_Atomics_gfx10 <0x62>; +defm S_BUFFER_ATOMIC_SUB_X2 : SM_Real_Atomics_gfx10 <0x63>; +defm S_BUFFER_ATOMIC_SMIN_X2 : SM_Real_Atomics_gfx10 <0x64>; +defm S_BUFFER_ATOMIC_UMIN_X2 : SM_Real_Atomics_gfx10 <0x65>; +defm S_BUFFER_ATOMIC_SMAX_X2 : SM_Real_Atomics_gfx10 <0x66>; +defm S_BUFFER_ATOMIC_UMAX_X2 : SM_Real_Atomics_gfx10 <0x67>; +defm S_BUFFER_ATOMIC_AND_X2 : SM_Real_Atomics_gfx10 <0x68>; +defm S_BUFFER_ATOMIC_OR_X2 : SM_Real_Atomics_gfx10 <0x69>; +defm S_BUFFER_ATOMIC_XOR_X2 : SM_Real_Atomics_gfx10 <0x6a>; +defm S_BUFFER_ATOMIC_INC_X2 : SM_Real_Atomics_gfx10 <0x6b>; +defm S_BUFFER_ATOMIC_DEC_X2 : SM_Real_Atomics_gfx10 <0x6c>; + +defm S_ATOMIC_SWAP : SM_Real_Atomics_gfx10 <0x80>; +defm S_ATOMIC_CMPSWAP : SM_Real_Atomics_gfx10 <0x81>; +defm S_ATOMIC_ADD : SM_Real_Atomics_gfx10 <0x82>; +defm S_ATOMIC_SUB : SM_Real_Atomics_gfx10 <0x83>; +defm S_ATOMIC_SMIN : SM_Real_Atomics_gfx10 <0x84>; +defm S_ATOMIC_UMIN : SM_Real_Atomics_gfx10 <0x85>; +defm S_ATOMIC_SMAX : SM_Real_Atomics_gfx10 <0x86>; +defm S_ATOMIC_UMAX : SM_Real_Atomics_gfx10 <0x87>; +defm S_ATOMIC_AND : SM_Real_Atomics_gfx10 <0x88>; +defm S_ATOMIC_OR : SM_Real_Atomics_gfx10 <0x89>; +defm S_ATOMIC_XOR : SM_Real_Atomics_gfx10 <0x8a>; +defm S_ATOMIC_INC : SM_Real_Atomics_gfx10 <0x8b>; +defm S_ATOMIC_DEC : SM_Real_Atomics_gfx10 <0x8c>; + +defm S_ATOMIC_SWAP_X2 : SM_Real_Atomics_gfx10 <0xa0>; +defm S_ATOMIC_CMPSWAP_X2 : SM_Real_Atomics_gfx10 <0xa1>; +defm S_ATOMIC_ADD_X2 : SM_Real_Atomics_gfx10 <0xa2>; +defm S_ATOMIC_SUB_X2 : SM_Real_Atomics_gfx10 <0xa3>; +defm S_ATOMIC_SMIN_X2 : SM_Real_Atomics_gfx10 <0xa4>; +defm S_ATOMIC_UMIN_X2 : SM_Real_Atomics_gfx10 <0xa5>; +defm S_ATOMIC_SMAX_X2 : SM_Real_Atomics_gfx10 <0xa6>; +defm S_ATOMIC_UMAX_X2 : SM_Real_Atomics_gfx10 <0xa7>; +defm S_ATOMIC_AND_X2 : SM_Real_Atomics_gfx10 <0xa8>; +defm S_ATOMIC_OR_X2 : SM_Real_Atomics_gfx10 <0xa9>; +defm S_ATOMIC_XOR_X2 : SM_Real_Atomics_gfx10 <0xaa>; +defm S_ATOMIC_INC_X2 : SM_Real_Atomics_gfx10 <0xab>; +defm S_ATOMIC_DEC_X2 : SM_Real_Atomics_gfx10 <0xac>; + +multiclass SM_Real_Discard_gfx10 op> { + defvar ps = NAME; def _IMM_gfx10 : SMEM_Real_gfx10 (ps#_IMM)>; def _SGPR_gfx10 : SMEM_Real_gfx10 (ps#_SGPR)>; def _SGPR_IMM_gfx10 : SMEM_Real_gfx10 (ps#_SGPR_IMM)>; } -defm S_DCACHE_DISCARD : SM_Real_Discard_gfx10 <0x28, "S_DCACHE_DISCARD">; -defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_gfx10 <0x29, "S_DCACHE_DISCARD_X2">; +defm S_DCACHE_DISCARD : SM_Real_Discard_gfx10 <0x28>; +defm S_DCACHE_DISCARD_X2 : SM_Real_Discard_gfx10 <0x29>; } // End SubtargetPredicate = HasScalarAtomics @@ -1165,7 +1156,8 @@ class SMEM_Real_Load_gfx11 op, string ps, string opName, OffsetMode offsets> : SMEM_Real_gfx11(ps # offsets.Variant), opName>; -multiclass SM_Real_Loads_gfx11 op, string ps, string opName> { +multiclass SM_Real_Loads_gfx11 op, string ps> { + defvar opName = !tolower(NAME); def _IMM_gfx11 : SMEM_Real_Load_gfx11; def _SGPR_gfx11 : SMEM_Real_Load_gfx11; def _SGPR_IMM_gfx11 : SMEM_Real_Load_gfx11; @@ -1173,17 +1165,17 @@ Requires<[isGFX11Plus]>; } -defm S_LOAD_B32 : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD", "s_load_b32">; -defm S_LOAD_B64 : SM_Real_Loads_gfx11<0x001, "S_LOAD_DWORDX2", "s_load_b64">; -defm S_LOAD_B128 : SM_Real_Loads_gfx11<0x002, "S_LOAD_DWORDX4", "s_load_b128">; -defm S_LOAD_B256 : SM_Real_Loads_gfx11<0x003, "S_LOAD_DWORDX8", "s_load_b256">; -defm S_LOAD_B512 : SM_Real_Loads_gfx11<0x004, "S_LOAD_DWORDX16", "s_load_b512">; +defm S_LOAD_B32 : SM_Real_Loads_gfx11<0x000, "S_LOAD_DWORD">; +defm S_LOAD_B64 : SM_Real_Loads_gfx11<0x001, "S_LOAD_DWORDX2">; +defm S_LOAD_B128 : SM_Real_Loads_gfx11<0x002, "S_LOAD_DWORDX4">; +defm S_LOAD_B256 : SM_Real_Loads_gfx11<0x003, "S_LOAD_DWORDX8">; +defm S_LOAD_B512 : SM_Real_Loads_gfx11<0x004, "S_LOAD_DWORDX16">; -defm S_BUFFER_LOAD_B32 : SM_Real_Loads_gfx11<0x008, "S_BUFFER_LOAD_DWORD", "s_buffer_load_b32">; -defm S_BUFFER_LOAD_B64 : SM_Real_Loads_gfx11<0x009, "S_BUFFER_LOAD_DWORDX2", "s_buffer_load_b64">; -defm S_BUFFER_LOAD_B128 : SM_Real_Loads_gfx11<0x00a, "S_BUFFER_LOAD_DWORDX4", "s_buffer_load_b128">; -defm S_BUFFER_LOAD_B256 : SM_Real_Loads_gfx11<0x00b, "S_BUFFER_LOAD_DWORDX8", "s_buffer_load_b256">; -defm S_BUFFER_LOAD_B512 : SM_Real_Loads_gfx11<0x00c, "S_BUFFER_LOAD_DWORDX16", "s_buffer_load_b512">; +defm S_BUFFER_LOAD_B32 : SM_Real_Loads_gfx11<0x008, "S_BUFFER_LOAD_DWORD">; +defm S_BUFFER_LOAD_B64 : SM_Real_Loads_gfx11<0x009, "S_BUFFER_LOAD_DWORDX2">; +defm S_BUFFER_LOAD_B128 : SM_Real_Loads_gfx11<0x00a, "S_BUFFER_LOAD_DWORDX4">; +defm S_BUFFER_LOAD_B256 : SM_Real_Loads_gfx11<0x00b, "S_BUFFER_LOAD_DWORDX8">; +defm S_BUFFER_LOAD_B512 : SM_Real_Loads_gfx11<0x00c, "S_BUFFER_LOAD_DWORDX16">; def S_GL1_INV_gfx11 : SMEM_Real_gfx11<0x020, S_GL1_INV>; def S_DCACHE_INV_gfx11 : SMEM_Real_gfx11<0x021, S_DCACHE_INV>; @@ -1196,12 +1188,13 @@ let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?); } -multiclass SM_Real_Probe_gfx11 op, string ps> { +multiclass SM_Real_Probe_gfx11 op> { + defvar ps = NAME; def _IMM_gfx11 : SMEM_Real_Store_gfx11 (ps#_IMM)>; def _SGPR_gfx11 : SMEM_Real_Store_gfx11 (ps#_SGPR)>; def _SGPR_IMM_gfx11 : SMEM_Real_Store_gfx11 (ps#_SGPR_IMM)>; } -defm S_ATC_PROBE : SM_Real_Probe_gfx11 <0x22, "S_ATC_PROBE">; -defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx11 <0x23, "S_ATC_PROBE_BUFFER">; +defm S_ATC_PROBE : SM_Real_Probe_gfx11 <0x22>; +defm S_ATC_PROBE_BUFFER : SM_Real_Probe_gfx11 <0x23>;